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Commits (24)
  • Ben Avison's avatar
    Resync with allocations database · 8934eabd
    Ben Avison authored 
    Detail:
  * Filetype for MJPEG files
  * Extra AUN error
  * Resolved error base clash between AbortRegions and VFPSupport
  * New alias for OS_Byte 221


Version 2.51. Tagged as 'HdrSrc-2_51'
    8934eabd
  • Jeffrey Lee's avatar
    Update VMSAv6 definitions · 625c738d
    Jeffrey Lee authored 
    Detail:
  hdr/MEMM/VMSAv6 - Remove XScale-specific L1_X, L2_X, L2L_X flags. Add L2_S flag. Add definitions for the cache size ID register fields.
Admin:
  Tested on ARM11, Cortex-A7, -A8, -A9, -A15


Version 2.52. Tagged as 'HdrSrc-2_52'
    625c738d
  • Ben Avison's avatar
    Resync with allocations database · 925f3379
    Ben Avison authored 
    Detail:
  Two extra kernel error numbers in NewErrors
  Updated comment in FSNumbers to state filing system prefix used by SDFS

Version 2.53. Tagged as 'HdrSrc-2_53'
    925f3379
  • Ben Avison's avatar
    Resync with allocations database · 2aa15909
    Ben Avison authored 
    Detail:
  Various allocations relating to SPIDriver and SATAFS made public

Version 2.54. Tagged as 'HdrSrc-2_54'
    2aa15909
  • Ben Avison's avatar
    Support for OMAP543x, AM5728 and ADFS 4 · ac8f2a6d
    Ben Avison authored 
    Detail:
  * Complete the Cortex-A7 support which was initially added for RPi 2, to
    allow for builds that only target Cortex-A7. Because Cortex-A15 and
    Cortex-A17 CPUs are indistinguishable architecturally from Cortex-A7
    (all are ARMv7VE with VFPv4, Advanced SIMD v2 and hardware integer divide)
    any such platforms are expected to use Machine=CortexA7. Also bear in
    mind that if we ever support multiple cores on big.LITTLE CPUs, execution
    can move between these core types at runtime, making an assembly time
    option to distinguish between them meaningless!
  * Correct Machines All and All32 to include support for VFPv4
  * Decloak the ATA driver SWI chunk
  * Add a global error allocation for use by the ATA subsystem (placed in
    global space because it propagates into the CD stack)


Version 2.55. Tagged as 'HdrSrc-2_55'
    ac8f2a6d
  • Ben Avison's avatar
    More ADFS 4 support · 5de3a597
    Ben Avison authored 
    Detail:
  * Decloak ATA switcher error base

Retagged as 'HdrSrc-2_55'

Version 2.55. Not tagged
    5de3a597
  • Ben Avison's avatar
    Add a symbol definition for HYP mode · fa17397d
    Ben Avison authored 
    Detail:
  This is the mode used for hypervisor exceptions in ARMv7VE and later.


Version 2.56. Tagged as 'HdrSrc-2_56'
    fa17397d
  • Ben Avison's avatar
    Resync with allocations database · 1e044546
    Ben Avison authored 
    Detail:
  A couple of new error allocations for the sound subsystem

Version 2.57. Tagged as 'HdrSrc-2_57'
    1e044546
  • Ben Avison's avatar
    New compile-time architecture flags: · 9f9d0319
    Ben Avison authored 
      * ARMv7VE (virtualisation extension)
  * ARMv8
  * ARMv8 cryptographic extension
  Machine=RPi builds now targets ARMv8 as well as ARMv6 and ARMv7;
  Machine=CortexA7 builds now set the VE flag; and All and All32 include ARMv8.

Version 2.58. Tagged as 'HdrSrc-2_58'
    9f9d0319
  • Ben Avison's avatar
    Resync with allocations database · e75ac298
    Ben Avison authored 
    Version 2.59. Tagged as 'HdrSrc-2_59'
    e75ac298
  • Jeffrey Lee's avatar
    Optimise DivRem and PSR manipulation macros · bd0ce26f
    Jeffrey Lee authored 
    Detail:
  hdr/Macros - DivRem is now able to use UDIV when building for architectures that support it. A "norem" option is also available, to allow the remainder calculation to be skipped if it's not needed (since we don't get it for free when using UDIV).
  hdr/CPU/Generic32 - PHPSEI, WritePSRc and SetMode now use the ARMv6 CPS instruction where possible, delivering performance gains compared to the equivalent MSR. Where CPS isn't used, WritePSRc now attempts to emit a single MSR instead of the 4 instructions generated by the SCPSR macro.
Admin:
  Tested on Cortex-A15
  PSR manipulation macros trialed on a few different CPU architectures to arrive at the conclusion that CPS is as good or better than MSR


Version 2.60. Tagged as 'HdrSrc-2_60'
    bd0ce26f
  • Jeffrey Lee's avatar
    GET a header dependency · 3074d45c
    Jeffrey Lee authored 
    Detail:
  hdr/Macros - Several macros now depend on Hdr:CPU.Arch, and it's reasonable to assume more architecture-specific optimisations will be made in future, so make sure we GET that header if necessary
Admin:
  Tested on Raspberry Pi
  Fixes issues building components that GET Hdr:Macros but not Hdr:CPU.Arch, e.g. DivRem usage in several HALs


Version 2.61. Tagged as 'HdrSrc-2_61'
    3074d45c
  • Jeffrey Lee's avatar
    Revert change from HdrSrc 2.61 · 03e4d645
    Jeffrey Lee authored 
    Detail:
  hdr/Macros - Remove GET of Hdr:CPU.Arch that was added in HdrSrc 2.61. Closer inspection of the OS sources suggest that only a handful of files were affected by the DivRem breakage, so to avoid HdrSrc turning into a tangled mess of headers that all include each other it's been decided that it's better to stick with the status quo and require users of Hdr:Macros to include Hdr:CPU.Arch as and when necessary (99% of the time Hdr:System will have already pulled it in).
Admin:
  Tested on Raspberry Pi


Version 2.62. Tagged as 'HdrSrc-2_62'
    03e4d645
  • Jeffrey Lee's avatar
    Add new "26" machine type. Simplify ARM2 support. · 7d0f8d91
    Jeffrey Lee authored 
    Detail:
  hdr/Machine/26, hdr/Machine/Machine - Add new "26" machine type, which targets all 26 bit machines/OS versions (running only in 26 bit mode)
  hdr/CPU/Arch - Use ELIF to avoid bracket spam. Remove duplicate CortexA7 case.
  hdr/CPU/Generic26 - Add NOPs to PSR manipulation macros in order to make them ARM2-safe (Generic32 macros are already structured to have suitable NOPs when generating 32bit-neutral code, so it makes sense for Generic26 to take care of ARM2 as well). This removes the need for components which use these macros to insert any manual NOPs, whether for the StrongARM MSR bug or the ARM2 TEQP bug.
  hdr/CPU/Generic32 - Flag the StrongARM MSR NOP diagnostic message as a warning, so the line number can be included in the output, so developers can more easily investigate the issue.
Admin:
  Tested with PlingSystem build


Version 2.63. Tagged as 'HdrSrc-2_63'
    7d0f8d91
  • Steve Revill's avatar
    CortexA7 is missing from the HiResTTX switch. This means on Titanium · 15c9ad3f
    Steve Revill authored 
    MODE 7 doesn't really work because the DVI framer chip can't clock
as low as 13.5MHz for 320x200.

Version 2.64. Tagged as 'HdrSrc-2_64'
    15c9ad3f
  • Jeffrey Lee's avatar
    Add new PSR manipulation macros, optimised for 32bit machines · 71306206
    Jeffrey Lee authored 
    Detail:
  Many of our existing PSR manipulation macros (specifically, ones used for changing mode or controlling interrupts) are based around the code sequences you'd typically use on a 26bit system. Although this has worked well in terms of producing a 32bit version of the OS, it's also left us with macros that can be sub-optimal for 32bit machines, or are inconvenient to use due to the potential of corrupting other PSR flags
  This change adds a new set of macros which are designed and optimised for 32bit-only targets, but can still fall back to 26/32bit neutral or 26bit-only configurations
  hdr/CPU/Generic32:
  - Add the new macros (SEI, CLI, SetModeSEI, SetModeCLI & variants).
  - Improve existing SetMode macro to add 26bit compatibility, and to add an extra optimisation for pre-ARMv6 (emit single MSR if IRQ state is known)
  - Improve SCPSR to allow the source mode to be any 32bit mode
  - Fix conditional 26bit/32bit neutral SCPSR - the 32bit check TEQ corrupts NZCV so we can't do conditional execution on $cond after it (and we've already branched on the opposite condition anyway)
  - Fix 26bit/32bit neutral SCPSR to preserve NZCV when following the MSR code path
  - Make CLRPSR and SETPSR just call through to SCPSR - in terms of output the first two have no advantages over SCPSR
  - Update WritePSRc documentation to reflect that it can now be used in any (non-USR) source mode
  hdr/CPU/Generic26:
  - Update WritePSRc documentation to match Generic32
Admin:
  Tested on Raspberry Pi
  Output of new macros manually checked for various machine types (RPi, Tungsten, All, 26)


Version 2.65. Tagged as 'HdrSrc-2_65'
    71306206
  • Jeffrey Lee's avatar
    Fix SetMode macro · 833b0b02
    Jeffrey Lee authored 
    Detail:
  hdr/CPU/Generic32 - Copy-paste error led to wrong variable name in a conditional block
Admin:
  Tested on Raspberry Pi, Iyonix


Version 2.66. Tagged as 'HdrSrc-2_66'
    833b0b02
  • Ben Avison's avatar
    Resync with allocations database · 76495ac5
    Ben Avison authored 
    Version 2.67. Tagged as 'HdrSrc-2_67'
    76495ac5
  • Ben Avison's avatar
    Resync with allocations database · 69c46a2f
    Ben Avison authored 
    Detail:
  Additional kernel error numbers for Jeffrey Lee

Version 2.68. Tagged as 'HdrSrc-2_68'
    69c46a2f
  • Jeffrey Lee's avatar
    Update VMSAv6 page table definitions · 0b4990ab
    Jeffrey Lee authored 
    Detail:
  hdr/MEMM/VMSAv6 - Add AP_PROM for the "privileged mode ROM" permission. Define the shareable bit for L1 page table entries.
Admin:
  Tested on Raspberry Pi


Version 2.69. Tagged as 'HdrSrc-2_69'
    0b4990ab
  • Ben Avison's avatar
    Resync with allocations database · c1dced2c
    Ben Avison authored 
    Detail:
  Additional error and service call definitions requested by Sprow

Version 2.70. Tagged as 'HdrSrc-2_70'
    c1dced2c
  • Ben Avison's avatar
    Resync with allocations database (extensions to GraphicsV) · eb0df56d
    Ben Avison authored 
    Version 2.71. Tagged as 'HdrSrc-2_71'
    eb0df56d
  • Ben Avison's avatar
    Resync with allocations database (SMP module definitions) · f38dfe08
    Ben Avison authored 
    Version 2.72. Tagged as 'HdrSrc-2_72'
    f38dfe08
  • Jeffrey Lee's avatar
    Fix non-functional teletext on some platforms, and standardise on HiResTTX across the board · bbca0fed
    Jeffrey Lee authored 
    Detail:
  * Neither of our native Cortex-A9 machines natively support 16 colour modes, so HiResTTX must be used since the kernel only supports >16 colour TTX when that option is on.
  * Our Cortex-A8 machines can do 16 colours, but we might as well switch them to HiResTTX as well since they've got plenty of horsepower to render it at that resolution.
  * That just leaves IOMD as the odd one out using low-res TTX. If hardware scrolling or VDU 23,18,1 is used then performance of hi-res TTX doesn't seem to be that much worse than low-res, so for consistency it's probably best to take the performance hit and run all platforms with HiResTTX.
  hdr/Machine/Machine - Updated as above. Also use TTX256 for Cortex-A9 so that the "native" mode 7 will be 256 colour instaed of 16 colour.
Admin:
  Tested on Pandaboard, iMX6, BB-xM, StrongARM RiscPC
  Fixes lack of teletext on Pandaboard + iMX6


Version 2.73. Tagged as 'HdrSrc-2_73'
    bbca0fed
Hide whitespace changes
Inline Side-by-side
Showing with 592 additions and 358 deletions
VersionNum
View file @ bbca0fed
/* (2.50)
/* (2.73)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 2.50
#define Module_MajorVersion_CMHG 2.73
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 02 Feb 2015
#define Module_Date_CMHG 26 Jan 2018
#define Module_MajorVersion "2.50"
#define Module_Version 250
#define Module_MajorVersion "2.73"
#define Module_Version 273
#define Module_MinorVersion ""
#define Module_Date "02 Feb 2015"
#define Module_Date "26 Jan 2018"
#define Module_ApplicationDate "02-Feb-15"
#define Module_ApplicationDate "26-Jan-18"
#define Module_ComponentName "HdrSrc"
#define Module_ComponentPath "castle/RiscOS/Sources/Programmer/HdrSrc"
#define Module_FullVersion "2.50"
#define Module_HelpVersion "2.50 (02 Feb 2015)"
#define Module_LibraryVersionInfo "2:50"
#define Module_FullVersion "2.73"
#define Module_HelpVersion "2.73 (26 Jan 2018)"
#define Module_LibraryVersionInfo "2:73"
hdr/CMOS
View file @ bbca0fed
......@@ -324,16 +324,14 @@ PrintSoundCMOS * TutuCMOS ; give it a meaningful name as well!
; by Mark Taunton for use in 16-bit sound support
VduCMOS # 1 ; &85
; Bit 1 used to be bit 4 of configured Mode, but no longer used now Configure Mode = Configure WimpMode
; so now means screen has not been configured when set.
MonitorNotConfigured * &02
SyncBits * &81 ; bits 0 and 7 for sync type
Sync_Separate * &00
Sync_Composite * &01
Sync_Reserved * &80
Sync_Auto * &81
; Bit 1 free for future use (was bit 4 of configured Mode, but no longer used now configured Mode == WimpMode)
MonitorTypeBits * &7C ; bits 2..6 for monitor type
; 0 => normal
; 1 => multisync
......@@ -342,6 +340,10 @@ MonitorTypeBits * &7C ; bits 2..6 for monitor type
; 4 => Super VGA
; 5 => LCD
; 6 => 3rd party use
; 7 => from MDF (internal use only)
; 8-15 => unallocated, but can be set by the user
; 16 => EDID (invalid pre RISC OS 5.23, taken as 'AUTO')
; 17-30 => unallocated (invalid, taken as 'AUTO')
; 31 => AUTO
MonitorTypeShift * 2
MonitorType0 * &00
......@@ -360,6 +362,7 @@ MonitorTypeC * &30
MonitorTypeD * &34
MonitorTypeE * &38
MonitorTypeF * &3C
MonitorTypeEDID * &40
MonitorTypeAuto * &7C
SyncAutoBit * &80
FontCMOS # 1 ; &86 units of 4K
......
hdr/CPU/Arch
View file @ bbca0fed
......@@ -161,51 +161,53 @@ MchFlg_v5 * 2_00000000000000000000000000000100
MchFlg_v6 * 2_00000000000000000000000000001000
; DBG, DMB, PLI, PLDW and ThumbEE instruction set
MchFlg_v7 * 2_00000000000000000000000000010000
; CRC32, HLT, LDA(EX), SEVL, STL(EX), VMAXNM, VMINNM, VRINT, VSEL
MchFlg_v8 * 2_00000000000000000000000000100000
; SWP and SWPB
MchFlg_a * 2_00000000000000000000000000100000
MchFlg_a * 2_00000000000000000000000001000000
; Hardware FPA - FPA10 if v2 (ARM3); FPA11 if v3 (ARM700 or ARM7500FE)
MchFlg_F * 2_00000000000000000000000001000000
MchFlg_F * 2_00000000000000000000000010000000
; Withdrawal of 26-bit modes
MchFlg_G * 2_00000000000000000000000010000000
MchFlg_G * 2_00000000000000000000000100000000
; 64+32x32 bit MLA and MUL
MchFlg_M * 2_00000000000000000000000100000000
MchFlg_M * 2_00000000000000000000001000000000
; BX and Thumb - Thumbv1 if ARMv4; Thumbv2 if ARMv5; Thumbv3 if ARMv6
; no established terminology for later revisions
MchFlg_T * 2_00000000000000000000001000000000
MchFlg_T * 2_00000000000000000000010000000000
; Enhanced DSP extension - 32+16*16, 33+32*16, 64+16*16 MLA and MUL,
; saturated ADD/SUB
MchFlg_E * 2_00000000000000000000010000000000
MchFlg_E * 2_00000000000000000000100000000000
; PLD, LDRD/STRD, MRRC/MCRR
MchFlg_P * 2_00000000000000000000100000000000
MchFlg_P * 2_00000000000000000001000000000000
; Intel XScale extensions - 40+32*32, 40+16*16, 40+16*16+16*16 MLA,
; mini data cache
MchFlg_X * 2_00000000000000000001000000000000
MchFlg_X * 2_00000000000000000010000000000000
; Jazelle extension - BXJ
MchFlg_J * 2_00000000000000000010000000000000
MchFlg_J * 2_00000000000000000100000000000000
; Multiprocessing extensions - CLREX, YIELD, WFE, WFI, SEV, SMI and
; security extensions
MchFlg_K * 2_00000000000000000100000000000000
MchFlg_K * 2_00000000000000001000000000000000
; Thumb 2 and more - MOVW, MOVH, bitfield operations, DSB, ISB,
; 8/16/64 bit LDR/STREX, LDRT/STRT for halfwords and signed bytes, 32-32*32 MLS
MchFlg_T2 * 2_00000000000000001000000000000000
MchFlg_T2 * 2_00000000000000010000000000000000
; Virtualisation extension - ERET, HVC, banked MRS and MSR and hardware divide
MchFlg_VE * 2_00000000000000100000000000000000
; Cryptographic extension - AES, SHA1, SHA256
MchFlg_C * 2_00000000000001000000000000000000
; VFP - VFPv1 if ARMv5T; VFPv2 if ARMv5TE or ARMv6; VFPv3 if ARMv7
MchFlg_V * 2_00000000000000010000000000000000
MchFlg_V * 2_00000000000010000000000000000000
; VFP D variant (double precision)
MchFlg_VD * 2_00000000000000100000000000000000
MchFlg_VD * 2_00000000000100000000000000000000
; VFP 32 double-precision registers variant
MchFlg_V32 * 2_00000000000001000000000000000000
MchFlg_V32 * 2_00000000001000000000000000000000
; VFP half-precision variant
MchFlg_VH * 2_00000000000010000000000000000000
MchFlg_VH * 2_00000000010000000000000000000000
; VFPv4 - fused multiply-accumulate
MchFlg_Vv4 * 2_00000000000100000000000000000000
MchFlg_Vv4 * 2_00000000100000000000000000000000
; Advanced SIMD extensions - integer only if no VFP; FP half or single
; precision options mirror the VFP options
MchFlg_A * 2_00000000001000000000000000000000
MchFlg_A * 2_00000010000000000000000000000000
; Remaining flags reserved for future use
;MchFlg_ * 2_00000000010000000000000000000000
;MchFlg_ * 2_00000000100000000000000000000000
;MchFlg_ * 2_00000001000000000000000000000000
;MchFlg_ * 2_00000010000000000000000000000000
;MchFlg_ * 2_00000100000000000000000000000000
;MchFlg_ * 2_00001000000000000000000000000000
;MchFlg_ * 2_00010000000000000000000000000000
......@@ -221,6 +223,7 @@ MchFlgs_v5T * MchFlgs_v4T :OR: MchFlg_v5
MchFlgs_v5TE * MchFlgs_v5T :OR: MchFlg_E :OR: MchFlg_P
MchFlgs_v6 * MchFlgs_v5TE :OR: MchFlg_v6 :OR: MchFlg_J
MchFlgs_v7 * MchFlgs_v6 :OR: MchFlg_v7 :OR: MchFlg_K :OR: MchFlg_T2
MchFlgs_v8 * (MchFlgs_v7 :AND: :NOT: MchFlg_a) :OR: MchFlg_v8 :OR: MchFlg_VE :OR: MchFlg_V :OR: MchFlg_VD :OR: MchFlg_V32 :OR: MchFlg_VH :OR: MchFlg_Vv4 :OR: MchFlg_A
GBLA MchFlgs_Cumulative
MchFlgs_Cumulative SETA 0
......@@ -232,193 +235,103 @@ $lab ArchitectureOption $arch
LCLA MchFlgs
[ "$arch" = "v2"
MchFlgs SETA 0
|
[ "$arch" = "v2a"
ELIF "$arch" = "v2a"
MchFlgs SETA MchFlg_a
|
[ "$arch" = "v2a_FPA"
ELIF "$arch" = "v2a_FPA"
MchFlgs SETA MchFlg_a :OR: MchFlg_F
|
[ "$arch" = "v3"
ELIF "$arch" = "v3"
MchFlgs SETA MchFlgs_v3
|
[ "$arch" = "v3_FPA"
ELIF "$arch" = "v3_FPA"
MchFlgs SETA MchFlgs_v3 :OR: MchFlg_F
|
[ "$arch" = "v3G"
ELIF "$arch" = "v3G"
MchFlgs SETA MchFlgs_v3 :OR: MchFlg_G
|
[ "$arch" = "v3M"
ELIF "$arch" = "v3M"
MchFlgs SETA MchFlgs_v3 :OR: MchFlg_M
|
[ "$arch" = "v4xM"
ELIF "$arch" = "v4xM"
MchFlgs SETA MchFlgs_v4 :AND: :NOT: MchFlg_M
|
[ "$arch" = "v4"
ELIF "$arch" = "v4"
MchFlgs SETA MchFlgs_v4
|
[ "$arch" = "v4TxM"
ELIF "$arch" = "v4TxM"
MchFlgs SETA MchFlgs_v4T :AND: :NOT: MchFlg_M
|
[ "$arch" = "v4T"
ELIF "$arch" = "v4T"
MchFlgs SETA MchFlgs_v4T
|
[ "$arch" = "v5xM"
ELIF "$arch" = "v5xM"
MchFlgs SETA MchFlgs_v5T :AND: :NOT: (MchFlg_M :OR: MchFlg_T)
|
[ "$arch" = "v5"
ELIF "$arch" = "v5"
MchFlgs SETA MchFlgs_v5T :AND: :NOT: MchFlg_T
|
[ "$arch" = "v5TxM"
ELIF "$arch" = "v5TxM"
MchFlgs SETA MchFlgs_v5T :AND: :NOT: MchFlg_M
|
[ "$arch" = "v5T"
ELIF "$arch" = "v5T"
MchFlgs SETA MchFlgs_v5T
|
[ "$arch" = "v5T_VFP1"
ELIF "$arch" = "v5T_VFP1"
MchFlgs SETA MchFlgs_v5T :OR: MchFlg_V
|
[ "$arch" = "v5T_VFP1D"
ELIF "$arch" = "v5T_VFP1D"
MchFlgs SETA MchFlgs_v5T :OR: MchFlg_V :OR: MchFlg_VD
|
[ "$arch" = "v5TExP"
ELIF "$arch" = "v5TExP"
MchFlgs SETA MchFlgs_v5TE :AND: :NOT: MchFlg_P
|
[ "$arch" = "v5TE"
ELIF "$arch" = "v5TE"
MchFlgs SETA MchFlgs_v5TE
|
[ "$arch" = "v5TEX"
ELIF "$arch" = "v5TEX"
MchFlgs SETA MchFlgs_v5TE :OR: MchFlg_X
|
[ "$arch" = "v5TE_VFP2"
ELIF "$arch" = "v5TE_VFP2"
MchFlgs SETA MchFlgs_v5TE :OR: MchFlg_V
|
[ "$arch" = "v5TE_VFP2D"
ELIF "$arch" = "v5TE_VFP2D"
MchFlgs SETA MchFlgs_v5TE :OR: MchFlg_V :OR: MchFlg_VD
|
[ "$arch" = "v5TEJ"
ELIF "$arch" = "v5TEJ"
MchFlgs SETA MchFlgs_v5TE :OR: MchFlg_J
|
[ "$arch" = "v5TEJ_VFP2"
ELIF "$arch" = "v5TEJ_VFP2"
MchFlgs SETA MchFlgs_v5TE :OR: MchFlg_J :OR: MchFlg_V
|
[ "$arch" = "v5TEJ_VFP2D"
ELIF "$arch" = "v5TEJ_VFP2D"
MchFlgs SETA MchFlgs_v5TE :OR: MchFlg_J :OR: MchFlg_V :OR: MchFlg_VD
|
[ "$arch" = "v6"
ELIF "$arch" = "v6"
MchFlgs SETA MchFlgs_v6
|
[ "$arch" = "v6_VFP2"
ELIF "$arch" = "v6_VFP2"
MchFlgs SETA MchFlgs_v6 :OR: MchFlg_V
|
[ "$arch" = "v6_VFP2D"
ELIF "$arch" = "v6_VFP2D"
MchFlgs SETA MchFlgs_v6 :OR: MchFlg_V :OR: MchFlg_VD
|
[ "$arch" = "v6K"
ELIF "$arch" = "v6K"
MchFlgs SETA MchFlgs_v6 :OR: MchFlg_K
|
[ "$arch" = "v6K_VFP2"
ELIF "$arch" = "v6K_VFP2"
MchFlgs SETA MchFlgs_v6 :OR: MchFlg_K :OR: MchFlg_V
|
[ "$arch" = "v6K_VFP2D"
ELIF "$arch" = "v6K_VFP2D"
MchFlgs SETA MchFlgs_v6 :OR: MchFlg_K :OR: MchFlg_V :OR: MchFlg_VD
|
[ "$arch" = "v6T2"
ELIF "$arch" = "v6T2"
MchFlgs SETA MchFlgs_v6 :OR: MchFlg_T2
|
[ "$arch" = "v6T2_VFP2"
ELIF "$arch" = "v6T2_VFP2"
MchFlgs SETA MchFlgs_v6 :OR: MchFlg_T2 :OR: MchFlg_V
|
[ "$arch" = "v6T2_VFP2D"
ELIF "$arch" = "v6T2_VFP2D"
MchFlgs SETA MchFlgs_v6 :OR: MchFlg_T2 :OR: MchFlg_V :OR: MchFlg_VD
|
[ "$arch" = "v7"
ELIF "$arch" = "v7"
MchFlgs SETA MchFlgs_v7
|
[ "$arch" = "v7_VFP3"
ELIF "$arch" = "v7_VFP3"
MchFlgs SETA MchFlgs_v7 :OR: MchFlg_V
|
[ "$arch" = "v7_VFP3D"
ELIF "$arch" = "v7_VFP3D"
MchFlgs SETA MchFlgs_v7 :OR: MchFlg_V :OR: MchFlg_VD
|
[ "$arch" = "v7_VFP3D32"
ELIF "$arch" = "v7_VFP3D32"
MchFlgs SETA MchFlgs_v7 :OR: MchFlg_V :OR: MchFlg_VD :OR: MchFlg_V32
|
[ "$arch" = "v7_VFP3H"
ELIF "$arch" = "v7_VFP3H"
MchFlgs SETA MchFlgs_v7 :OR: MchFlg_V :OR: MchFlg_VH
|
[ "$arch" = "v7_VFP3DH"
ELIF "$arch" = "v7_VFP3DH"
MchFlgs SETA MchFlgs_v7 :OR: MchFlg_V :OR: MchFlg_VD :OR: MchFlg_VH
|
[ "$arch" = "v7_VFP3D32H"
ELIF "$arch" = "v7_VFP3D32H"
MchFlgs SETA MchFlgs_v7 :OR: MchFlg_V :OR: MchFlg_VD :OR: MchFlg_V32 :OR: MchFlg_VH
|
[ "$arch" = "v7_SIMD"
ELIF "$arch" = "v7_SIMD"
MchFlgs SETA MchFlgs_v7 :OR: MchFlg_A
|
[ "$arch" = "v7_VFP3_SIMD"
ELIF "$arch" = "v7_VFP3_SIMD"
MchFlgs SETA MchFlgs_v7 :OR: MchFlg_V :OR: MchFlg_A
|
[ "$arch" = "v7_VFP3D32_SIMD"
ELIF "$arch" = "v7_VFP3D32_SIMD"
MchFlgs SETA MchFlgs_v7 :OR: MchFlg_V :OR: MchFlg_VD :OR: MchFlg_V32 :OR: MchFlg_A
|
[ "$arch" = "v7_VFP3H_SIMD"
ELIF "$arch" = "v7_VFP3H_SIMD"
MchFlgs SETA MchFlgs_v7 :OR: MchFlg_V :OR: MchFlg_VH :OR: MchFlg_A
|
[ "$arch" = "v7_VFP3D32H_SIMD"
ELIF "$arch" = "v7_VFP3D32H_SIMD"
MchFlgs SETA MchFlgs_v7 :OR: MchFlg_V :OR: MchFlg_VD :OR: MchFlg_V32 :OR: MchFlg_VH :OR: MchFlg_A
|
[ "$arch" = "v7_VFP4D32_SIMD"
MchFlgs SETA MchFlgs_v7 :OR: MchFlg_V :OR: MchFlg_VD :OR: MchFlg_V32 :OR: MchFlg_VH :OR: MchFlg_Vv4 :OR: MchFlg_A
ELIF "$arch" = "v7VE_VFP4D32_SIMD"
MchFlgs SETA MchFlgs_v7 :OR: MchFlg_VE :OR: MchFlg_V :OR: MchFlg_VD :OR: MchFlg_V32 :OR: MchFlg_VH :OR: MchFlg_Vv4 :OR: MchFlg_A
ELIF "$arch" = "v8"
MchFlgs SETA MchFlgs_v8
|
! 1, "Unrecognised architecture: $arch"
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
MchFlgs_Cumulative SETA MchFlgs_Cumulative :OR: MchFlgs
MchFlgs_CumulativeNOT SETA MchFlgs_CumulativeNOT :OR: :NOT: MchFlgs
MEND
......@@ -427,60 +340,48 @@ MchFlgs_CumulativeNOT SETA MchFlgs_CumulativeNOT :OR: :NOT: MchFlgs
ArchitectureOption v2
ArchitectureOption v2a
ArchitectureOption v2a_FPA
|
[ "$Machine" = "32" ; basic 32-bit capable machines (used for many ARM7TDMI and ARM9 ports)
ELIF "$Machine" = "26" ; All 26-bit capable machines, running in 26-bit mode
ArchitectureOption v2
ArchitectureOption v2a
ArchitectureOption v2a_FPA
ArchitectureOption v3
ArchitectureOption v3_FPA
ArchitectureOption v4
ELIF "$Machine" = "32" ; basic 32-bit capable machines (used for many ARM7TDMI and ARM9 ports)
ArchitectureOption v3
ArchitectureOption v3_FPA
ArchitectureOption v4
ArchitectureOption v4T
|
[ "$Machine" = "IOMD" ; 32-bit IOMD-class machines ARM6/ARM7/StrongARM
ELIF "$Machine" = "IOMD" ; 32-bit IOMD-class machines ARM6/ARM7/StrongARM
ArchitectureOption v3
ArchitectureOption v3_FPA
ArchitectureOption v4
|
[ "$Machine" = "Tungsten" ; Iyonix PC
ELIF "$Machine" = "Tungsten" ; Iyonix PC
ArchitectureOption v5TEX
|
[ "$Machine" = "ARM11ZF"
ELIF "$Machine" = "ARM11ZF"
ArchitectureOption v6K_VFP2D
|
[ "$Machine" = "RPi" ; Raspberry Pi versions are similar enough that one ROM can handle two architectures
ELIF "$Machine" = "RPi" ; Raspberry Pi versions are similar enough that one ROM can handle three architectures
ArchitectureOption v6K_VFP2D
ArchitectureOption v7_VFP4D32_SIMD
|
[ "$Machine" = "CortexA7" ; Cortex A7
ArchitectureOption v7_VFP4D32_SIMD
|
[ "$Machine" = "CortexA8" ; Cortex A8, e.g. TI OMAP35xx
ArchitectureOption v7VE_VFP4D32_SIMD
ArchitectureOption v8
ELIF "$Machine" = "CortexA7" ; Cortex A7, A15 or A17, e.g. BCM2836, TI OMAP543x, TI AM5728
ArchitectureOption v7VE_VFP4D32_SIMD
ELIF "$Machine" = "CortexA8" ; Cortex A8, e.g. TI OMAP35xx
ArchitectureOption v7_VFP3D32_SIMD
|
[ "$Machine" = "CortexA9" ; Cortex A9
ELIF "$Machine" = "CortexA9" ; Cortex A9, e.g. TI OMAP44xx, Freescale i.MX6
ArchitectureOption v7_VFP3D32H_SIMD
|
[ "$Machine" = "All" ; if the target code is required to run on
ELIF "$Machine" = "All" ; if the target code is required to run on
; any RISC OS machine
ArchitectureOption v2
ArchitectureOption v2a_FPA
ArchitectureOption v7_VFP3D32H_SIMD
|
[ "$Machine" = "All32" ; if the target code is required to run on
ArchitectureOption v8
ELIF "$Machine" = "All32" ; if the target code is required to run on
; any 32-bit capable RISC OS machine
ArchitectureOption v3
ArchitectureOption v3_FPA
ArchitectureOption v7_VFP3D32H_SIMD
ArchitectureOption v8
|
! 1, "Unrecognised machine: $Machine"
]
]
]
]
]
]
]
]
]
]
]
GBLL SupportARMv3
......@@ -508,6 +409,11 @@ SupportARMv7 SETL (MchFlgs_Cumulative :AND: MchFlg_v7) > 0
GBLL NoARMv7
NoARMv7 SETL (MchFlgs_CumulativeNOT :AND: MchFlg_v7) > 0
GBLL SupportARMv8
SupportARMv8 SETL (MchFlgs_Cumulative :AND: MchFlg_v8) > 0
GBLL NoARMv8
NoARMv8 SETL (MchFlgs_CumulativeNOT :AND: MchFlg_v8) > 0
GBLL SupportARMa
SupportARMa SETL (MchFlgs_Cumulative :AND: MchFlg_a) > 0
GBLL NoARMa
......@@ -563,6 +469,16 @@ SupportARMT2 SETL (MchFlgs_Cumulative :AND: MchFlg_T2) > 0
GBLL NoARMT2
NoARMT2 SETL (MchFlgs_CumulativeNOT :AND: MchFlg_T2) > 0
GBLL SupportARMVE
SupportARMVE SETL (MchFlgs_Cumulative :AND: MchFlg_VE) > 0
GBLL NoARMVE
NoARMVE SETL (MchFlgs_CumulativeNOT :AND: MchFlg_VE) > 0
GBLL SupportARMC
SupportARMC SETL (MchFlgs_Cumulative :AND: MchFlg_C) > 0
GBLL NoARMC
NoARMC SETL (MchFlgs_CumulativeNOT :AND: MchFlg_C) > 0
GBLL SupportARMV
SupportARMV SETL (MchFlgs_Cumulative :AND: MchFlg_V) > 0
GBLL NoARMV
......
hdr/CPU/Generic26
View file @ bbca0fed
......@@ -334,6 +334,11 @@ $label RestPSR $reg, $cond, $fields
! 0, "Unpredictable behaviour due to deprecated RestPSR fields parameter"
]
$label TEQ$cond.P pc, $reg
[ NoARMa :LAND: "$fields"<>"f"
; Assume mode may be changing, emit NOP for ARM2
! 0, "RestPSR inserting NOP for ARM2 TEQP bug", 1
NOP
]
MEND
; ****************************************************
......@@ -361,6 +366,10 @@ $label
MOV$cond $srcreg, pc
ORR$cond $regtmp, $srcreg, #($set) :OR: ($clr)
TEQ$cond.P $regtmp, #$clr
]
[ NoARMa :LAND: ((($set) :OR: ($clr)) :AND: M_bits) <> 0
! 0, "SCPSR inserting NOP for ARM2 TEQP bug", 1
NOP
]
MEND
......@@ -387,6 +396,10 @@ srcreg SETS "$oldpsr"
$label MOV$cond $srcreg, pc
ORR$cond $regtmp, $srcreg, #$bits
TEQ$cond.P $regtmp, #0
[ NoARMa :LAND: (($bits) :AND: M_bits) <> 0
! 0, "SETPSR inserting NOP for ARM2 TEQP bug", 1
NOP
]
MEND
; **************************************************
......@@ -411,6 +424,10 @@ srcreg SETS "$oldpsr"
]
$label MOV$cond $srcreg, pc
TEQ$cond.P $srcreg, #$bits
[ NoARMa :LAND: (($bits) :AND: M_bits) <> 0
! 0, "TOGPSR inserting NOP for ARM2 TEQP bug", 1
NOP
]
MEND
; ***********************************************
......@@ -425,26 +442,37 @@ $label MOV$cond $oldpsr, pc
|
$label TEQ$cond.P $regtog, pc
]
[ NoARMa
! 0, "TOGPSRR inserting NOP for ARM2 TEQP bug", 1
NOP
]
MEND
; *************************************************
; *** WritePSRc - Set the PSR control bits to ***
; *** an absolute value. ***
; *** Sets I,F,M[0:1], corrupts NZVC. ***
; *** Preserves 32-bitness. ***
; *** Only use in IRQ26/32,FIQ26/32,SVC26/32 ***
; *** Ignored in USR modes, illegal in others ***
; *** Use instead of TEQP PC,#$value ***
; *************************************************
; ***************************************************
; *** WritePSRc - Set the PSR control bits to ***
; *** an absolute value. ***
; *** Sets I,F,M[0:3], corrupts NZVC. ***
; *** Preserves 32-bitness. Ignored in USR mode. ***
; *** PSR is specified as 26bit form, so only ***
; *** USR/IRQ/FIQ/SVC can be used as dest mode, ***
; *** but source can be any non-USR mode ***
; *** (M[2:3] will be cleared) ***
; *** Use instead of TEQP PC,#$value ***
; ***************************************************
MACRO
$label WritePSRc $value, $regtmp, $cond, $oldpsr
[ ($value :AND::NOT: (I_bit+F_bit+SVC_mode)) <> 0
! 1, "Illegal flags for WritePSRc"
]
$label
[ "$oldpsr" <> ""
SavePSR $oldpsr, $cond
]
$label TEQ$cond.P PC, #$value
TEQ$cond.P PC, #$value
[ NoARMa
! 0, "WritePSRc inserting NOP for ARM2 TEQP bug", 1
NOP
]
MEND
] ; No32bitCode
......
hdr/CPU/Generic32
View file @ bbca0fed
......@@ -67,6 +67,7 @@ IRQ32_mode * 2_10010
SVC32_mode * 2_10011
MON32_mode * 2_10110
ABT32_mode * 2_10111
HYP32_mode * 2_11010
UND32_mode * 2_11011
SYS32_mode * 2_11111
......@@ -92,14 +93,33 @@ r13_und RN 13
r14_und RN 14
lr_und RN 14
[ :LNOT: No32bitCode
; 32 bit versions of the macros in Generic26
GBLA CPU32_bits
GBLA CPU32_set
GBLA CPU32_clr
; ***************************************************
; *** IFto32 - Convert I/F/IF/FI string to ***
; *** I32_bit+F32_bit flags in variable psr32 ***
; ***************************************************
MACRO
$psr32 IFto32 $if
LCLS upper
upper SETS :UPPERCASE: "$if"
[ "$upper" = "I"
$psr32 SETA I32_bit
ELIF "$upper" = "F"
$psr32 SETA F32_bit
ELIF "$upper" = "IF" :LOR: "$upper" = "FI"
$psr32 SETA I32_bit+F32_bit
|
! 1, "Unsupported interrupt flags"
]
MEND
[ :LNOT: No32bitCode
; 32 bit versions of the macros in Generic26
; ***************************************************
; *** PSRto32 - Convert a PSR constant to a ***
; *** 32-bit PSR value in variable psr32 ***
......@@ -139,49 +159,7 @@ $label MSR$cond CPSR_f, #0
; ***********************************************
MACRO
$label CLRPSR $bits, $regtmp, $cond, $oldpsr
LCLS srcreg
[ "$oldpsr"=""
srcreg SETS "$regtmp"
|
srcreg SETS "$oldpsr"
]
CPU32_bits PSRto32 $bits ; Map to 32 bit PSR
[ NoARMv3
$label
[ "$cond"<>"" :LAND: "$cond"<>"AL"
LCLS rcc
rcc SETS :REVERSE_CC:"$cond"
B$rcc %FT02 ; Go round when $cond-itional
]
MOV $srcreg, pc ; Snapshot 26-bit PSR
MRS $srcreg, CPSR ; Snapshot 32-bit PSR, or NOP pre ARMv3
TEQ r0, r0 ; Set Z
MSR CPSR_f, #0 ; Clear Z if ARMv3 or later
BNE %FT01
BIC $regtmp, $srcreg, #$bits
TEQP $regtmp, #0
B %FT02
01
[ (CPU32_bits :AND: &F0000000) <> 0 :LAND: (CPU32_bits :AND: &F0) <> 0
; Can't be expressed as a single ARM immediate constant
BIC $regtmp, $srcreg, #CPU32_bits :AND: &F0000000
BIC $regtmp, $regtmp, #CPU32_bits :AND: &0FFFFFFF
|
BIC $regtmp, $srcreg, #CPU32_bits
]
somemsr AL, CPSR, $regtmp, CPU32_bits
02
|
$label MRS$cond $srcreg, CPSR
[ (CPU32_bits :AND: &F0000000) <> 0 :LAND: (CPU32_bits :AND: &F0) <> 0
; Can't be expressed as a single ARM immediate constant
BIC$cond $regtmp, $srcreg, #CPU32_bits :AND: &F0000000
BIC$cond $regtmp, $regtmp, #CPU32_bits :AND: &0FFFFFFF
|
BIC$cond $regtmp, $srcreg, #CPU32_bits
]
somemsr $cond, CPSR, $regtmp, CPU32_bits, unsafe
]
$label SCPSR 0, $bits, $regtmp, $cond, $oldpsr
MEND
; **************************************************
......@@ -228,7 +206,14 @@ $label
B %FT02
01
]
[ "$regtmp" = "" :LOR: StrongARM_MSR_bug
[ :LNOT: NoARMv6
; CPS is quicker than MSR
; If there's a high probability of IRQs already being disabled, we can
; save even more time by branching over the CPS. But for now assume IRQs
; will mostly be on.
MRS $usereg, CPSR
CPSID i
ELIF "$regtmp" = "" :LOR: StrongARM_MSR_bug
MRS $usereg, CPSR
TST $usereg, #I32_bit ; is I32_bit set?
ORREQ $usereg, $usereg, #I32_bit ; no, then set it
......@@ -372,6 +357,10 @@ $label SCPSR $set, $clr, $regtmp, $cond, $oldpsr
LCLS srcreg
CPU32_set PSRto32 $set
CPU32_clr PSRto32 $clr
[ :LNOT: No32bitCode :LAND: ((CPU32_set :OR: CPU32_clr) :AND: 3) <> 0
; If 32bit modes are supported and we're changing mode, make sure we clear bits 2 and 3 of the mode so we can safely switch from ABT/UND/SYS to SVC/IRQ/etc.
CPU32_clr SETA CPU32_clr :OR: 12
]
[ "$oldpsr"=""
srcreg SETS "$regtmp"
|
......@@ -393,34 +382,34 @@ rcc SETS :REVERSE_CC:"$cond"
MSR CPSR_f, #0 ; Clear Z if ARMv3 or later
BNE %FT01
[ (($set) :OR: ($clr)) = ARM_CC_Mask
TEQ$cond.P pc, #$set ; All change, so skip the clear operation
TEQP pc, #$set ; All change, so skip the clear operation
|
ORR$cond $regtmp, $srcreg, #($set) :OR: ($clr)
TEQ$cond.P $regtmp, #$clr
ORR $regtmp, $srcreg, #($set) :OR: ($clr)
TEQP $regtmp, #$clr
]
B %FT02
01
[ (CPU32_set :AND: &F0000000) <> 0 :LAND: (CPU32_set :AND: &F0) <> 0
ORR$cond $regtmp, $srcreg, #CPU32_set :AND: &F0000000
ORR$cond $regtmp, $regtmp, #CPU32_set :AND: &0FFFFFFF
ORR $regtmp, $srcreg, #CPU32_set :AND: &F0000000
ORR $regtmp, $regtmp, #CPU32_set :AND: &0FFFFFFF
srcreg SETS "$regtmp"
|
[ CPU32_set <> 0
ORR$cond $regtmp, $srcreg, #CPU32_set
ORR $regtmp, $srcreg, #CPU32_set
srcreg SETS "$regtmp"
]
]
[ (CPU32_clr :AND: &F0000000) <> 0 :LAND: (CPU32_clr :AND: &F0) <> 0
BIC$cond $regtmp, $srcreg, #CPU32_clr :AND: &F0000000
BIC$cond $regtmp, $regtmp, #CPU32_clr :AND: &0FFFFFFF
BIC $regtmp, $srcreg, #CPU32_clr :AND: &F0000000
BIC $regtmp, $regtmp, #CPU32_clr :AND: &0FFFFFFF
srcreg SETS "$regtmp"
|
[ CPU32_clr <> 0
BIC$cond $regtmp, $srcreg, #CPU32_clr
BIC $regtmp, $srcreg, #CPU32_clr
srcreg SETS "$regtmp"
]
]
somemsr $cond, CPSR, $srcreg, CPU32_set:OR:CPU32_clr, unsafe
somemsr AL, CPSR, $srcreg, CPU32_set:OR:CPU32_clr:OR:&F0000000
02
|
$label MRS$cond $srcreg, CPSR
......@@ -537,49 +526,7 @@ $label MSR$cond CPSR_f, #C_bit
; ************************************************
MACRO
$label SETPSR $bits, $regtmp, $cond, $oldpsr
LCLS srcreg
[ "$oldpsr"=""
srcreg SETS "$regtmp"
|
srcreg SETS "$oldpsr"
]
CPU32_bits PSRto32 $bits ; Map to 32 bit PSR
[ NoARMv3
$label
[ "$cond"<>"" :LAND: "$cond"<>"AL"
LCLS rcc
rcc SETS :REVERSE_CC:"$cond"
B$rcc %FT02 ; Go round when $cond-itional
]
MOV $srcreg, pc ; Snapshot 26-bit PSR
MRS $srcreg, CPSR ; Snapshot 32-bit PSR, or NOP pre ARMv3
TEQ r0, r0 ; Set Z
MSR CPSR_f, #0 ; Clear Z if ARMv3 or later
BNE %FT01
ORR $regtmp, $srcreg, #$bits
TEQP $regtmp, #0
B %FT02
01
[ (CPU32_bits :AND: &F0000000) <> 0 :LAND: (CPU32_bits :AND: &F0) <> 0
; Can't be expressed as a single ARM immediate constant
ORR $regtmp, $srcreg, #CPU32_bits :AND: &F0000000
ORR $regtmp, $regtmp, #CPU32_bits :AND: &0FFFFFFF
|
ORR $regtmp, $srcreg, #CPU32_bits
]
somemsr AL, CPSR, $regtmp, CPU32_bits
02
|
$label MRS$cond $srcreg, CPSR
[ (CPU32_bits :AND: &F0000000) <> 0 :LAND: (CPU32_bits :AND: &F0) <> 0
; Can't be expressed as a single ARM immediate constant
ORR$cond $regtmp, $srcreg, #CPU32_bits :AND: &F0000000
ORR$cond $regtmp, $regtmp, #CPU32_bits :AND: &0FFFFFFF
|
ORR$cond $regtmp, $srcreg, #CPU32_bits
]
somemsr $cond, CPSR, $regtmp, CPU32_bits, unsafe
]
$label SCPSR $bits, 0, $regtmp, $cond, $oldpsr
MEND
; **************************************************
......@@ -683,21 +630,42 @@ $label MRS$cond $srcreg, CPSR
]
MEND
; *************************************************
; *** WritePSRc - Set the PSR control bits to ***
; *** an absolute value. ***
; *** Sets I,F,M[0:1], corrupts NZVC. ***
; *** Preserves 32-bitness. ***
; *** Only use in IRQ26/32,FIQ26/32,SVC26/32 ***
; *** Ignored in USR modes, illegal in others ***
; *** Use instead of TEQP PC,#$value ***
; *************************************************
; ***************************************************
; *** WritePSRc - Set the PSR control bits to ***
; *** an absolute value. ***
; *** Sets I,F,M[0:3], corrupts NZVC. ***
; *** Preserves 32-bitness. Ignored in USR mode. ***
; *** PSR is specified as 26bit form, so only ***
; *** USR/IRQ/FIQ/SVC can be used as dest mode, ***
; *** but source can be any non-USR mode ***
; *** (M[2:3] will be cleared) ***
; *** Use instead of TEQP PC,#$value ***
; ***************************************************
MACRO
$label WritePSRc $value, $regtmp, $cond, $oldpsr
[ ($value :AND::NOT: (I_bit+F_bit+SVC_mode)) <> 0
! 1, "Illegal flags for WritePSRc"
]
[ No26bitCode
; We only care about 32bit (non-thumb) processor modes
; Write the PSR directly to avoid unnecessary bloat from SCPSR
$label
CPU32_bits PSRto32 $value
[ "$oldpsr" <> ""
MRS$cond $oldpsr, CPSR
]
[ NoARMv6 :LOR: ((CPU32_bits :AND: (I32_bit+F32_bit)) <> 0) :LOR: (("$cond" <> "") :LAND: ("$cond" <> "AL"))
MSR$cond CPSR_c, #CPU32_bits :OR: USR32_mode
[ "$cond" <> "" :LAND: "$cond" <> "AL" :LAND: StrongARM_MSR_bug
NOP
]
|
; CPS is faster than CPSR_c, but is limited in that if I+F are being set they must take the same value
CPSIE if, #(CPU32_bits :AND: M32_bits) :OR: USR32_mode
]
|
$label SCPSR $value, (I_bit+F_bit+SVC_mode):EOR:($value), $regtmp, $cond, $oldpsr
]
MEND
] ; :LNOT: No32bitCode
......@@ -860,30 +828,179 @@ op SETA ($op2a) :OR: (0:SHL:25)
DCI Cond_$cond :OR: 2_00000001001000001111000000000000 :OR: op :OR: psrtype
[ StrongARM_MSR_bug :LAND: "$sabug" <> "safe" :LAND: "$cond" <> "AL" :LAND: "$cond" <> "" :LAND: ((psrtype :AND: &410000) = &10000)
[ "$sabug" <> "unsafe"
! 0, "mymsr inserting NOP for StrongARM MSR CPSR_c bug"
! 0, "mymsr inserting NOP for StrongARM MSR CPSR_c bug", 1
]
NOP
]
MEND
; This next group of macros (SetMode, SExx, CLxx, and combinations) are
; optimised for 32bit architectures:
;
; * 32bit-only processor modes (e.g. SYS) are fully supported
; * Except for the T bit (assumed to be 0), only the indicated PSR fields will be touched (e.g. NZCV always preserved)
; * They assemble down to one instruction (CPS or MRS) wherever possible
; * Due to the limits of CPS this means they're all unconditional
; * For the one-instruction MRS form you'll have to provide 'hints' for the current mode/IF bits. But even though you're specifying the mode + interrupt flags, these macros are still better than WritePSRc (for ARMv6+)
; * When building 26/32bit neutral or 26bit-only versions:
; * The saved PSR will be the CPSR if MRS supported, else it's a saved PC (same rules as SavePSR, WritePSRc, etc.)
; * The SetMode macros will preserve the 32bit-ness of the host, unless asked to switch into a 32bit-only mode (e.g. SYS)
;
; Note the side-effects of SEI/SEF/CLI/CLF. The macros assume that if IRQ state
; is being altered, FIQs are enabled, and if FIQ state is being altered, IRQs
; are disabled. This is based on the premise that it's unsafe/unreliable to
; have FIQs disabled while IRQs are enabled (RISC OS generally assumes FIQs are
; enabled, so if you have FIQs disabled but IRQs enabled it would be easy for
; an IRQ handler to come along and do something which enables FIQs).
; ****************************************************
; *** SetMode - sets processor mode to constant ***
; *** value newmode using register regtmp as a ***
; *** temporary. ***
; *** If $irqs is provided it's expected to be the ***
; *** current I32+F32 flags ***
; *** $regtmp only required if 26bit support ***
; *** required, or no $irqs provided. ***
; ****************************************************
MACRO
SetMode $newmode, $regtmp, $oldpsr
[ "$oldpsr"=""
SetMode $newmode, $regtmp, $oldpsr, $irqs
[ :LNOT: NoARMv6
[ "$oldpsr"<>""
MRS $oldpsr, CPSR
]
CPS #$newmode
ELIF No26bitCode :LOR: ($newmode > SVC32_mode)
[ "$oldpsr"<>""
MRS $oldpsr, CPSR
]
[ "$irqs" <> ""
MSR CPSR_c, #$newmode + $irqs
ELIF "$oldpsr"=""
MRS $regtmp, CPSR
BIC $regtmp, $regtmp, #M32_bits
ORR $regtmp, $regtmp, #$newmode
MSR CPSR_c, $regtmp
|
MRS $oldpsr, CPSR
BIC $regtmp, $oldpsr, #M32_bits
ORR $regtmp, $regtmp, #$newmode
MSR CPSR_c, $regtmp
MSR CPSR_c, $regtmp
]
|
; Use SCPSR for 26/32bit-friendly PSR manipulation
SCPSR ($newmode :AND: 3), ($newmode :AND: 3) :EOR: 3, $regtmp, , $oldpsr
]
MEND
; *************************************************
; *** SEI - Disable IRQs, may enable FIQs ***
; *** SEF - Disable FIQs, may disable IRQs ***
; *** SEIF - Disable IRQs+FIQs ***
; *** If $mode is provided (preferred) then it ***
; *** must be the current 32bit processor mode. ***
; *** $regtmp only required if 26bit support ***
; *** required, or no $mode provided. ***
; *************************************************
MACRO
SE$op $mode, $regtmp, $oldpsr
CPU32_bits IFto32 $op
[ :LNOT: NoARMv6
[ "$oldpsr" <> ""
MRS $oldpsr, CPSR
]
CPSID $op
ELIF ("$mode" <> "") :LAND: (No26bitCode :LOR: (($mode + 0) > SVC32_mode))
[ "$oldpsr" <> ""
MRS $oldpsr, CPSR
]
MSR CPSR_c, #$mode+(CPU32_bits :OR: I32_bit)
|
; Use SETPSR for 26/32bit-friendly PSR manipulation
SETPSR CPU32_bits :SHL: IF32_26Shift, $regtmp, , $oldpsr
]
MEND
; *************************************************
; *** CLI - Enable IRQs, may enable FIQs ***
; *** CLF - Enable FIQs, may disable IRQs ***
; *** CLIF - Enable IRQs+FIQs ***
; *** If $mode is provided (preferred) then it ***
; *** must be the current 32bit processor mode. ***
; *** $regtmp only required if 26bit support ***
; *** required, or no $mode provided. ***
; *************************************************
MACRO
CL$op $mode, $regtmp, $oldpsr
CPU32_bits IFto32 $op
[ :LNOT: NoARMv6
[ "$oldpsr" <> ""
MRS $oldpsr, CPSR
]
CPSIE $op
ELIF ("$mode" <> "") :LAND: (No26bitCode :LOR: (($mode + 0) > SVC32_mode))
[ "$oldpsr" <> ""
MRS $oldpsr, CPSR
]
MSR CPSR_c, #$mode+I32_bit+F32_bit-(CPU32_bits :OR: F32_bit)
|
; Use CLRPSR for 26/32bit-friendly PSR manipulation
CLRPSR CPU32_bits :SHL: IF32_26Shift, $regtmp, , $oldpsr
]
MEND
; ***************************************************************
; *** SetModeSEI - Set mode + disable IRQs, may enable FIQs ***
; *** SetModeSEF - Set mode + disable FIQs, may disable IRQs ***
; *** SetModeSEIF - Set mode + disable IRQs+FIQs ***
; *** $regtmp only required if 26bit support required ***
; ***************************************************************
MACRO
SetModeSE$op $mode, $regtmp, $oldpsr
CPU32_bits IFto32 $op
[ :LNOT: NoARMv6
[ "$oldpsr" <> ""
MRS $oldpsr, CPSR
]
CPSID $op, #$mode
ELIF No26bitCode :LOR: ($mode > SVC32_mode)
[ "$oldpsr" <> ""
MRS $oldpsr, CPSR
]
MSR CPSR_c, #$mode+(CPU32_bits :OR: I32_bit)
|
LCLA clear_bits
LCLA set_bits
set_bits SETA ($mode :AND: 3) + (CPU32_bits :SHL: IF32_26Shift)
clear_bits SETA 3 :AND: :NOT: set_bits
SCPSR &$set_bits, &$clear_bits, $regtmp, , $oldpsr
]
MEND
; **************************************************************
; *** SetModeCLI - Set mode + enable IRQs, may enable FIQs ***
; *** SetModeCLF - Set mode + enable FIQs, may disable IRQs ***
; *** SetModeCLIF - Set mode + enable IRQs+FIQs ***
; *** $regtmp only required if 26bit support required ***
; **************************************************************
MACRO
SetModeCL$op $mode, $regtmp, $oldpsr
CPU32_bits IFto32 $op
[ :LNOT: NoARMv6
[ "$oldpsr" <> ""
MRS $oldpsr, CPSR
]
CPSIE $op, #$mode
ELIF No26bitCode :LOR: ($mode > SVC32_mode)
[ "$oldpsr" <> ""
MRS $oldpsr, CPSR
]
MSR CPSR_c, #$mode+I32_bit+F32_bit-(CPU32_bits :OR: F32_bit)
|
LCLA clear_bits
LCLA set_bits
set_bits SETA $mode :AND: 3
clear_bits SETA (3 :AND: :NOT: set_bits) + (CPU32_bits :SHL: IF32_26Shift)
SCPSR &$set_bits, &$clear_bits, $regtmp, , $oldpsr
]
MEND
] ; :LNOT: :DEF: Included_Hdr_CPU_Generic32
......
hdr/Devices
View file @ bbca0fed
......@@ -52,6 +52,8 @@ Device_RCMM # 1 ; &1018 Terry Adams
^ &101A
Device_USBd # 1 ; &101A John Ballance (Castle)
Device_USBTematic # 1 ; &101B Tematic (Dan)
^ &101E
Device_SPIDriver # 1 ; &101E John Ballance
OPT OldOpt
END
hdr/FSNumbers
View file @ bbca0fed
......@@ -79,7 +79,10 @@ fsnumber_FlashFS # 1 ; 136 Acorn (ap)
^ 162
fsnumber_TFTP # 1 ; 162 Kevin Bracey
^ 192
fsnumber_SDFS # 1 ; 192 ROOL / Ben Avison
fsnumber_SDFS # 1 ; 192 SDFS: ROOL / Ben Avison
^ 194
fsnumber_SATAFS # 1 ; 194 SATAFS: John Ballance
fsnumber_Source # 1 ; 195 Source: Rob Sprowson
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
......
hdr/FileTypes
View file @ bbca0fed
......@@ -826,6 +826,10 @@ FileType_OOXMLDoc_Name SETS "MSWordX"
FileType_MPO EQU &00000A7B
FileType_MPO_Name SETS "MPO"
GBLS FileType_MJPEG_Name
FileType_MJPEG EQU &00000A7A
FileType_MJPEG_Name SETS "MJPEG"
GBLS FileType_Translator_CUR_Name
FileType_Translator_CUR EQU &000006A5
FileType_Translator_CUR_Name SETS "CUR"
......
hdr/GraphicsV
View file @ bbca0fed
......@@ -45,6 +45,7 @@ GraphicsV_SelectHead * 15
GraphicsV_StartupMode * 16
GraphicsV_PixelFormats * 17
GraphicsV_ReadInfo * 18
GraphicsV_VetMode2 * 19
; GraphicsV_SetDMAAddress
GVDAG_VInit * 0
......@@ -85,4 +86,13 @@ GVReadInfo_DriverName * 2 ; Driver name for display to user
GVReadInfo_HardwareName * 3 ; Hardware name for display to user (e.g. PCI card name)
GVReadInfo_ControlListItems * 4 ; List of known VIDC control list items
; GraphicsV_VetMode2 result flags (r0)
GVVetMode2_ResultMask * 3
GVVetMode2_Result_Unsupported * 0 ; Provided mode is unsupported
GVVetMode2_Result_SysFramestore * 1 ; Mode is supported, and will use the system framestore (i.e. kernel-managed DA 2)
GVVetMode2_Result_ExtFramestore * 2 ; Mode is supported, and will use the external framestore (as defined by R3 & R5)
GVVetMode2_Result_UnkFramestore * 3 ; Mode is supported, but driver doesn't know where the framestore will be (e.g. framestore is managed by another component, like the GPU firmware in the Pi)
GVVetMode2_ExtraBytes_Invalid * 4 ; The input value of the ExtraBytes control list item was invalid, driver has suggested a new value in R2
END
hdr/MEMM/VMSAv6
View file @ bbca0fed
......@@ -27,6 +27,7 @@ AP_ROM * 2_100010 ; user read-only, svc read-only
AP_None * 2_000001 ; user no access, svc read/write
AP_Read * 2_000010 ; user read-only, svc read/write
AP_Full * 2_000011 ; user read/write, svc read/write
AP_PROM * 2_100001 ; user no access, svc read-only
L1_APShift * 10 ; value to shift AP_ values by for L1 entry
L2_APShift * 4 ; value to shift AP_ values by for L2 entry
......@@ -55,9 +56,9 @@ L1_TEXShift * 12
L1_TEX * 2_111 :SHL: 12 ; Type Extension bits
L1_C * 1 :SHL: 3 ; cacheable
L1_B * 1 :SHL: 2 ; bufferable
L1_S * 1 :SHL: 16 ; shareable
L1_nG * 1 :SHL: 17 ; 1=entry associated with ASID, 0=global
L1_XN * 1 :SHL: 4 ; eXecute Never
L1_X * 1 :SHL: 12 ; XScale - modifies meaning of C and B bits (is TEX bit 0)
L2L_TEXShift * 12 ; For large pages
L2_TEXShift * 6 ; For extended small pages
......@@ -65,11 +66,10 @@ L2L_TEX * 2_111 :SHL: 12 ; Type Extension bits (large pages)
L2_TEX * 2_111 :SHL: 6 ; Type Extension bits (tiny and extended pages)
L2_C * 1 :SHL: 3 ; cacheable bit in level 2 entry
L2_B * 1 :SHL: 2 ; bufferable --------""----------
L2_S * 1 :SHL: 10 ; shareable
L2_nG * 1 :SHL: 11 ; 1=entry associated with ASID, 0=global
L2L_XN * 1 :SHL: 15 ; eXecute Never for large pages
L2_XN * 1 ; eXecute Never for extended small pages
L2L_X * 1 :SHL: 12 ; XScale - modifies meaning of C and B bits (large pages) (is TEX bit 0)
L2_X * 1 :SHL: 6 ; XScale - modifies meaning of C and B bits (tiny and extended pages) (is TEX bit 0)
; CP15 control register bits
; Retaining MMUC_* naming for compatability with existing code
......@@ -120,7 +120,24 @@ CR_Domains CN 3 ; read/write
CR_FaultStatus CN 5 ; read
CR_FaultAddress CN 6 ; read
; Cache type register fields
; Cache size ID register fields
CCSIDR_WT_pos * 31
CCSIDR_WT_mask * 1:SHL:CCSIDR_WT_pos
CCSIDR_WB_pos * 30
CCSIDR_WB_mask * 1:SHL:CCSIDR_WB_pos
CCSIDR_RA_pos * 29
CCSIDR_RA_mask * 1:SHL:CCSIDR_RA_pos
CCSIDR_WA_pos * 28
CCSIDR_WA_mask * 1:SHL:CCSIDR_WA_pos
CCSIDR_NumSets_pos * 13
CCSIDR_NumSets_mask * &7FFF:SHL:CCSIDR_NumSets_pos
CCSIDR_Associativity_pos * 3
CCSIDR_Associativity_mask * &3FF:SHL:CCSIDR_Associativity_pos
CCSIDR_LineSize_pos * 0
CCSIDR_LineSize_mask * 7:SHL:CCSIDR_LineSize_pos
; Cache type register fields (ARMv6 register format)
; NOTE - need to be kept in sync with hdr.MEMM.ARM600!
CT_ctype_pos * 25
......
hdr/Machine/26 0 → 100644
View file @ bbca0fed
; Copyright 2016 Castle Technology Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
SUBT Machine-independent builds, for 26 bit OS versions
GBLS Machine
Machine SETS "26"
GET Hdr:Machine.Machine
END
hdr/Machine/CortexA7 0 → 100644
View file @ bbca0fed
; Copyright 2015 Castle Technology Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
SUBT Cortex-A7/-A15/-A17 machine: ARMv7VE + VFPv4 + NEON
GBLS Machine
Machine SETS "CortexA7"
GET Hdr:Machine.Machine
END
hdr/Machine/Machine
View file @ bbca0fed
......@@ -49,6 +49,7 @@ M_Omega SETL Machine="Omega"
M_Peregrine SETL Machine="Peregrine"
M_STB3 SETL Machine="STB3"
M_STB400 SETL Machine="STB400"
GBLL M_26
GBLL M_32
GBLL M_All
GBLL M_All32
......@@ -57,9 +58,11 @@ M_STB400 SETL Machine="STB400"
GBLL M_RPi
GBLL M_CortexA8
GBLL M_CortexA9
GBLL M_CortexA7
GBLL M_IOMD
GBLL M_STB5
GBLL M_Tungsten
M_26 SETL Machine="26"
M_32 SETL Machine="32"
M_All SETL Machine="All"
M_All32 SETL Machine="All32"
......@@ -68,19 +71,23 @@ M_ARM11ZF SETL Machine="ARM11ZF"
M_RPi SETL Machine="RPi"
M_CortexA8 SETL Machine="CortexA8"
M_CortexA9 SETL Machine="CortexA9"
M_CortexA7 SETL Machine="CortexA7"
M_IOMD SETL Machine="IOMD"
M_STB5 SETL Machine="STB5"
M_Tungsten SETL Machine="Tungsten"
[ Machine="CortexA15" :LOR: Machine="CortexA17"
! 1, "You probably wanted to use Machine=CortexA7"
]
; Are we only supporting 26bit processor modes?
; If true, we mustn't rely on MSR, MRS etc, and we should be
; RISC OS 3.1 compatible.
GBLL No32bitCode
No32bitCode SETL M_Archimedes :LOR: M_Morris :LOR: M_Falcon :LOR: M_Omega :LOR: M_Peregrine :LOR: M_STB3 :LOR: M_STB400
No32bitCode SETL M_26 :LOR: M_Archimedes :LOR: M_Morris :LOR: M_Falcon :LOR: M_Omega :LOR: M_Peregrine :LOR: M_STB3 :LOR: M_STB400
; Are we only supporting 32bit processor modes?
GBLL No26bitCode
No26bitCode SETL M_32 :LOR: M_Lazarus :LOR: M_IOMD :LOR: M_Tungsten :LOR: M_STB5 :LOR: M_ARM11ZF :LOR: M_RPi :LOR: M_CortexA8 :LOR: M_CortexA9
No26bitCode SETL M_32 :LOR: M_Lazarus :LOR: M_IOMD :LOR: M_Tungsten :LOR: M_STB5 :LOR: M_ARM11ZF :LOR: M_RPi :LOR: M_CortexA8 :LOR: M_CortexA9 :LOR: M_CortexA7
; If this makes your head hurt, the other way of looking at it is
; 26/32 neutral => No32bitCode FALSE No26bitCode FALSE
......@@ -91,13 +98,13 @@ No26bitCode SETL M_32 :LOR: M_Lazarus :LOR: M_IOMD :LOR: M_Tungsten :LOR:
; Override optimisation settings to avoid using unaligned LDR(H)/STR(H) on ARMv6+
; This switch should only be enabled for debugging purposes
GBLL NoUnaligned
NoUnaligned SETL M_ARM11ZF :LOR: M_RPi :LOR: M_CortexA8 :LOR: M_CortexA9
NoUnaligned SETL M_ARM11ZF :LOR: M_RPi :LOR: M_CortexA8 :LOR: M_CortexA9 :LOR: M_CortexA7
; Do we need to deal with the StrongARM conditional MSR CPSR_c bug?
GBLL StrongARM_MSR_bug
StrongARM_MSR_bug SETL M_All :LOR: M_All32 :LOR: M_IOMD
StrongARM_MSR_bug SETL M_26 :LOR: M_All :LOR: M_All32 :LOR: M_IOMD
[ :LNOT: M_All :LAND: :LNOT: M_All32
[ :LNOT: M_All :LAND: :LNOT: M_All32 :LAND: :LNOT: M_26
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; Switches that should not be used by machine-independent code
......@@ -129,7 +136,7 @@ MEMC_Type SETS "IOMD"
GetMEMC SETS "GET Hdr:IO." :CC: MEMC_Type
GBLS MEMM_Type
[ M_ARM11ZF :LOR: M_RPi :LOR: M_CortexA8 :LOR: M_CortexA9
[ M_ARM11ZF :LOR: M_RPi :LOR: M_CortexA8 :LOR: M_CortexA9 :LOR: M_CortexA7
MEMM_Type SETS "VMSAv6"
|
MEMM_Type SETS "ARM600"
......@@ -173,7 +180,7 @@ DontUseVCO SETL M_Lazarus :LOR: M_STB400
; Are we using a HAL?
GBLL HAL
HAL SETL M_32 :LOR: M_IOMD :LOR: M_Tungsten :LOR: M_STB5 :LOR: M_ARM11ZF :LOR: M_RPi :LOR: M_CortexA8 :LOR: M_CortexA9
HAL SETL M_32 :LOR: M_IOMD :LOR: M_Tungsten :LOR: M_STB5 :LOR: M_ARM11ZF :LOR: M_RPi :LOR: M_CortexA8 :LOR: M_CortexA9 :LOR: M_CortexA7
; General flag for STB/NCD-type products
GBLL STB
......@@ -202,7 +209,7 @@ MaxI2Cspeed SETA 100
; E2ROM is supported at i2c addresses >= A8 in addition to normal CMOS RAM
; Note that this also controls HAL NVRAM support, and RTCSupport.
GBLL E2ROMSupport
E2ROMSupport SETL M_Falcon :LOR: M_Omega :LOR: M_Peregrine :LOR: M_STB3 :LOR: M_STB400 :LOR: M_STB5 :LOR: M_Lazarus :LOR: M_32 :LOR: M_IOMD :LOR: M_Tungsten :LOR: M_ARM11ZF :LOR: M_RPi :LOR: M_CortexA8 :LOR: M_CortexA9
E2ROMSupport SETL M_Falcon :LOR: M_Omega :LOR: M_Peregrine :LOR: M_STB3 :LOR: M_STB400 :LOR: M_STB5 :LOR: M_Lazarus :LOR: M_32 :LOR: M_IOMD :LOR: M_Tungsten :LOR: M_ARM11ZF :LOR: M_RPi :LOR: M_CortexA8 :LOR: M_CortexA9 :LOR: M_CortexA7
; Support for network 'podule' cards
GBLL NetPodSupport
......@@ -246,13 +253,13 @@ BatManSupport SETL {FALSE} :LAND: StorkPowerSave
GBLL MorrisSupport
MorrisSupport SETL {TRUE}
; Less blocky teletext font
; Less blocky teletext font + support for any TTX mode colour depth >= 4bpp
GBLL HiResTTX
HiResTTX SETL M_Lazarus :LOR: M_STB400 :LOR: M_STB5 :LOR: M_Tungsten :LOR: M_ARM11ZF :LOR: M_RPi
HiResTTX SETL {TRUE}
; Teletext rendered at 8bpp
; Default teletext mode is 8bpp (when HiResTTX = {TRUE})
GBLL TTX256
TTX256 SETL M_Tungsten :LOR: M_STB5 :LOR: M_ARM11ZF :LOR: M_RPi
TTX256 SETL M_Tungsten :LOR: M_STB5 :LOR: M_ARM11ZF :LOR: M_RPi :LOR: M_CortexA9
; Safe area when doing TV modes
; Expressed as percentage of screen not to use - left, bottom, right, top
......
hdr/Macros
View file @ bbca0fed
......@@ -109,7 +109,7 @@ OldOpt SETA {OPT}
;$label ColourConv $in,$out,$tmpR,$tmpG,$tmpB,$red_shift,$red_bits,$green_shift,$green_bits,$blue_shift,$blue_bits,$alpha Convert &BBGGRR00 colours to various formats
;$label DEC $reg,$by Decrement a register (by a value)
;$label DECS $reg,$by Decrement a register (by a value) settng PSR
;$label DivRem $rc, $ra, $rb, $rtemp Get DIV and REM of two values
;$label DivRem $rc, $ra, $rb, $rtemp, $norem Get DIV and optional REM of two values
;$label DoCallTable $jumpreg, $tablename, $work Call a routine in a jump table
;$label DoFastJumpTable $jumpreg, $trash Call a routine in a jump table
;$label DoJumpTable $jumpreg, $tablename, $work1, $work2 Call a routine in a jump table
......@@ -693,14 +693,17 @@ $label SUBS $reg,$reg,#$by
]
MEND
; *************************************************
; *** DivRem - Integer division and remainder ***
; *** rc := ra DIV rb; ra := ra REM rb ***
; *** rb preserved, rtemp corrupt ***
; *************************************************
; **********************************************************
; *** DivRem - Unsigned integer division and remainder ***
; *** rc := ra DIV rb; ra := ra REM rb ***
; *** rb preserved, rtemp corrupt ***
; *** omits remainder (-> ra corrupt) if "$norem" <> "" ***
; *** rb can be a constant if it starts with '#' ***
; **********************************************************
MACRO
$label DivRem $rc, $ra, $rb, $rtemp
$label DivRem $rc, $ra, $rb, $rtemp, $norem
$label
[ NoARMVE
MOV $rtemp, $rb
CMP $rtemp, $ra, LSR #1
01
......@@ -715,6 +718,18 @@ $label
MOV $rtemp, $rtemp, LSR #1
CMP $rtemp, $rb
BCS %BT02
ELIF ("$rb" :LEFT: 1) == "#"
MOV $rtemp, $rb
UDIV $rc, $ra, $rtemp
[ "$norem" == ""
MLS $ra, $rtemp, $rc, $ra
]
|
UDIV $rc, $ra, $rb
[ "$norem" == ""
MLS $ra, $rb, $rc, $ra
]
]
MEND
; *********************
......
hdr/NewErrors
View file @ bbca0fed
......@@ -203,6 +203,7 @@ OldOpt SETA {OPT}
AddError NaffSWI, "SWI not known", ErrorNumber_ModuleBadSWI
AddError NeedMod, "Module %0 cannot start without module %1"
AddError2 RMNot32bit, "RMNot32bit:Module is not 32-bit compatible", ErrorNumber_BadRMHeaderField
AddError BadErrPtr, "BadErrPtr:SWI &%0 returned a bad error pointer"
; Variables errors
......@@ -298,6 +299,11 @@ ErrorBase_TerritoryManager # 16
AddError ChangeDynReEntered, "CDA Re-entered"
AddError BadOpOnSpareDA, "Bad Op on sparse DA"
AddError FreePoolLocked, "Free pool locked"
AddError BadDynamicAreaOptions,"BadDynamicAreaOptions:Bad dynamic area options"
AddError BadPageNumber, "BadPageNumber:Bad page number"
AddError NoMemChunkAvailable, "NoMemChunkAvailable:No chunk available"
AddError NoRoomForIO, "NoRoomForIO:No room for IO space"
AddError AccessPrivilegeNotFound, "AccessPrivilegeNotFound:Access privilege not found"
; Oscli and other errors
......@@ -427,6 +433,7 @@ ErrorBase_Econet * &300
AddError NoNetworkAccess, "No access to network"
AddError2 EconetInternalError, "Fatal internal error"
AddError NoEconetInterrupt, "Hardware fault in Econet Interface"
AddError AUNNotConfigured, "AUN not configured"
; Loaded Econet transients
ASSERT @ <= ErrorBase_Econet + &40
......@@ -660,6 +667,7 @@ ErrorBase_Econet * &300
AddError BadCommandOption, "Bad command option"
AddError UnknownSerialOp, "Unknown serial operation"
AddError BadHard, "BadHard" ; "Unsupported hardware configuration"
AddError TooComplex, "TooComplex:Transfer too complex"
; International errors
......@@ -1192,6 +1200,9 @@ ErrorBase_SDFS * &00010000 + ( fsnumber_SDFS :SHL: 8 ) ; fs 192
AddError NoSoundDevices, "No sound controller devices found"
; Extra Level 1 error
AddError AutoTuningUnavailable,"Automatic tuning unavailable"
; Extra Level 0 errors
AddError BadSoundDevice, "Sound controller device initialisation failed"
AddError SoundDevNotFound, "Sound device not found"
; SCSI driver errors
......@@ -1222,6 +1233,7 @@ ErrorBase_SDFS * &00010000 + ( fsnumber_SDFS :SHL: 8 ) ; fs 192
AddError2 IIC_NoAcknowledge, "No acknowledge from IIC device"
AddError2 IIC_Error, "IIC error" ;RO5
AddError2 IIC_Busy, "IIC system busy" ; RO5
AddError2 IIC_BadBus, "IIC bus not present" ; RO5
......@@ -1296,7 +1308,18 @@ ErrorBase_MachineExceptions # &100
ErrorBase_CoProc0 # &100
ErrorBase_FloatingPoint # &100
ErrorBase_EconetExceptions # &100
; Previously ErrorBase_AbortRegions was allocated next, &80000400, but the
; associated comment said &80000500. It is unclear which base was actually
; used on RISC OS Select (or even if it was used at all).
# &100
ErrorBase_AbortRegions # &100 ; &80000500
; Likewise, ErrorBase_VectorFloatingPoint was briefly assigned &80000500
; but with a comment saying &80000600. However, only the ARM11-based
; Raspberry Pi was capable of generating the exceptions that triggered
; these errors, and throughout the time this was the case, there was no
; stable OS release for the Pi, and nor is it believed that anything
; was written that acted upon the error numbers, so now we make the symbol
; resolve to the same number that was always documented.
ErrorBase_VectorFloatingPoint # &100 ; &80000600
^ ErrorBase_MachineExceptions
......@@ -1529,5 +1552,16 @@ ErrorBase_DeskRecord # &100 ; &0081F800 Steve Revill
ErrorBase_USBAudio # &100 ; &0081F900 Dave Higton
ErrorBase_RTC # &100 ; &0081FA00 Rob Sprowson
ErrorBase_BASIC # &100 ; &0081FB00 Rob Sprowson
^ &00820500
ErrorBase_ATA # &100 ; &00820500 Ben Avison
ErrorBase_SPIDriver # &100 ; &00820600 John Ballance
^ &00820800
ErrorBase_SerialUSB # &100 ; &00820800 Colin Granville
^ &00820A00
ErrorBase_OHCIDriver # &40 ; &00820A00 Rob Sprowson
ErrorBase_EHCIDriver # &40 ; &00820A40 Rob Sprowson
ErrorBase_MUSBDriver # &40 ; &00820A80 Rob Sprowson
ErrorBase_DWCDriver # &40 ; &00820AC0 Rob Sprowson
ErrorBase_SMP # &100 ; &00820D00 Jeffrey Lee
OPT OldOpt
END
hdr/OsBytes
View file @ bbca0fed
......@@ -230,7 +230,8 @@ OsByte_RW_VDUQueue # 1 ; &DA/218 Acorn - BBC MOS
OsByte_RW_TabCharCode # 1 ; &DB/219 Acorn - BBC MOS
OsByte_RW_SoundSystemElk * OsByte_RW_TabCharCode
OsByte_RW_EscapeCharCode # 1 ; &DC/220 Acorn - BBC MOS
OsByte_RW_UseOfCode197To207 # 1 ; &DD/221 Acorn - BBC MOS
OsByte_RW_UseOfCode192To207 # 1 ; &DD/221 Acorn - BBC MOS
OsByte_RW_UseOfCode197To207 * OsByte_RW_UseOfCode192To207 ; typo in previous header?
OsByte_RW_UseOfCode208To223 # 1 ; &DE/222 Acorn - BBC MOS
OsByte_RW_UseOfCode224To239 # 1 ; &DF/223 Acorn - BBC MOS
OsByte_RW_UseOfCode240To255 # 1 ; &E0/224 Acorn - BBC MOS
......
hdr/SWIs
View file @ bbca0fed
......@@ -1733,6 +1733,36 @@ RTCSWI EQU &00001653
RTCSWI_Base EQU &000594C0
RTCSWI_Name SETS "RTC"
GBLS ATASwitchSWI_Name
ATASwitchSWI EQU &0000165E
ATASwitchSWI_Base EQU &00059780
ATASwitchSWI_Name SETS "ATA"
GBLS SPIDriverSWI_Name
SPIDriverSWI EQU &00001662
SPIDriverSWI_Base EQU &00059880
SPIDriverSWI_Name SETS "SPID"
GBLS SATAFSSWI_Name
SATAFSSWI EQU &00001663
SATAFSSWI_Base EQU &000598C0
SATAFSSWI_Name SETS "SATAFS"
GBLS CPUClockSWI_Name
CPUClockSWI EQU &00001666
CPUClockSWI_Base EQU &00059980
CPUClockSWI_Name SETS "CPUClock"
GBLS PL2303SWI_Name
PL2303SWI EQU &00001667
PL2303SWI_Base EQU &000599C0
PL2303SWI_Name SETS "PL2303"
GBLS SMPSWI_Name
SMPSWI EQU &0000166F
SMPSWI_Base EQU &00059BC0
SMPSWI_Name SETS "SMP"
; Application SWI Chunks
......
hdr/Services
View file @ bbca0fed
......@@ -290,6 +290,9 @@ Service_BootBootVarsSet # 1 ; &810C0
Service_BootResourcesVarsSet # 1 ; &810C1
Service_BootChoicesVarsSet # 1 ; &810C2
^ &81100
IICService # 64 ; &81100, Rob Sprowson
^ &82880 ; Aquarius Window services
Service_WindowModuleUnused # 1 ; &82880
Service_WindowModuleStarting # 1 ; &82881
......