Very minor tweaks to the CPU.Arch header file.

Changed the formatting of example 4 to look more consistent with they way
we format asm code. Corrected the comments for example 5 to indicate that
R0 may be corrupted also.

Version 1.66. Tagged as 'HdrSrc-1_66'

VersionNum

-/* (1.65)
+/* (1.66)
  *
  * This file is automatically maintained by srccommit, do not edit manually.
  * Last processed by srccommit version: 1.1.
  *
  */
-#define Module_MajorVersion_CMHG        1.65
+#define Module_MajorVersion_CMHG        1.66
 #define Module_MinorVersion_CMHG        
-#define Module_Date_CMHG                06 May 2009
+#define Module_Date_CMHG                08 May 2009
 
-#define Module_MajorVersion             "1.65"
-#define Module_Version                  165
+#define Module_MajorVersion             "1.66"
+#define Module_Version                  166
 #define Module_MinorVersion             ""
-#define Module_Date                     "06 May 2009"
+#define Module_Date                     "08 May 2009"
 
-#define Module_ApplicationDate          "06-May-09"
+#define Module_ApplicationDate          "08-May-09"
 
 #define Module_ComponentName            "HdrSrc"
 #define Module_ComponentPath            "castle/RiscOS/Sources/Programmer/HdrSrc"
 
-#define Module_FullVersion              "1.65"
-#define Module_HelpVersion              "1.65 (06 May 2009)"
-#define Module_LibraryVersionInfo       "1:65"
+#define Module_FullVersion              "1.66"
+#define Module_HelpVersion              "1.66 (08 May 2009)"
+#define Module_LibraryVersionInfo       "1:66"

hdr/CPU/Arch

@@ -96,23 +96,23 @@
 ;
 ;  [ :LNOT: SupportARMv3
 ;    ; Can only be executed in 26-bit mode
-;    TEQP PC, #2
+;    TEQP    PC, #2
 ;    NOP
 ;  |
 ;  [ NoARMG
 ;    ; Could be either 26-bit mode or 32-bit mode
-;    TEQ PC, PC
-;    MSREQ CPSR_c, #&12
-;    TEQNEP PC, #2
+;    TEQ     PC, PC
+;    MSREQ   CPSR_c, #&12
+;    TEQNEP  PC, #2
 ;    NOP
 ;  |
 ;    ; Can only be executed in 32-bit mode
-;    MSR CPSR_c, #&12
+;    MSR     CPSR_c, #&12
 ;  ]
 ;  ]
 
 ; Example 5: load a word from address in r0, which may be non-word-aligned,
-; into r1. Registers r2 and r3 may be corrupted.
+; into r1. Registers r0, r2 and r3 may be corrupted.
 ;
 ; Under ARMv6, unaligned behaviour can be configured either way, but since
 ; ARMv7 mandates the new behaviour we have to handle it anyway, so we may as