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  • Robert Sprowson's avatar
    Import of SetStation sources · 5c19a3b0
    Robert Sprowson authored 
    Recreated with the help of !SID, this is the utility previously supplied with AUN to set a machine's station number. Note, it pokes IOC and has various other 26 bit delights in it.
Produces almost the same binary, with the exception of LDRB rn,[rd] which AAsm used to create LDRB rn,[rd],#0 for,
Not tagged.
    5c19a3b0
  • Robert Sprowson's avatar
    Makefile recreated from fragments · 36910551
    Robert Sprowson authored 
    Moved NewOS/OldOS switches into Econet.s.
Updated line labels in SetStn utility to have non-autogenerated names.
Note: as a result of simplifying the Makefile, it is no longer possible to build an EconetMsgs module.

Binary identical, not tested. Tagged as Econet-5_76-pre1.
    36910551
  • Robert Sprowson's avatar
    Rationalise build switches · 15c0f607
    Robert Sprowson authored 
    Drop support for OldOS (RISC OS 2), it's time to accept MessageTrans does exist now.
Drop support for ARM8, the processor that never was.
Use {TRUE} and {FALSE} objasm built in variables.
Tagged as Econet-5_76-pre2.
    15c0f607
  • Robert Sprowson's avatar
    Add support for RAM variant · cabba62b
    Robert Sprowson authored 
    Now we use the shared makefiles & accept MessageTrans is present, we get a RAM variant with merged messages almost for free. Add the supporting ResourceFS register/deregister code, this removes the need for a separate EconetMsgs module.
Tested on a RISC OS 3.70 Risc PC with AEH60 card, browsing a server & copying files to and fro.

Version 5.76. Tagged as 'Econet-5_76'
    cabba62b
  • Robert Sprowson's avatar
    Add Ursula fast service table, make hardware base common · b7c83ced
    Robert Sprowson authored 
    Added an Ursula fast reject service call table, inspected in !Verma for correctness.
Remove the 'PoduleCapable' switch, since in both cases it boils down to an LDR of the address of the 68B54 controller there's little to choose between it being in the workspace or a constant in ROM.
Changed 2x unaligned loads into LDRB's since only 1 byte values are needed (Commands.s).

Tested on an AEH60 on RISC OS 3.70.

Version 5.77. Tagged as 'Econet-5_77'
    b7c83ced
  • Robert Sprowson's avatar
    Give line labels more sensible names · 2c7cefbe
    Robert Sprowson authored 
    Binary identical, not tagged.
    2c7cefbe
  • ROOL's avatar
    Fix for RMA corruption · 0b132ffd
    ROOL authored 
    Detail:
  ImmediateRecord can hold a TxCB, but was only sized for CommonCB. When in ROM the neighbouring module seems tolerant of the start of its workspace being overwrittem, but when softloaded (esp. on RISC OS 3.xx) frequent "Heap corrupt" or address exceptions would occur.
Admin:
  Submission from Ian Bradbury.

Version 5.78. Tagged as 'Econet-5_78'
    0b132ffd
  • ROOL's avatar
    32-bit compatible · 1f1e3584
    ROOL authored 
    Detail:
  Added a veneer to the SWI handler so that internally they can corrupt flags and only on exit are 26 .v. 32 bit differences considered.
  No need to flags preserve the service call handler(s), module init, module finalisation.
  Fix bug in RxGetRegisters, the value in r9 pointing to the register block is a banked FIQ mode register, so the IRQ r13/r14 and SVC r13/r14 would be written whereever the unbanked r9 happened to be pointing. May also be worth considering adding a RxGetRegisters32 so the extra PSR fields can be read (not done).
  Changed references to ADR rN, IOC to MOV rN, #IOC.
  For OS_Byte calls use names from Hdr:OsBytes.
  Fix for lock up in SetTicker. If Service_ClaimFIQ were to return an error, the function returned without re-enabling interrupts. Extra PLP inserted.
  Removed manual NOPs after PSR fiddling macros, these are now included in the macro where required with HdrSrc-2_63.
  Delete many unused macros from Macros.s to save having to bother 32 bitting them...
    1f1e3584
  • ROOL's avatar
    Minor fixes · 2aa8ad61
    ROOL authored 
    Detail:
  Change some signed pointer compares to be unsigned.
  Report network speed in kilohertz not kelvinhertz.
Admin:
  Not tested - the code changes are in debug switches only.

Version 5.80. Tagged as 'Econet-5_80'
    2aa8ad61
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Showing with 411 additions and 1186 deletions
MkClean,fd7 → !MkClean,fd7
View file @ 2aa8ad61
| Copyright 1996 Acorn Computers Ltd
| Copyright 2015 Castle Technology Ltd
|
| Licensed under the Apache License, Version 2.0 (the "License");
| you may not use this file except in compliance with the License.
......
MkExport,fd7 → !MkRam,fd7
View file @ 2aa8ad61
| Copyright 1999 Pace Micro Technology plc
| Copyright 2015 Castle Technology Ltd
|
| Licensed under the Apache License, Version 2.0 (the "License");
| you may not use this file except in compliance with the License.
......@@ -13,4 +13,4 @@
| limitations under the License.
|
Dir <Obey$Dir>
amu_machine export
amu_machine standalone THROWBACK=-throwback
MkRom,fd7 → !MkRom,fd7
View file @ 2aa8ad61
| Copyright 1996 Acorn Computers Ltd
| Copyright 2015 Castle Technology Ltd
|
| Licensed under the Apache License, Version 2.0 (the "License");
| you may not use this file except in compliance with the License.
......
Makefile
View file @ 2aa8ad61
......@@ -14,128 +14,13 @@
#
# Makefile for Econet
#
# ***********************************
# *** C h a n g e L i s t ***
# ***********************************
# Date Name Description
# ---- ---- -----------
# 28-Jun-94 AMcC Created.
# 05-Oct-99 SNB Translates header into C header
#
#
# Paths
#
EXP_HDR = <export$dir>
C_EXP_HDR = <cexport$dir>.Interface.h
#
# Generic options:
#
MKDIR = do mkdir -p
AS = objasm
LD = link
CP = copy
MODGEN = modgen
RM = remove
TOKENISE = tokenise
XWIPE = x wipe
PERL = do <Perl$Dir>.perl
AFLAGS = -depend !Depend -stamp -closeexec -quit
CPFLAGS = ~cfr~v
TOKENS = Hdr:Tokens
#
# Program specific options:
#
COMPONENT = Econet
SOURCE = NewOS
SOURCE200 = OldOS
TARGET = rm.Econet
TARGET200 = rm.Econet200
HDR = hdr.${COMPONENT}
EXPORTS = ${EXP_HDR}.Econet ${C_EXP_HDR}.Econet
MESSAGESMOD = rm.EconetMsgs
MESSAGES = Resources.${LOCALE}.Messages
RESPATH = Resources.Econet.Messages
MODNAME = EconetMessages
MODHELP = EconetMessages
#
# Rules:
#
all: ${TARGET}
@echo ${COMPONENT}: ${TARGET} built
all200: ${TARGET200}
@echo ${COMPONENT}: ${TARGET200} built
#
# Generic Build rules:
#
rom: ${TARGET}
@echo ${COMPONENT}: rom module built
export: ${EXPORTS}
@echo ${COMPONENT}: export complete
install_rom: $(TARGET)
$(CP) $(TARGET) $(INSTDIR).$(COMPONENT) $(CPFLAGS)
@echo ${COMPONENT}: rom module installed
install: ${TARGET}
${CP} ${TARGET} ${INSTDIR}.${COMPONENT} ${CPFLAGS}
@echo ${COMPONENT}: module installed
clean:
${RM} ${TARGET}
${RM} ${TARGET200}
${RM} ${MESSAGESMOD}
${XWIPE} o ~CFR~V
@echo ${COMPONENT}: cleaned
resources:
${MKDIR} ${RESDIR}.${COMPONENT}
${CP} Resources.${LOCALE}.Messages ${RESDIR}.${COMPONENT}.Messages ${CPFLAGS}
@echo ${COMPONENT}: resource files copied
#
# Assemble the Econet module
#
${TARGET}: ${SOURCE}
${MKDIR} o
${AS} ${SOURCE} -o o.Module ${AFLAGS}
${LD} -rmf -o $@ o.Module
${TARGET200}: ${SOURCE200}
${MKDIR} o
${AS} ${SOURCE200} -o o.Module ${AFLAGS}
${LD} -rmf -o $@ o.Module
#
# Export hdr files
#
${EXP_HDR}.Econet: hdr.Econet
${CP} hdr.Econet $@ ${CPFLAGS}
${C_EXP_HDR}.Econet: hdr.Econet
${mkdir} ${C_EXP_HDR}
${PERL} Build:Hdr2H hdr.Econet $@
#
# Generate an Econet Messages module
# Note: need to set alias to ensure that <Version> is expanded
#
msgmod: ${MESSAGESMOD}
@echo ${COMPONENT}: messages module built
${MESSAGESMOD}: ${MESSAGES} VersionNum
${PERL} build:getversion Econet$BuildV Econet$FullV Econet$Date
Do ${MODGEN} -date "<Econet$Date>" $@ ${MODNAME} ${MODHELP} <Econet$BuildV> ${MESSAGES} ${RESPATH}
HEADER1 = Econet
ASMCHEADER1 = Econet
EXPORTS = ${C_EXP_HDR}.${ASMCHEADER1}
#---------------------------------------------------------------------------
include StdTools
include AAsmModule
# Dynamic dependencies:
MkNew,fd7 deleted 100644 → 0
View file @ 0c540a08
| Copyright 1996 Acorn Computers Ltd
|
| Licensed under the Apache License, Version 2.0 (the "License");
| you may not use this file except in compliance with the License.
| You may obtain a copy of the License at
|
| http://www.apache.org/licenses/LICENSE-2.0
|
| Unless required by applicable law or agreed to in writing, software
| distributed under the License is distributed on an "AS IS" BASIS,
| WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
| See the License for the specific language governing permissions and
| limitations under the License.
|
Dir <Obey$Dir>
amu_machine all
MkOld,fd7 deleted 100644 → 0
View file @ 0c540a08
| Copyright 1996 Acorn Computers Ltd
|
| Licensed under the Apache License, Version 2.0 (the "License");
| you may not use this file except in compliance with the License.
| You may obtain a copy of the License at
|
| http://www.apache.org/licenses/LICENSE-2.0
|
| Unless required by applicable law or agreed to in writing, software
| distributed under the License is distributed on an "AS IS" BASIS,
| WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
| See the License for the specific language governing permissions and
| limitations under the License.
|
Dir <Obey$Dir>
amu_machine all200
NewOS deleted 100644 → 0
View file @ 0c540a08
TTL ==> &.Arthur.Econet.NewOS
GBLL OldOs
OldOs SETL {FALSE}
GBLL UseMsgTrans
UseMsgTrans SETL {TRUE}
GBLS OsString
OsString SETS ""
GBLL StrongARM
StrongARM SETL {TRUE}
GBLL ARM810support
ARM810support SETL {FALSE}
GBLL ReleaseVersion
ReleaseVersion SETL {TRUE}
LNK s.Module
OldOS deleted 100644 → 0
View file @ 0c540a08
TTL ==> &.Arthur.Econet.OldOS
GBLL OldOs
OldOs SETL {TRUE}
GBLL UseMsgTrans
UseMsgTrans SETL {FALSE}
GBLS OsString
OsString SETS " (2.00)"
GBLL StrongARM
StrongARM SETL {FALSE}
GBLL ARM810support
ARM810support SETL {FALSE}
GBLL ReleaseVersion
ReleaseVersion SETL {TRUE}
LNK s.Module
Resources/UK/Messages
View file @ 2aa8ad61
......@@ -29,7 +29,7 @@ NoPorts:All ports allocated
BadNumb:Bad number
BadConf:|j|mConfigured network station number is invalid, using 1 instead.|j|m
HelpStn:Network station %0
StnFreq:Network station %0, network clock %1 KHz
StnFreq:Network station %0, network clock %1 kHz
StnNClk:Network station %0, no clock
AcrnEco:Acorn Econet|j|m
EcoNClk:Acorn Econet, no clock|j|m
......
VersionASM
View file @ 2aa8ad61
......@@ -11,13 +11,13 @@
GBLS Module_HelpVersion
GBLS Module_ComponentName
GBLS Module_ComponentPath
Module_MajorVersion SETS "5.75"
Module_Version SETA 575
Module_MajorVersion SETS "5.80"
Module_Version SETA 580
Module_MinorVersion SETS ""
Module_Date SETS "26 Nov 2011"
Module_ApplicationDate SETS "26-Nov-11"
Module_Date SETS "02 Jul 2016"
Module_ApplicationDate SETS "02-Jul-16"
Module_ComponentName SETS "Econet"
Module_ComponentPath SETS "castle/RiscOS/Sources/Networking/Econet"
Module_FullVersion SETS "5.75"
Module_HelpVersion SETS "5.75 (26 Nov 2011)"
Module_FullVersion SETS "5.80"
Module_HelpVersion SETS "5.80 (02 Jul 2016)"
END
VersionNum
View file @ 2aa8ad61
/* (5.75)
/* (5.80)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 5.75
#define Module_MajorVersion_CMHG 5.80
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 26 Nov 2011
#define Module_Date_CMHG 02 Jul 2016
#define Module_MajorVersion "5.75"
#define Module_Version 575
#define Module_MajorVersion "5.80"
#define Module_Version 580
#define Module_MinorVersion ""
#define Module_Date "26 Nov 2011"
#define Module_Date "02 Jul 2016"
#define Module_ApplicationDate "26-Nov-11"
#define Module_ApplicationDate "02-Jul-16"
#define Module_ComponentName "Econet"
#define Module_ComponentPath "castle/RiscOS/Sources/Networking/Econet"
#define Module_FullVersion "5.75"
#define Module_HelpVersion "5.75 (26 Nov 2011)"
#define Module_LibraryVersionInfo "5:75"
#define Module_FullVersion "5.80"
#define Module_HelpVersion "5.80 (02 Jul 2016)"
#define Module_LibraryVersionInfo "5:80"
s/Background
View file @ 2aa8ad61
......@@ -17,15 +17,15 @@
ALIGN $Alignment
Interrupt ROUT
Push "lr"
ADR r14, IOC
MOV r14, #IOC
LDRB r14, [ r14, #IOCIRQREQA ] ; IRQ Request register
TST r14, #force_bit ; IRQ forced from FIQ
Pull "pc", EQ ; If it wasn't an FIQ to IRQ down-grade
LD r14, FIQStatus
TEQ r14, #FIQ_Owner ; Are we the owner of FIQ?
Pull "pc", NE ; If it wasn't us who did it, give it back
TEQP psr, #( IFlag + SVC_mode ) ; Goto SVC
NOP
Push "r0" ; Get a spare unbanked register
WritePSRc I_bit+SVC_mode, r14,, r0 ; Goto SVC
Push "r0-r4, lr" ; On supervisor stack
[ DebugIRQ
LDR r2, =Border_Pink
......@@ -33,13 +33,12 @@ Interrupt ROUT
STR r2, [ r3, #0 ]
]
InterruptLoop
TEQP psr, #( FFlag + IFlag + SVC_mode ) ; Disable FIQ
ADR r1, IOC ; Not mode dependent
SETPSR F_bit, lr,, r2 ; Disable FIQ
MOV r1, #IOC ; Not banked
LDRB r0, [ r1, #IOCIRQMSKA ] ; IRQ Mask register
BIC r0, r0, #force_bit ; Must clear it first in case it happens again!
STRB r0, [ r1, #IOCIRQMSKA ] ; IRQ Mask register
TEQP psr, #( IFlag + SVC_mode ) ; Enable FIQ
NOP ; Next instruction uses wp hence it's mode dependent
RestPSR r2 ; Enable FIQ
LD r0, PeekPokeFlag ; First look for a peek or a poke memory check
TEQ r0, #0 ; Are we down grading a peek or a poke?
BEQ InterruptImmediate
......@@ -53,11 +52,7 @@ InterruptLoop
ADR r2, ScoutBuffer + 4 ; Here lies the start and end address+1
LDMIA r2, { r0, r1 }
SWI XOS_ValidateAddress
[ PoduleCapable
LDR r1, HardwareAddress
|
LDR r1, =EconetController ; Get the address of our chip
]
LDR r1, HardwareAddress ; Get the address of our chip
BVS DontAllowPeekOrPoke
BCS DontAllowPeekOrPoke
MOV r0, #2_11100111 ; RTS, CLRTxST, CLRRxST, FlagIdle, 2Byte, PSE
......@@ -105,7 +100,7 @@ InterruptImmediate ; Then look for an immed
TEQ r0, #BitSeven + Econet_UserProcedureCall
MOVEQ r0, #Event_Econet_UserRPC
MOVNE r0, #Event_Econet_OSProc
[ False ; Debug
[ {FALSE} ; Debug
DREG r0, "XOS_GenerateEvent called, R0 = &", cc
DREG r1, ", R1 = &", cc
DREG r1, ", R2 = &", cc
......@@ -175,7 +170,7 @@ CheckForEvent
LDR r1, [ r14, #Offset_Handle ]
LDRB r2, [ r14, #Offset_Status ]
LDRB r3, [ r14, #Offset_Port ]
[ False ; Debug
[ {FALSE} ; Debug
DREG r0, "XOS_GenerateEvent called, R0 = &", cc
DREG r1, ", R1 = &", cc
DREG r2, ", R2 = &", cc
......@@ -192,9 +187,8 @@ InterruptFinished
STR r2, [ r3, #0 ]
]
Pull "r0-r4, lr" ; Off supervisor stack
TEQP psr, #IFlag + IRQ_mode ; Return to original mode
NOP
Pull "lr, pc" ; Off IRQ stack
RestPSR r0
Pull "r0, lr, pc" ; Off IRQ stack
ALIGN $Alignment
Event ROUT
......@@ -202,23 +196,22 @@ Event ROUT
; This code will be entered in SWI mode because I called it from SWI mode
; so there is no need to go to SWI mode to preserve R14 in SWIs
TEQ r0, #Event_Econet_OSProc
MOVNES pc, lr
MOVNE pc, lr
TEQ r2, #Econet_OSCharacterFromNotify ; Bottom byte of RPC number is what to do
BEQ InsertCharacter
TEQ r2, #Econet_OSCauseFatalError
BEQ CauseFatalError
MOV r0, #Event_Econet_OSProc
BICS pc, lr, #VFlag
MOVNE pc, lr
InsertCharacter
[ False ; Debug
[ {FALSE} ; Debug
DREG r0, "InsertCharacter called, R0 = &", cc
DREG r1, ", R1 = &", cc
DREG r2, ", R2 = &", cc
DREG r3, ", R3 = &", cc
DREG r4, ", R4 = &"
]
MOV r0, #138
MOV r0, #OsByte_InsertBufferedChar
LDRB r2, [ r1, #4 ] ; Pick up the character from the buffer
MOV r1, #0
MOV r3, lr
......@@ -229,7 +222,6 @@ CauseFatalError
MOV r1, #0
ST r1, LockOut ; Clear the lockout state
ADR r0, ErrorRemoted
[ UseMsgTrans
ADR lr, ExecuteFatalError
B MakeError
ExecuteFatalError
......@@ -239,11 +231,6 @@ ErrorRemoted
DCD ErrorNumber_Remoted
DCB "Remoted", 0
ALIGN
|
SWI OS_GenerateError
Err Remoted
]
LTORG
......@@ -261,7 +248,7 @@ Pacemaker ROUT
TEQ r7, #FIQ_PoweredDown ; Is it OK to do anything?
Pull "r6, r7, pc", EQ ; No we aren't even alive
Push "r2-r5"
MOV r5, psr ; Save mode in r5, should be IRQ might just be SVC
SavePSR r5 ; Save mode in r5, should be IRQ might just be SVC
LD r7, TxCBList ; Now check the transmit queue to see what needs restarting
B %30
......@@ -277,7 +264,7 @@ CheckTxList
30
TEQ r7, #NIL
BNE CheckTxList
[ PerthPowerDown
[ PerthPowerDown
; Now check if it is Power Down time yet
LDR r7, PowerDownTime
CMP r7, r6
......@@ -297,13 +284,13 @@ CheckTxList
LDR r7, RxCBList
TEQ r7, #NIL
BEQ %70 ; Its OK, so lets do it
TEQP psr, #( IFlag + SVC_mode ) ; Goto SVC
WritePSRc I_bit+SVC_mode, r2 ; Goto SVC
MOV r2, #ServicePortable_TidyUp ; Lets beg for it (non-mode dependent register)
Push "r1, lr" ; This may cause SWIs, which will change PowerDownTime
MOV r1, #Service_Portable
SWI XOS_ServiceCall
Pull "r1, lr"
TEQP psr, r5 ; Restore mode and interrupt state
RestPSR r5 ; Restore mode and interrupt state
LDR r7, RxCBList
TEQ r7, #NIL
60
......@@ -311,39 +298,36 @@ CheckTxList
STRNE r7, PowerDownTime
Pull "r2-r7, pc", NE ; Still got things to do
70
[ DebugPowerDown
[ DebugPowerDown
LDR r7, =Border_Magenta
ADR r14, VIDC
STR r7, [ r14, #0 ]
]
TEQP psr, #( IFlag + SVC_mode ) ; Goto SVC
NOP
[ UsePortableModule
]
WritePSRc I_bit+SVC_mode, r7 ; Goto SVC
[ UsePortableModule
Push "r0, r1, lr" ; On supervisor stack
MOV r0, #0 ; Turn it off
MVN r1, #PortableControl_EconetEnable
SWI XPortable_Control
Pull "r0, r1, lr"
|
|
Push "r1-r3, lr" ; On supervisor stack
MOV r1, #Service_Portable
MOV r2, #ServicePortable_PowerDown
MOV r3, #PortableControl_EconetEnable
SWI XOS_ServiceCall
Pull "r1-r3, lr"
]
TEQP psr, r5 ; Restore mode and interrupt state
NOP
]
RestPSR r5 ; Restore mode and interrupt state
NoPowerDownYet
]
]
[ ReceiveInBackground
LD r2, BridgeRxHandle
TEQ r2, #0
BEQ %90 ; Bridge handle already abandoned
CMP r6, #BridgeWaitTime
BLS %90 ; Not time to abandon yet, unsigned CMP
TEQP psr, #SVC_mode ; Goto SVC, needed to call AbandonAndReadReceive
NOP
WritePSRc SVC_mode, r6 ; Goto SVC, needed to call AbandonAndReadReceive
Push "r0, r1, r5, r10, r11, lr"
MOV r0, #0
ST r0, BridgeRxHandle
......@@ -359,8 +343,7 @@ NoPowerDownYet
97
]
Pull "r0, r1, r5, r10, r11, lr"
TEQP psr, r5 ; Restore mode and interrupt state
NOP
RestPSR r5 ; Restore mode and interrupt state
90
]
ExitPacemaker
......@@ -441,14 +424,11 @@ LocalCopyLoop
STRB r4, [ r2, #Offset_Control ]
MOV r4, #Status_Received ; Mark the reception as completed
STRB r4, [ r2, #Offset_Status ]
MOV r4, psr ; Save interrupt state
TEQP psr, #( FFlag + IFlag + SVC_mode ) ; Disable all interrupts
NOP ; Note; WP *IS* a mode dependent register
WritePSRc I_bit+F_bit+SVC_mode, r3,, r4 ; Disable all interrupts, save interrupt state
LD r3, EventSequenceNumber
INC r3 ; Get an event number
ST r3, EventSequenceNumber
TEQP psr, r4 ; Restore interrupts and mode
NOP
RestPSR r4 ; Restore interrupts and mode
LDRB r4, [ r7, #Offset_Broadcast ]
TEQ r4, #0 ; Is this a broadcast?
MOVNE r4, #Status_Transmitted ; Mark a normal transmit as completed
......@@ -483,14 +463,10 @@ LocalNetError
B ExitRestartRecord
SendToWire
[ False ; **************** Bodge ****************
[ {FALSE} ; **************** Bodge ****************
! 0, " **** Bodge code assembled in SendToWire ****"
Push r10
[ PoduleCapable
LDR r10, HardwareAddress
|
LDR r10, =EconetController
]
LDRB r10, SReg2
ST r10, Status2
Pull r10
......@@ -500,8 +476,7 @@ SendToWire
MOVNE r4, #Status_NoClock
STRNEB r4, [ r7, #Offset_Status ]
BNE DoEventAndExit ; No mode change yet
TEQP psr, #( FFlag + IFlag + FIQ_mode ) ; Goto FIQ mode, disable all interrupts
NOP ; Note; WP *IS* a mode dependent register
WritePSRc I_bit+F_bit+FIQ_mode, r4 ; Goto FIQ mode, disable all interrupts
LD r4, FIQBusy ; Get the FIQBusy flag
TEQ r4, #0 ; Test it
BNE ExitRestartRecord
......@@ -542,8 +517,7 @@ StoreModeWord
SetFIQ TxFromMe, r8, r9, Long, Init, r13
SetJump TxControlAndPort, r8, r9, Long
ExitRestartRecord
TEQP psr, r5 ; Return to correct mode, and interrupt state
NOP ; Restores NZCVIF and the mode bits
RestPSR r5 ; Return to correct mode, and interrupt state
Pull "r2-r7, pc"
ImmediateModeBits ; Stored as bytes to be put in the top bits
......@@ -572,16 +546,13 @@ NoLineAccess ; Line jammed ??
DoEventAndExit
; R7 <= Pointer to CB to event
; Trashes R3 and R4
MOV r4, psr ; Save interrupt state
TEQP psr, #( FFlag + IFlag + SVC_mode ) ; Disable all interrupts
NOP ; Note; WP *IS* a mode dependent register
WritePSRc I_bit+F_bit+SVC_mode, r3,, r4 ; Disable all interrupts, save interrupt state
LD r3, EventSequenceNumber
INC r3
ST r3, EventSequenceNumber
TEQP psr, r4 ; Restore interrupts and mode
NOP
RestPSR r4 ; Restore interrupts and mode
STR r3, [ r7, #Offset_Event ]
ADR r4, IOC
MOV r4, #IOC
LDRB r3, [ r4, #IOCIRQMSKA ] ; IRQ Mask register
ORR r3, r3, #force_bit
STRB r3, [ r4, #IOCIRQMSKA ] ; IRQ Mask register
......
s/Commands
View file @ 2aa8ad61
......@@ -57,7 +57,6 @@ HelpTable
DCD 0
DoStarHelpStation ROUT
[ UseMsgTrans
Push "r0-r6, lr"
; R0 is a buffer address
; R1 is the buffer size
......@@ -114,35 +113,6 @@ Token_HelpStationNoClock
Token_HelpStationFrequency
DCB "StnFreq", 0
ALIGN
|
Push "r0-r2, lr"
; R0 is a buffer address
; R1 is the buffer size
LDR wp, [ r12 ]
MOV r2, r1 ; Buffer length
MOV r1, r0 ; Buffer address
BL AddString
DCB "Econet station ", 0
ALIGN
Push r1
SWIVC XEconet_ReadLocalStationAndNet
Push "r0, r1"
MOVVC r0, sp ; Point at the station number
LDRVC r1, [ sp, #8 ]
SWIVC XOS_ConvertNetStation
INC sp, 12 ; Trash two data values and the saved R1
BVS ExitHelpCode
LD r0, Status2
TST r0, #DCD
BEQ ExitHelpCode
BL AddString
NoClockString
DCB " no clock", 0
ALIGN
ExitHelpCode
STRVS r0, [ sp, #0 ]
Pull "r0-r2, pc"
]
[ ErrorInfo
HelpForStarErrorInfo
......@@ -185,9 +155,9 @@ DoStarErrorInfo ROUT
NetErrorListLoop
LDR r3, NetErrorListPointer
CMP r4, r3
ADRGEL r4, NetErrorList
STRGE r4, NetErrorListPointer
BGE ExitErrorInfo
ADRCSL r4, NetErrorList
STRCS r4, NetErrorListPointer
BCS ExitErrorInfo
ADRL r1, TextBuffer
MOV r2, #?TextBuffer
BL AddString
......@@ -224,7 +194,7 @@ NetErrorListLoop
SWIVC XOS_ConvertHex2
BVS ExitErrorInfo
NetErrorNoHandle
LDR r0, [ r4, #0 ]
LDRB r0, [ r4, #0 ]
TEQ r0, #255
BEQ NetErrorNoSReg1
BL AddString
......@@ -233,7 +203,7 @@ NetErrorNoHandle
SWIVC XOS_ConvertHex2
BVS ExitErrorInfo
NetErrorNoSReg1
LDR r0, [ r4, #1 ]
LDRB r0, [ r4, #1 ]
TEQ r0, #255
BEQ NetErrorNoSReg2
BL AddString
......@@ -591,11 +561,17 @@ PrintNameAndValueAsByte
]
[ (:LNOT: UseMsgTrans) :LOR: ErrorInfo :LOR: ControlBlocks
[ ErrorInfo :LOR: ControlBlocks
AddString ROUT
Push r1
CLRV
[ :LNOT: No32bitCode
TEQ pc, pc ; Check processor mode
BICNE lr, lr, #ARM_CC_Mask
BICEQ lr, lr, #3
|
BIC lr, lr, #ARM_CC_Mask
]
10
TEQ r2, #0
SETV EQ
......@@ -608,7 +584,6 @@ AddString ROUT
INC lr, 3 ; Get to the right word boundary
BIC lr, lr, #3 ; Align afterwards
Pull r0
[ UseMsgTrans
MOVVC pc, lr
ADR r0, ErrorBufferOverflow
B MakeError
......@@ -617,10 +592,6 @@ ErrorBufferOverflow
DCD ErrorNumber_CDATBufferOverflow
DCB "BufOFlo", 0
ALIGN
|
ADRVSL Error, ErrorCDATBufferOverflow
MOV pc, lr
]
]
END
s/Module → s/Econet
View file @ 2aa8ad61
This diff is collapsed.
s/Interface
View file @ 2aa8ad61
This diff is collapsed.
s/Macros
View file @ 2aa8ad61
......@@ -33,168 +33,6 @@ C0 CN 0
C5 CN 5
C10 CN 10
MACRO
FIQStr $s
STR r4, [ r0, -r0 ] ; Save in a known place
LDR r4, =DebugTraceRegs ; Work area
STMIA r4!, { r0-r3 }
LDMIA r4!, { r1, r2 }
STMIA r4!, { r5 }
MOV r5, psr ; Preserve mode
TEQP psr, #( FFlag + IFlag + SVC_mode ) ; Set FIQ flag and goto SVC mode
CMP r2, #50
BLT %FT30
ADR r3, %FT20
10
LDRB r0, [ r3 ], #1
STRB r0, [ r1, #0 ]
TEQ r0, #0
SUBNE r2, r2, #1
ADDNE r1, r1, #1
BNE %BT10
B %FT30
20
DCB $s, 0
ALIGN
30
TEQP r5, #0 ; Return to Correct mode
LDMDB r4!, { r5 }
STMDB r4!, { r1, r2 }
LDMDB r4!, { r0-r3 }
LDR r4, [ r0, -r0 ]
MEND
MACRO
FIQReg $r
STR r4, [ r0, -r0 ] ; Save in a known place
LDR r4, =DebugTraceRegs ; Work area
STMIA r4!, { r0-r3 }
MOV r3, psr ; Preserve mode
[ $r = r4
LDR r0, [ r0, -r0 ]
|
MOV r0, $r
]
TEQP psr, #( FFlag + IFlag + SVC_mode ) ; Set FIQ flag and goto SVC mode
LDMIA r4!, { r1, r2 }
STMIA r4!, { r14 } ; Preserve SVC r14
SWI XOS_ConvertHex8
LDMDB r4!, { r14 }
STMDB r4!, { r1, r2 }
TEQP r3, #0 ; Return to Correct mode
LDMDB r4!, { r0-r3 }
LDR r4, [ r0, -r0 ]
MEND
MACRO
Str $s
Push "r0-r4"
MOV r4, psr ; Preserve mode
TEQP psr, #( FFlag + IFlag + SVC_mode ) ; Set FIQ flag and goto SVC mode
LDR r0, =DebugTraceAddr ; Work area
LDMIA r0, { r1, r2 }
CMP r2, #50
BLT %FT30
ADR r3, %FT20
10
LDRB r0, [ r3 ], #1
STRB r0, [ r1, #0 ]
TEQ r0, #0
SUBNE r2, r2, #1
ADDNE r1, r1, #1
BNE %BT10
B %FT30
20
DCB $s, 0
ALIGN
30
LDR r0, =DebugTraceAddr ; Work area
STMIA r0, { r1, r2 }
TEQP r4, #0 ; Return to Correct mode
Pull "r0-r4"
MEND
MACRO
Reg $r
Push "r0-r4"
MOV r4, psr ; Preserve mode
TEQP psr, #( FFlag + IFlag + SVC_mode ) ; Set FIQ flag and goto SVC mode
LDR r0, =DebugTraceAddr ; Work area
LDMIA r0, { r1, r2 }
CMP r2, #50
BLT %FT30
[ $r = r0
LDR r0, [ sp, #0 ]
|
[ $r = r1
LDR r0, [ sp, #4 ]
|
[ $r = r2
LDR r0, [ sp, #8 ]
|
[ $r = r3
LDR r0, [ sp, #12 ]
|
[ $r = r4
LDR r0, [ sp, #16 ]
|
MOV r0, $r
]
]
]
]
]
Push "lr"
SWI XOS_ConvertHex8
Pull "lr"
30
LDR r0, =DebugTraceAddr ; Work area
STMIA r0, { r1, r2 }
TEQP r4, #0 ; Return to Correct mode
Pull "r0-r4"
MEND
MACRO
DebugStats $Reg,$Id
STR r0, [ r0, -r0 ]
LDR r0, =DebugRegs
STMIA r0, { r1, r2, r3 }
LDR r1, =DebugPtr
LDR r2, [ r1, #0 ]
LDR r3, [ r1, #DebugLimit-DebugPtr ]
CMP r3, r2
ORR r3, $Reg, #($Id :SHL: 16)
STMLTDB r2!, { r3 }
STRLT r2, [ r1, #0 ]
LDMIA r0, { r1, r2, r3 }
LDR r0, [ r0, -r0 ]
MEND
MACRO
Load $reg,$identifier,$c
; If the global variable with the same name as "$identifier"
; is null then it is assumed that a variable exists and can be
; LD'd from, otherwise the global variable is assumed to contain
; the text of the value that can be LDR ='d.
[ $identifier = ""
LD $reg, $identifier.Var, $c
|
LDR$c $reg, =$$$identifier
]
MEND
MACRO
Stor $reg,$identifier,$cond
; If the global variable with the same name as the identifier
; is null then it is assumed that a variable exists and can be
; ST'd to, otherwise an error is raised
[ $identifier = ""
ST $reg, $identifier.Var, $cond
|
! 0, "Storing to constant value"
]
MEND
MACRO
$a SetFIQ $dest,$rega,$regb,$style,$init,$regc
; $dest is the label of the code to jump to
......@@ -206,7 +44,7 @@ $a SetFIQ $dest,$rega,$regb,$style,$init,$regc
]
[ "$init" = "Init"
$a
[ {TRUE} ; ; Cope with 32bit CPUs
[ :LNOT: No32bitCode ; Cope with 32bit CPUs
MRS $regc, CPSR ; Switch to _32 mode with IRQs and FIQs off
ORR $regb, $regc, #I32_bit :OR: F32_bit ; Has to be done in two stages because RISC OS
MSR CPSR_cxsf, $regb ; can't return to a 32bit mode and interrupts
......@@ -216,33 +54,30 @@ $a
ADR $rega, FIQVector
LDR $regb, =&E51FF004 ; LDR pc, .+4 = LDR pc, [ pc, #-4 ]
STR $regb, [ $rega ], #4
[ {TRUE} ; ; Cope with 32bit CPUs
[ :LNOT: No32bitCode ; Cope with 32bit CPUs
; And switch back
MSR CPSR_cxsf, $regc
]
[ StrongARM
; Local version of OS_SynchroniseCodeAreas, because it's far too much hassle
; calling a SWI in these circumstances
MRC ARM_config_cp, 0, $regc, ARM_ID_reg, C0, 0
AND $regc,$regc,#&F000
TEQS $regc,#&A000
BNE %FT01 ; not StrongARM
; We want to clean the (32-byte) data cache line containing
; the FIQVector word.
ADR $regc, FIQVector
MCR ARM_config_cp, 0, $regc, ARM8A_cache_reg, C10, 1 ; clean DC entry
MCR ARM_config_cp, 0, $regc, ARM8A_cache_reg, C10, 4 ; drain WB
MCR ARM_config_cp, 0, $regc, ARM8A_cache_reg, C5, 0 ; flush IC
; Normally 4 NOPs could be required to make sure the
; modified instruction wasn't in the pipeline. Fortunately
; we know that the FIQ vector can't be called within 3
; instructions of here (and if an FIQ were to go off, the
; pipeline would be flushed anyway).
[ StrongARM
; Local version of OS_SynchroniseCodeAreas, because it's far too much hassle
; calling a SWI in these circumstances
MRC ARM_config_cp, 0, $regc, ARM_ID_reg, C0, 0
AND $regc,$regc,#&F000
TEQS $regc,#&A000
BNE %FT01 ; not StrongARM
; We want to clean the (32-byte) data cache line containing
; the FIQVector word.
ADR $regc, FIQVector
MCR ARM_config_cp, 0, $regc, ARM8A_cache_reg, C10, 1 ; clean DC entry
MCR ARM_config_cp, 0, $regc, ARM8A_cache_reg, C10, 4 ; drain WB
MCR ARM_config_cp, 0, $regc, ARM8A_cache_reg, C5, 0 ; flush IC
; Normally 4 NOPs could be required to make sure the
; modified instruction wasn't in the pipeline. Fortunately
; we know that the FIQ vector can't be called within 3
; instructions of here (and if an FIQ were to go off, the
; pipeline would be flushed anyway).
1
[ ARM810support
SUB PC,PC,#4 ; flushes branch predict on ARM810 (local equivalent of OS_SynchroniseCodeAreas)
]
]
]
|
$a ADR $rega, FIQVector + 4
]
......@@ -272,22 +107,13 @@ $a ADR $rega, $dest
MEND
MACRO
$a PutFIQ $rega,$regb,$init
$a PutFIQ $rega,$regb
; $rega is the register with the instruction in it
; $regb is the register to use for the pointer
[ "$rega" = "" :LOR: "$regb" = ""
! 1,"Syntax is: PutFIQ instruction, address [, init]"
! 1,"Syntax is: PutFIQ instruction, address"
]
[ "$init" = "Init"
[ StrongARM
! 1,"PutFIQ Init won't work on StrongARM!"
]
$a ADR $rega, FIQVector
LDR $regb, =&E51FF004 ; LDR pc, .+4 = LDR pc, [ pc, #-4 ]
STR $regb, [ $rega ], #4
|
$a ADR $rega, FIQVector + 4
]
ADR $regb, NextJump
LDR $regb, [ $regb, #0 ]
STR $regb, [ $rega, #0 ]
......@@ -355,7 +181,7 @@ $a ADR $rega, FIQVector + 4
MACRO
TurnAroundDelay $reg1,$reg2,$reg3,$delay
ADR r10, IOC
MOV r10, #IOC
[ "$delay" = "" ; Default case is 40 microseconds
MOV $reg1, #80
| ; Delay value in microseconds
......@@ -373,21 +199,7 @@ $a ADR $rega, FIQVector + 4
SUBS $reg1, $reg1, #1 ; Decrement ticks
BNE %BT10 ; Then continue if not done
; delay has expired
[ PoduleCapable
LDR r10, HardwareAddress
|
LDR r10, =EconetController
]
MEND
MACRO
Err $name
ALIGN
Error$name
DCD ErrorNumber_$name
DCB ErrorString_$name
DCB 0
ALIGN
MEND
OPT OldOpt
......
s/Memory
View file @ 2aa8ad61
......@@ -77,14 +77,11 @@ Event_Done * &FFFFFFFF ; A larger number
; bottom half word has the destination address
Word TxMode ; Top byte has the mode bits,
Word PowerDownTime ; When "Time" >= to this then Power Down
[ :LNOT: OldOs
Word MachinePeekData ; Computed at init-time
]
[ PoduleCapable
Word HardwareAddress
Word HardwareAddress ; MC68B54
Word InterruptAddress
Byte InterruptMask
]
Byte SWILock ; Indicates, to FIQ code, we are servicing a SWI
Byte LockOut ; Used to lock out more immediate ops when
......@@ -118,10 +115,9 @@ FIQ_PoweredDown * 2
Word EventSequenceNumber ; Used to ensure events are offered in the correct order
Word PortTable, 16 ; 256 2bit set [ 0..255 ]
[ UseMsgTrans
Word MessageBlockAddress
Word MessageBlock, 4 ; Needed by Mr Spastic MessageTrans
]
Word MessageBlock, 4 ; Needed by MessageTrans
Word
Byte ScoutBuffer, &410
......@@ -131,8 +127,8 @@ FIQ_PoweredDown * 2
Byte ArgumentsBuffer, &100
Word
Byte ImmediateRecord, Size_CommonCB ; Used while peek and poke happen
ASSERT Size_TxCB > Size_RxCB
Byte ImmediateRecord, Size_TxCB ; Used while peek and poke happen
BroadcastBit * 1 :SHL: 29
ImmediateBit * 1 :SHL: 28
......
s/Receive
View file @ 2aa8ad61
......@@ -205,11 +205,7 @@ CheckRxCB
LDRB r13, [ r11, #Offset_Status ] ; Now check status
TEQ r13, #Status_RxReady
TryNextRxCB
[ PoduleCapable
LDR r10, HardwareAddress
|
LDR r10, =EconetController ; Always branched to with BNE, because something didn't match
]
LDR r10, HardwareAddress ; Always branched to with BNE, because something didn't match
BEQ ScoutMatch ; This branch taken on the TEQ above
LDR r11, [ r11, #Offset_Link ]
B CheckRxCB
......@@ -242,7 +238,7 @@ ScoutMatch
ALIGN $Alignment
WaitForData ; Shared with reception of Poke
[ False ; DebugFIQ
[ {FALSE} ; DebugFIQ
ADR r8, DebugSpacePointer
LDR r9, [ r8, #0 ]
TEQ r9, #0
......@@ -251,7 +247,7 @@ WaitForData ; Shared with reception
LDRNEB r13, SReg2
STRNEB r13, [ r9 ], #1
CMP r9, #DebugSpaceEnd
MOVGE r9, #0
MOVCS r9, #0
STR r9, [ r8, #0 ]
]
SetJump EndOfData, r8, r13
......@@ -276,7 +272,7 @@ WaitForData ; Shared with reception
TEQ r9, #0
STRNEB r13, [ r9 ], #1
CMP r9, #DebugSpaceEnd
MOVGE r9, #0
MOVCS r9, #0
STR r9, [ r8, #0 ]
]
TST r13, #AddressPresent
......@@ -363,7 +359,7 @@ CauseEventAndReset
ST r13, EventSequenceNumber
STR r13, [ r11, #Offset_Event ]
CauseInterruptAndReset
ADR r11, IOC
MOV r11, #IOC
LDRB r13, [ r11, #IOCIRQMSKA ] ; IRQ Mask register
ORR r13, r13, #force_bit ; FIQ to IRQ down-grade
STRB r13, [ r11, #IOCIRQMSKA ] ; IRQ Mask register
......@@ -523,7 +519,7 @@ ValidatePeekPokeAddress
MOV r8, #-1
ST r8, PeekPokeFlag ; Set flag
ADR r8, IOC
MOV r8, #IOC
LDRB r13, [ r8, #IOCIRQMSKA ] ; IRQ Mask register
ORR r13, r13, #force_bit ; FIQ to IRQ down-grade
STRB r13, [ r8, #IOCIRQMSKA ] ; IRQ Mask register
......@@ -620,30 +616,32 @@ RxMachinePeek ; &88
ADR r9, VIDC
STR r8, [ r9, #0 ]
]
[ OldOs
ADRL r8, MachineVersionNumber
MOV r9, #4 - 1
|
ADR r8, MachinePeekData
MOV r9, #?MachinePeekData - 1
]
B CommonPeek
RxGetRegisters ; &89
ADR r9, Registers
STMIA r9, { r0-r14 } ^ ; Put down user R0 to R14
ADD r9, r9, #15 * 4 ; R9 now has address of R15
STMIA r9!, { r0-r7 } ; Using 2x STMs because SASTMhatbroken
STMIA r9, { r8-r14 } ^ ; Put down user R0 to R14
ADD r9, r9, #7 * 4 ; R9 now has address of R15
SUB r8, lr, #4 ; Correct PC
[ No26bitCode
STR r8, [ r9 ], #4 ; Store R15 (PC), perhaps need RxGetRegisters32 for PSR?
|
STR r8, [ r9 ], #4 ; Store R15 (PC+PSR)
TEQP psr, #FFlag + IFlag + IRQ_mode ; Go to IRQ Mode
NOP
STMIA r9!, { r13, r14 }
TEQP psr, #FFlag + IFlag + SVC_mode ; Go to SVC Mode
NOP
STMIA r9, { r13, r14 }
TEQP psr, #FFlag + IFlag + FIQ_mode ; Go back to FIQ Mode
NOP
]
MOV r7, r9 ; Put register block into unbanked register
WritePSRc I_bit+F_bit+IRQ_mode, r8 ; Go to IRQ Mode
STMIA r7!, { r13, r14 }
WritePSRc I_bit+F_bit+SVC_mode, r8 ; Go to SVC Mode
STMIA r7, { r13, r14 }
WritePSRc I_bit+F_bit+FIQ_mode, r8 ; Go back to FIQ Mode
ADR r8, Registers
LDR r7, [ r8, #7 * 4 ] ; Restore unbanked register
MOV r9, #?Registers - 1
CommonPeek
SetFIQ TxFromMe, r11, r13
......
s/Transmit
View file @ 2aa8ad61
......@@ -154,7 +154,7 @@ FinishScout
TurnAroundDelay r8, r9, r13
IgnoreCTS
LD r13, SReg1
[ False ; Fix2441 **************************************
[ {FALSE} ; Fix2441 **************************************
TSTS r13, #CTS ; Is there a CTS status that we should ignore?
BNE IgnoreCTS
]
......
MkMsgs,fd7 → utils/!MkSetStn,fd7
View file @ 2aa8ad61
| Copyright 1996 Acorn Computers Ltd
| Copyright 2014 Castle Technology Ltd
|
| Licensed under the Apache License, Version 2.0 (the "License");
| you may not use this file except in compliance with the License.
......@@ -13,4 +13,6 @@
| limitations under the License.
|
Dir <Obey$Dir>
amu_machine msgmod
objasm SetStation -o <Wimp$Scrap>
link -bin -o ^.SetStation <Wimp$Scrap>
settype ^.SetStation Utility