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Resync with allocations database
Ben Avison authored 
Detail:
  Resolve allocation clash for vector &2C.  It appears that RISCOS Ltd used
  this vector in RISC OS 6 without getting it allocated - they really should
  have known better, since Hdr:RISCOS has always one of the header files
  centrally managed and coordinated between the two forks of RISC OS.
  Resolved by moving SeriousErrorV to &2D since it is a relatively recent
  addition (April 2016) and hasn't yet featured in a stable RISC OS 5
  release.
  Also correct some comments elsewhere in Hdr:RISCOS.


Version 6.01. Tagged as 'Kernel-6_01'
cc37d347
Name Last commit Last update
..
ExportVals 32-bit Kernel.
ARMops Support for ARMv8
Copro15ops Add new ARMops. Add macros which map the ARMv7/v8 cache/TLB maintenance mnemonics (as featured in recent ARM ARMs) to MCR ops.
EnvNumbers Import from cleaned 360 CD
HALDevice New HAL device ID reservations
HALEntries Change module initialisation to be a two pass scheme
KernelWS Tweak handling of zero page compatibility page
KeyWS Delete STB code
ModHand Resolve 2x header clashes
OSEntries Teach the kernel about different memory attributes
OSMem Add a compatibility page zero for high processor vectors / zero page relocation builds
OSMisc Expose CLREX via OS_PlatformFeatures
OSRSI6 Add initial support for "physical memory pools"
Options Recover gracefully from a completely blank set of CMOS
PL310 Add ARMops for PL310 L2 cache controller
PublicWS Fix HiProcVecs build. Remove old-style PublicWS definitions.
RISCOS Resync with allocations database
VIDCList Reverse interlace deprecation decision
Variables Import from cleaned 360 CD
VduExt Improve Service_DisplayStatus, Service_DisplayChanged functionality
VideoDevice Update VDU HAL device for new OMAPVideo driver, fix MVA-based cache/TLB maintenance ops aborting on ARMv7, add warning to VDU driver about inconsistent state variables during screen mode changes