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Tweak handling of zero page compatibility page
Jeffrey Lee authored 
Detail:
  s/MemInfo, hdr/KernelWS - Rather than peeking L2PT to determine if the compatibility page is enabled, use a workspace var to track its state. This ensures we won't get confused if other software decides to map something of its own to &0.
  s/NewReset - Ensure the CompatibilityPageEnabled flag is initialised correctly
Admin:
  Tested in Iyonix ROM softload


Version 5.90. Tagged as 'Kernel-5_90'
36062ff5
Name Last commit Last update
..
AMBControl Implement support for cacheable pagetables
PMF Change module initialisation to be a two pass scheme
vdu Fix software pointer when ExtraBytes is in use
ARM600 Implement support for cacheable pagetables
ARMops Streamline PL310 ARMops
Arthur2 Fix incorrect OS_SynchroniseCodeAreas call
Arthur3 Extend MonitorType configure keyword
ArthurSWIs Reimplement AMBControl ontop of the PMP system
CPUFeatures Revise comments - it's multiprocessing extensions, not virtualisation
ChangeDyn Fix inverted global vs. per-page cache flush logic in PMP LogOp_MapOut
Convrsions Add UUID output formatter to conversions
Exceptions Implement support for cacheable pagetables
ExtraSWIs Reimplement AMBControl ontop of the PMP system
GetAll Change module initialisation to be a two pass scheme
HAL Change module initialisation to be a two pass scheme
HeapMan Delete lots of old switches
HeapSort Avoid unnecesssary remainder calculations
Kernel Expose CLREX via OS_PlatformFeatures
LibKern More HAL work. IOMD HAL work in progress. Lots of my own little build scripts. Don't touch this.
MOSDict Import from cleaned 360 CD
MemInfo Tweak handling of zero page compatibility page
MemMap2 Implement support for cacheable pagetables
Middle Fix to OS_ReadSysInfo 1
ModHand Change module initialisation to be a two pass scheme
MoreComms Resolve 2x header clashes
MoreSWIs
MsgCode
NewIRQs
NewReset
Oscli
SWINaming
Super1
SysComms
TickEvents
UnSqueeze
Utility
VMSAv6