Robert Sprowson
authored
Historically the kernel looked after all aspects of cache control since they were common across all ARMs. However, not all cache controllers are created equal, and sometimes more complex initialisation steps are needed than fit the generic coprocessor ops - for example the PL310 attached to a Cortex-A9 has memory mapped control registers. Rather than clutter the kernel with one shot init code for every cache controller invented, we delegate that step to the HAL in HAL_Init. This is only a few hundred instructions later than where it was already being set. The kernel remains responsible for subsequent maintenance, this is just init which is being handed off. A quick survey of the Cortex-A TRMs shows: A5 - optional, for example ARM's PL310, ref TRM section 8.1.7. A7 - optional, C bit of SCTLR, ref TRM section 1.1. A8 - L2EN bit of ACTLR, note this bit has been recycled for other uses on other cores, ref TRM section 8.3. A9 - not integrated, ARM's PL310 uses bit 0 of control register 1, ref PL310 TRM section 3.1.1. A12 - see A17 A15 - integrated, C bit of SCTLR, ref TRM section 7.2.3. A17 - integrated, bit 18 of L2CTLR & C bit of SCTLR, ref TRM section 7.2. and while we've got the TRMs open, back fill the CPU id register table. Version 5.35, 4.79.2.250. Tagged as 'Kernel-5_35-4_79_2_250'