1. 16 Jan, 2015 1 commit
    • Jeffrey Lee's avatar
      Escape some dollars · ece80d58
      Jeffrey Lee authored
      Detail:
        s/NewReset, s/Super1 - Escape some dollars contained in strings to avoid warnings from objasm
      Admin:
        Resulting binary unchanged
      
      
      Version 5.35, 4.79.2.253. Tagged as 'Kernel-5_35-4_79_2_253'
      ece80d58
  2. 01 Jul, 2012 1 commit
    • Robert Sprowson's avatar
      Sort out SetBorder · fe354937
      Robert Sprowson authored
      NewReset.s:
      The one remaining use of SetBorder was to denote the user asked for and got a CMOS reset, which in the HAL case emitted a warning because setting the border is potentially complicated/slow.
      To solve this, the reset is noted and replaces the normal RISC OS banner with a warning message. The behaviour and text for this comes from the BBC Master, though the escape key is used in place of break since a reset isn't actually needed.
      Moved the unused cputable inside its corresponding switch.
      Two occurrences of WriteS_Translated would have executed the message in the V=1 case.
      KernelWS/Resources:
      Flag added to workspace, translation added to messages files.
      Heapman.s:
      Commented out use of SetBorder removed.
      Kernel.s:
      SetBorder macro removed.
      Middle.s:
      Switched out use of SetBorder removed.
      Super1.s:
      Conditional WriteS_Translated would try to execute the message in the opposite condition case.
      
      
      Version 5.35, 4.79.2.157. Tagged as 'Kernel-5_35-4_79_2_157'
      fe354937
  3. 08 Aug, 2011 1 commit
    • Jeffrey Lee's avatar
      Add zero page relocation support · 2247d8e9
      Jeffrey Lee authored
      Detail:
        A whole mass of changes to add high processor vectors + zero page relocation support to the Cortex branch of the kernel
        At the moment the code can only cope with two ZeroPage locations, &0 and &FFFF0000. But with a bit more tweaking those restrictions can probably be lifted, allowing ZeroPage to be hidden at almost any address (assuming it's fixed at compile time). If I've done my job right, these restrictions should all be enforced by asserts.
        There's a new option, HiProcVecs, in hdr/Options to control whether high processor vectors are used. When enabling it and building a ROM, remember:
        * FPEmulator needs to be built with the FPEAnchor=High option specified in the components file (not FPEAnchorType=High as my FPEmulator commit comments suggested)
        * ShareFS needs unplugging/removing since it can't cope with it yet
        * Iyonix users will need to use the latest ROOL boot sequence, to ensure the softloaded modules are compatible (OMAP, etc. don't really sof...
      2247d8e9
  4. 07 Oct, 2002 1 commit
  5. 26 Jun, 2001 1 commit
    • Mike Stephens's avatar
      1) Bring IOMD HAL more up to date. Add support for new call HAL_CleanerSpace... · 63a6ffec
      Mike Stephens authored
      1) Bring IOMD HAL more up to date. Add support for new call HAL_CleanerSpace (preparation for StrongARM kernel support).
      
      2) In kernel, add HAL_CleanerSpace call (preparation for
      StrongARM and XScale core support). Fix bug found with
      ARMv3 support during test on Risc PC.
      
      3) Implement new API for kernel SWIs that have used top
      bits of addresses as flags. The new API has an extra
      flag that must be set, so kernel can distinguish and
      support both APIs. The reason for all this is that
      addresses are 32-bits now, people, keep up there. Briefly:
      
        OS_HeapSort
          bit 31 of r0 set for new API, r1 is full 32-bit address
          flags move from r1 bits 31-29 to r0 bits 30-28
      
        OS_ReadLine
          bit 31 of r1 set for new API, r0 is full 32-bit address
          flags move from bits 31,30 of r0 to bits 30,29 of r1
      
        OS_SubstituteArgs
          bit 31 of r2 set for new API, r0 is full 32-bit address
          flag moves from bit 31 of r0 to bit 30 of r2
      
      Tested on Risc PC and briefly on Customer A 2
      
      Ta
      
      Version 5.35, 4.79.2.41. Tagged as 'Kernel-5_35-4_79_2_41'
      63a6ffec
  6. 04 Apr, 2000 1 commit
    • Kevin Bracey's avatar
      32-bit Kernel. · b4016e9c
      Kevin Bracey authored
      Details:
        The Kernel will now compile to produce a pure 32-bit system if No26bitCode is
        set to TRUE.
        If No26bitCode is FALSE, then the Kernel will be a standard 26-bit Kernel,
        although some internal changes have taken place to minimise compile
        switches between the two cases. See Docs.32bit for more technical info.
      
        The hardest part was the flood-fill...
      
      Other changes:
        Pointer shape changes now take place on the next VSync, rather than actually
        WAITING for the VSync. Turning the Hourglass on shouldn't slow your machine
        down by 5% now :)
      
        Lots of really crusty pre-IOMD code removed.
      
      Admin:
        Tested in 32 and 26-bit forms in a limited desktop build. Basically, this
        will need to see a lot of use to iron out difficulties. I'd like anyone who
        has a non-frozen project to at least attempt using this Kernel.
      
      Version 5.23. Tagged as 'Kernel-5_23'
      b4016e9c
  7. 05 Nov, 1996 1 commit