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Commit d4596a38 authored by Kevin Bracey's avatar Kevin Bracey
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Added ComboClock14MHz switch - only supported by SMC669. 

Version 4.91. Tagged as 'Kernel-4_91'
parent fb297c9b
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Showing with 16 additions and 12 deletions
VersionASM
View file @ d4596a38
......@@ -6,9 +6,9 @@
GBLS Module_MinorVersion
GBLS Module_Date
GBLS Module_FullVersion
Module_MajorVersion SETS "4.90"
Module_Version SETA 490
Module_MajorVersion SETS "4.91"
Module_Version SETA 491
Module_MinorVersion SETS ""
Module_Date SETS "29 Sep 1999"
Module_FullVersion SETS "4.90"
Module_Date SETS "01 Oct 1999"
Module_FullVersion SETS "4.91"
END
VersionNum
View file @ d4596a38
/* (4.90)
/* (4.91)
*
* This file is automatically maintained by srccommit, do not edit manually.
*
*/
#define Module_MajorVersion_CMHG 4.90
#define Module_MajorVersion_CMHG 4.91
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 29 Sep 1999
#define Module_Date_CMHG 01 Oct 1999
#define Module_MajorVersion "4.90"
#define Module_Version 490
#define Module_MajorVersion "4.91"
#define Module_Version 491
#define Module_MinorVersion ""
#define Module_Date "29 Sep 1999"
#define Module_Date "01 Oct 1999"
#define Module_FullVersion "4.90"
#define Module_FullVersion "4.91"
s/PMF/osinit
View file @ d4596a38
......@@ -1206,7 +1206,11 @@ ConfigSMC669Table
; DCB &0B, 0 ; floppy data rates (default)
; DCB &0C, 0 ; UART2 & UART1 standard speed, UART2 standard mode,
; UART2 full duplex, XMIT active hi, RCV active hi (default)
DCB &10, 2_01000000 ; 24MHz input to PLL (*not* default)
[ ComboClock14MHz
; DCB &10, 2_00000000 ; 14.318MHz input to PLL (default)
|
DCB &10, 2_01000000 ; 24MHz input to PLL
]
; DCB &1E, &80 ; GAMECS disabled (default)
; DCB &1F, 0 ; floppy drive types (default)
DCB &20, &FC ; FDC@3F0-7
......
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