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Commit cdf980ed authored by Mike Stephens's avatar Mike Stephens
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First attempt at ARM9 support, and general clean-up of old ARM-specific code,... 

First attempt at ARM9 support, and general clean-up of old ARM-specific code, now using vectored ARMops.

Not tested.

Version 5.35, 4.79.2.14. Tagged as 'Kernel-5_35-4_79_2_14'
parent 587eb2dc
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Showing with 614 additions and 503 deletions
Docs/HAL/Notes
View file @ cdf980ed
......@@ -59,6 +59,7 @@ FA200000 32K SVC stack
FA300000 8K ABT stack
FA400000 8K UND stack
FAE00000 1M Reserved for physical memory accesses
FAF00000 256k reserved for DCache cleaner address space (eg. StrongARM)
FAFE8000 32K HAL workspace
FAFF0000 32K "Cursor/System/Sound" block (probably becoming just "System")
FAFF8000 32K "Nowhere"
......
VersionASM
View file @ cdf980ed
......@@ -13,12 +13,12 @@
GBLS Module_ComponentPath
Module_MajorVersion SETS "5.35"
Module_Version SETA 535
Module_MinorVersion SETS "4.79.2.13"
Module_Date SETS "10 Nov 2000"
Module_ApplicationDate2 SETS "10-Nov-00"
Module_ApplicationDate4 SETS "10-Nov-2000"
Module_MinorVersion SETS "4.79.2.14"
Module_Date SETS "09 Jan 2001"
Module_ApplicationDate2 SETS "09-Jan-01"
Module_ApplicationDate4 SETS "09-Jan-2001"
Module_ComponentName SETS "Kernel"
Module_ComponentPath SETS "RiscOS/Sources/Kernel"
Module_FullVersion SETS "5.35 (4.79.2.13)"
Module_HelpVersion SETS "5.35 (10 Nov 2000) 4.79.2.13"
Module_FullVersion SETS "5.35 (4.79.2.14)"
Module_HelpVersion SETS "5.35 (09 Jan 2001) 4.79.2.14"
END
VersionNum
View file @ cdf980ed
......@@ -4,19 +4,19 @@
*
*/
#define Module_MajorVersion_CMHG 5.35
#define Module_MinorVersion_CMHG 4.79.2.13
#define Module_Date_CMHG 10 Nov 2000
#define Module_MinorVersion_CMHG 4.79.2.14
#define Module_Date_CMHG 09 Jan 2001
#define Module_MajorVersion "5.35"
#define Module_Version 535
#define Module_MinorVersion "4.79.2.13"
#define Module_Date "10 Nov 2000"
#define Module_MinorVersion "4.79.2.14"
#define Module_Date "09 Jan 2001"
#define Module_ApplicationDate2 "10-Nov-00"
#define Module_ApplicationDate4 "10-Nov-2000"
#define Module_ApplicationDate2 "09-Jan-01"
#define Module_ApplicationDate4 "09-Jan-2001"
#define Module_ComponentName "Kernel"
#define Module_ComponentPath "RiscOS/Sources/Kernel"
#define Module_FullVersion "5.35 (4.79.2.13)"
#define Module_HelpVersion "5.35 (10 Nov 2000) (4.79.2.13)"
#define Module_FullVersion "5.35 (4.79.2.14)"
#define Module_HelpVersion "5.35 (09 Jan 2001) (4.79.2.14)"
hdr/KernelWS
View file @ cdf980ed
......@@ -257,6 +257,7 @@ SVCStackAddress * &FA200000
ABTStackAddress * &FA300000
UNDStackAddress * &FA400000
PhysicalAccess * &FAE00000
DCacheCleanAddress * &FAF00000 ; eg. for StrongARM, 256k of space, up to FAF40000
[ {FALSE}
CursorChunkAddress * &FAFF0000
|
......@@ -1152,22 +1153,26 @@ HAL_Descriptor # 4
HAL_Workspace # 4
HAL_WsSize # 4
ICache_Info # 0
ICache_NSets # 4
ICache_Size # 4
ICache_LineLen # 1
ICache_Associativity # 1
Cache_Type # 1
Cache_Flags # 1
DCache_Info # 0
DCache_NSets # 4
DCache_Size # 4
DCache_LineLen # 1
DCache_Associativity # 1
ProcessorArch # 1
ICache_Info # 0
ICache_NSets # 4
ICache_Size # 4
ICache_LineLen # 1
ICache_Associativity # 1
Cache_Type # 1
Cache_Flags # 1
DCache_Info # 0
DCache_NSets # 4
DCache_Size # 4
DCache_LineLen # 1
DCache_Associativity # 1
# 2
DCache_IndexBit # 4
DCache_IndexSegStart # 4
DCache_RangeThreshold # 4
ProcessorArch # 1
AlignSpace
......
s/ARM600
View file @ cdf980ed
This diff is collapsed.
s/ARMops
View file @ cdf980ed
This diff is collapsed.
s/Arthur3
View file @ cdf980ed
......@@ -2372,6 +2372,8 @@ Config_MonitorType_setcode
B ConfigMultiField
]
LTORG
MonitorTypeCMOSTable
& MonitorTypeAuto :SHR: MonitorTypeShift ; Auto value
& MonitorTypeF :SHR: MonitorTypeShift ; maximum valid number
......
s/KbdResPC
View file @ cdf980ed
......@@ -72,6 +72,8 @@ SpecialData
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[ :LNOT HAL
SetUpKbd
MOV r0, #IOBase
MOV r1, #ctl_Enable + ctl_EnableIRQ
......@@ -88,12 +90,12 @@ SetUpKbd
; Change test to check for IOMD_Original, rather than IOMD_7500, so we include IOMD_7500FE
; in the latter category
LDRB r1, [r0, #IOMD_ID0]
LDRB r2, [r0, #IOMD_ID1] ; safe to use r2, since SetUpKbdReturn corrupts it
ORR r1, r1, r2, LSL #8 ; straight away
LDR r2, =IOMD_Original
TEQ r1, r2
BEQ %FT30
LDRB r1, [r0, #IOMD_ID0]
LDRB r2, [r0, #IOMD_ID1] ; safe to use r2, since SetUpKbdReturn corrupts it
ORR r1, r1, r2, LSL #8 ; straight away
LDR r2, =IOMD_Original
TEQ r1, r2
BEQ %FT30
|
LDRB R1, [R0, #IOMD_ID0] ;Are we running on Morris
CMP R1, #&E7
......@@ -125,6 +127,8 @@ SetUpKbd
B SetUpKbdReturn
] ; :LNOT: HAL
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; On ARM600, this routine must work in IRQ32 mode
......
s/Kernel
View file @ cdf980ed
......@@ -1461,7 +1461,7 @@ PlatFeatSWI ROUT
BNE %FT50 ;No, so send out a service call
;Ok, it's the 'code_features' reason code.
LDRB r0,[r0, #ProcessorFlags]
LDR r0,[r0, #ProcessorFlags]
TST r0, #2 ;Is the 'no irq enable/disable' bit set?
ADRNE r1, platfeat_irqinsert ;Yep, so point R1 to the delay routine
MOVEQ r1, #0
......
s/MemInfo
View file @ cdf980ed
......@@ -210,7 +210,9 @@ MemoryConvert ROUT
70
TST r0, #flush_cache ; If any page has been made uncacheable in L2 then flush!
BLNE meminfo_flushplease
BEQ %FT75
MOV r0, #0
ARMop Cache_CleanInvalidateAll,,,r0
75
EXIT
......
s/NewReset
View file @ cdf980ed
......@@ -227,6 +227,15 @@ CmosScreenWillDo
LTORG
[ HAL
! 0, "*** DUMMY CONT_Break, soft breaks/resets will not work yet with HAL"
CONT_Break
B CONT_Break
]
[ :LNOT: HAL
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; Data tables: VIDC := mode 0, all palette black
......@@ -342,6 +351,7 @@ VIDCTAB
VIDCPhys * &03400000 ; used to address VIDC when MMU is off
; Entered here after RESET (or BREAK)
; This code must be capable of being executed at a non-ROM address and with the MMU off,
......@@ -499,9 +509,6 @@ SetUpKbdReturn
ARMA_drain_WB
ARMA_flush_IC
vectorpoke_notSA_1
[ ARM810support
ARM8_branchpredict_flush ;IMB on ARM810, and harmless on other ARMs
]
]
BIC r0, r0, #I32_bit ; and enable IRQs
......@@ -541,6 +548,9 @@ vectorpoke_notSA_1
BL Processor_Type ; Determines the processor type & stores it in page 0.
]
] ; :LNOT: HAL
Continue_after_HALInit
;StrongARM: OK, there is quite a bit of code poking below, to various addresses. We'll
......@@ -598,10 +608,10 @@ Continue_after_HALInit
[ CacheCMOSRAM
BL InitCMOSCache ; initialise cache of CMOS RAM
TEQ R0, #0 ; returns zero on failure
LDREQ R1, [R0, #HAL_StartFlags]
ORREQ R1, R1, #OSStartFlag_NoCMOS
STREQ R1, [R0, #HAL_StartFlags]
TEQ R0, #0 ; returns zero on failure
LDREQ R1, [R0, #HAL_StartFlags]
ORREQ R1, R1, #OSStartFlag_NoCMOS
STREQ R1, [R0, #HAL_StartFlags]
]
; Now copy the initialised data
......@@ -669,26 +679,11 @@ conversionSWIfill
CMP R2, #OS_ConvertFileSize+1
BNE conversionSWIfill
;StrongARM: OK, that completes the poking around, some of which is code. Now let's
; do a full IMB type thing, to be safe (if we're running on StrongARM)
[ StrongARM
ARM_read_ID R0
AND R0,R0,#&F000
CMP R0,#&A000
BNE afterpokingaround_notSA
MOV R1,#0
STRB R1,[R1,#SyncCodeA_sema] ;initialise semaphore to 0
MOV R1,#ARMA_Cleaner_flipflop
LDR R0,=ARMA_Cleaners_address ;note: we are initialising ARMA_Cleaner_flipflop here
STR R0,[R1]
ARMA_clean_DC R0,R1,R2
ARMA_drain_WB
ARMA_flush_IC
afterpokingaround_notSA
[ ARM810support
ARM8_branchpredict_flush ;IMB on ARM810, and harmless on other ARMs
]
]
; OK, that completes the poking around, some of which is code. Now let's
; do a full IMB type thing, to be safe
;
MOV r0, #0
ARMop IMB_Full,,,r0
; Initialise CAO ptr to none.
......@@ -738,79 +733,79 @@ kbdthere
[ ValidateCMOS :LAND: STB
; Do a POR if some super-critical values are shagged or if checksum is invalid.
MOV R3, #-1 ; do all RAM if we do any
MOV R3, #-1 ; do all RAM if we do any
BL ValChecksum ; Always check the checksum
BNE cmos_reset
BNE cmos_reset
; ScreenSizeCMOS, RAMDiscCMOS, SysHeapCMOS, RMASizeCMOS and SpriteSizeCMOS
; should be 0. Happily they are at consecutive addresses so we can loop through
; them.
MOV R1, #ScreenSizeCMOS
MOV R1, #ScreenSizeCMOS
reset_loop
MOV R0, R1
BL Read
TEQ R0, #0
BNE cmos_reset
INC R1
TEQ R1, #SpriteSizeCMOS
BHI reset_loop
MOV R0, R1
BL Read
TEQ R0, #0
BNE cmos_reset
INC R1
TEQ R1, #SpriteSizeCMOS
BHI reset_loop
[ {FALSE}
; FontCMOS should be <= 32 (128K)
; What on earth was this about? Why would anyone require FontSize to
; be less than 128K?
MOV R0, #FontCMOS
BL Read
CMP R0, #32
BHI cmos_reset
MOV R0, #FontCMOS
BL Read
CMP R0, #32
BHI cmos_reset
]
[ {FALSE}
; Oh, just leave it be
MOV R0, #VduCMOS
BL Read
MOV R0, #VduCMOS
BL Read
[ IOMD_C_MonitorType = 0 :LAND: IOMD_C_PALNTSCType = 0
; Force TV if we don't have a MonitorType auto-detect bit
TEQ R0, #(Sync_Separate :OR: MonitorType0)
TEQ R0, #(Sync_Separate :OR: MonitorType0)
|
; Force auto-detect of monitor stuff if we have a MonitorType auto-detect bit
TEQ R0, #(Sync_Auto :OR: MonitorTypeAuto)
TEQ R0, #(Sync_Auto :OR: MonitorTypeAuto)
]
BNE cmos_reset
BNE cmos_reset
]
; Year should be >=1995, <=2020
; (2020 is arbitrary, but everything breaks soon after that)
MOV R0, #YearCMOS+1
BL Read
TEQ R0, #19
BNE check20
MOV R0, #YearCMOS+1
BL Read
TEQ R0, #19
BNE check20
; 20th century: year should be 95 to 99
MOV R0, #YearCMOS
BL Read
CMP r0,#95
BLT cmos_reset
CMP r0,#99
BHI cmos_reset
B checkboot
MOV R0, #YearCMOS
BL Read
CMP r0,#95
BLT cmos_reset
CMP r0,#99
BHI cmos_reset
B checkboot
check20
TEQ R0, #20
BNE cmos_reset
TEQ R0, #20
BNE cmos_reset
; 21st century: year should <= 20
MOV R0, #YearCMOS
BL Read
CMP R0, #20
BHI cmos_reset
MOV R0, #YearCMOS
BL Read
CMP R0, #20
BHI cmos_reset
checkboot
; Bit 4 of DBTBCMOS should be 1 (Boot)
MOV R0, #DBTBCMOS
BL Read
TEQ R0, #(1:SHL:4)
BNE cmos_reset
MOV R0, #DBTBCMOS
BL Read
TEQ R0, #(1:SHL:4)
BNE cmos_reset
]
......@@ -819,7 +814,7 @@ checkboot
[ HAL
MOV R0, #HAL_StartFlags
LDR R1, [R0]
TST R1, #OSStartFlag_NoCMOS ; If no CMOS, reset for sensible cache
TST R1, #OSStartFlag_NoCMOS ; If no CMOS, reset for sensible cache
BNE cmos_reset
TST R1, #OSStartFlag_POR
BEQ no_cmos_reset
......@@ -996,12 +991,12 @@ dont_program_mousetype
[ MorrisSupport
MOV R8, #IOMD_Base
LDRB r0, [r8, #IOMD_ID0]
LDRB r1, [r8, #IOMD_ID1]
ORR r0, r0, r1, LSL #8
LDR r1, =IOMD_Original
TEQ r0, r1
BEQ dont_program_mousetype
LDRB r0, [r8, #IOMD_ID0]
LDRB r1, [r8, #IOMD_ID1]
ORR r0, r0, r1, LSL #8
LDR r1, =IOMD_Original
TEQ r0, r1
BEQ dont_program_mousetype
;
; Morris based machines use PS2 mice/tracker balls
;
......@@ -1064,19 +1059,19 @@ DefaultCMOSTable ; list of non-zero options wanted :
= KeyDelCMOS, 32
= KeyRepCMOS, 8
= MODETVCMOS, &10 ; TV 0,1
= StartCMOS, (2:SHL:3) ; NOCAPS
= DBTBCMOS, (1:SHL:4) ; Boot
= StartCMOS, (2:SHL:3) ; NOCAPS
= DBTBCMOS, (1:SHL:4) ; Boot
= YearCMOS, 00
= YearCMOS+1, 20
[ IOMD_C_MonitorType = 0 :LAND: IOMD_C_PALNTSCType = 0
; TV if we don't have a MonitorType auto-detect bit
= VduCMOS, Sync_Separate :OR: MonitorType0
= VduCMOS, Sync_Separate :OR: MonitorType0
|
; auto-detect if we have a MonitorType auto-detect bit
= VduCMOS, Sync_Auto :OR: MonitorTypeAuto
= VduCMOS, Sync_Auto :OR: MonitorTypeAuto
]
= MouseStepCMOS, 2
= SystemSpeedCMOS, (1:SHL:2):OR:(1:SHL:4):OR:(0:SHL:5)
= SystemSpeedCMOS, (1:SHL:2):OR:(1:SHL:4):OR:(0:SHL:5)
; Delete-etc reset
; WimpMode auto
; Cache on
......@@ -1773,31 +1768,13 @@ ResetPart1Done ; R0 is reset type
LDR R1, RealIRQHandler
STR R1, [R0, #&18]
[ StrongARM
;for StrongARM, we need to do an IMB type thing for modifying code in vector area, and
;for copying irq handler code
ARM_read_ID r1
AND r1,r1,#&F000
CMP r1,#&A000
BNE furtherpoke_notSA
;first, we clean one cache entry, 0..1F, = vector area
MOV r1,#0
ARMA_clean_DCentry r1
;next, we clean DefaultIRQ1V code area
LDR r0,=DefaultIRQ1V
ADD r1,r0,#(DefaultIRQ1Vcode_end - DefaultIRQ1Vcode)
ARMA_clean_DCrange r0,r1
;and then we synch IC
ARMA_drain_WB
ARMA_flush_IC
MOV r0,#0 ;restore r0 as zero base
furtherpoke_notSA
[ ARM810support
ARM8_branchpredict_flush ;IMB on ARM810, and harmless on other ARMs
]
]
;we need to do an IMB type thing for modifying code in vector area,
;and for copying irq handler code
;
Push "r0"
MOV r0, #0
ARMop IMB_Full,,,r0
Pull "r0"
[ :LNOT:No26bitCode
......@@ -2134,7 +2111,7 @@ PT_lookup
LDR R2,[R1],#4
TEQ R2,#0
MOVMI R0,#0
STRMIB R2,[R0,#ProcessorType]
STRMI R2,[R0,#ProcessorType]
MOVMI PC,LR
TEQ R2,R0
ADDNE R1,R1,#8
......@@ -2142,7 +2119,7 @@ PT_lookup
LDMIA R1,{R0,R2}
MOV R1,#0
STRB R0,[R1,#ProcessorType]
STRB R2,[R1,#ProcessorFlags]
STR R2,[R1,#ProcessorFlags]
MOV PC,LR
]
......
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