A few fixes to the flash upgrade code.

Version 4.74. Tagged as 'Kernel-4_74'

VersionASM

@@ -6,9 +6,9 @@
 			GBLS	Module_MinorVersion
 			GBLS	Module_Date
 			GBLS	Module_FullVersion
-Module_MajorVersion	SETS    "4.73"
-Module_Version          SETA    473
+Module_MajorVersion	SETS    "4.74"
+Module_Version          SETA    474
 Module_MinorVersion	SETS	""
 Module_Date		SETS    "14 Apr 1999"
-Module_FullVersion      SETS    "4.73"
+Module_FullVersion      SETS    "4.74"
                         END

VersionNum

-/* (4.73)
+/* (4.74)
  *
  * This file is automatically maintained by srccommit, do not edit manually.
  *
  */
-#define Module_MajorVersion_CMHG     	4.73
+#define Module_MajorVersion_CMHG     	4.74
 #define Module_MinorVersion_CMHG	
 #define Module_Date_CMHG      		14 Apr 1999
 
-#define Module_MajorVersion     	"4.73"
-#define Module_Version                  473
+#define Module_MajorVersion     	"4.74"
+#define Module_Version                  474
 #define Module_MinorVersion		""
 #define Module_Date      		"14 Apr 1999"
 
-#define Module_FullVersion              "4.73"
+#define Module_FullVersion              "4.74"

s/FlashROM

@@ -131,7 +131,7 @@ FR_InitVideo    ROUT
         MOV     R2,#&000001
         ORR     R2,R2,#&000100
         ORR     R2,R2,#&010000
-        MOV     R3,#255
+        MOV     R3,#256
 03      STR     R1,[R10]
         ADD     R1,R1,R2
         SUBS    R3,R3,#1
@@ -165,7 +165,7 @@ FR_VFPch       * 1
 FR_InitVidRegs  ROUT
         DCD     &E0000000+(FR_FIFO:SHL:8)+(FR_BPP:SHL:5)+(FR_PixelRate:SHL:2)+FR_ClockSource
         DCD     &D0000000+&C288
-        DCD     &80000000+FR_HSync+FR_HLBdr+FR_HDisp+FR_HRBdr+FR_HFPch-8
+        DCD     &80000000+FR_HSync+FR_HBPch+FR_HLBdr+FR_HDisp+FR_HRBdr+FR_HFPch-8
         DCD     &81000000+FR_HSync-8
         DCD     &82000000+FR_HSync+FR_HBPch-12
         DCD     &83000000+FR_HSync+FR_HBPch+FR_HLBdr-18
@@ -176,7 +176,7 @@ FR_InitVidRegs  ROUT
         DCD     &92000000+FR_VSync+FR_VBPch-1
         DCD     &93000000+FR_VSync+FR_VBPch+FR_VTBdr-1
         DCD     &94000000+FR_VSync+FR_VBPch+FR_VTBdr+FR_VDisp-1
-        DCD     &90000000+FR_VSync+FR_VBPch+FR_VTBdr+FR_VDisp+FR_VBBdr-1
+        DCD     &95000000+FR_VSync+FR_VBPch+FR_VTBdr+FR_VDisp+FR_VBBdr-1
         DCD     &40008000
         DCD     &C0000000+(1:SHL:12)+3
         DCD     &D0000000+&C080+((FR_ModV-1):SHL:8)+(FR_ModR-1)
@@ -189,7 +189,7 @@ FR_FillScreen   ROUT
         LDR     R1,=FR_ScreenBase
         MOV     R2,#((256:SHL:16)/600):AND:&00FF
         ORR     R2,R2,#((256:SHL:16)/600):AND:&FF00
-        MOV     R3,R3
+        MOV     R3,R2
         MOV     R4,#FR_VDisp
 01      MOV     R5,#FR_HDisp
         MOV     R0,R3,LSR #16
@@ -252,7 +252,7 @@ FR_InitParallel ROUT
 ; Write CR4
         MOV     R0,#4
         STRB    R0,[R1]
-        MOV     R0,#&04         ; CR4=&03 (ECP & EPP mode)
+        MOV     R0,#&03         ; CR4=&03 (ECP & EPP mode)
         STRB    R0,[R1,#4]
 ; Write ECR
         MOV     R0,#&34         ; PS/2 Parallel Port mode, DMA off, interrupts off
@@ -277,9 +277,6 @@ FR_CopyBlockStart
 ; Dont use literals from here on in - the assembler's liable to pull them
 ; the non-RAM stuff above.
 
-FR_StackBaseVal    & FR_StackBase
-FR_TransferBuffVal & FR_TransferBuffAddr
-
 ; Code from here on gets copied to RAM (at FR_RAMCodeAddr) and run from there.
 
 FR_RAMCodeStart
@@ -667,6 +664,9 @@ FR_VerifyError
         MOV     R0,#FR_VerifyErrorState-FR_BorderStateTable
         B       FR_Error
 
+FR_StackBaseVal    & FR_StackBase
+FR_TransferBuffVal & FR_TransferBuffAddr
+
 FR_RAMCodeEnd
 
         END