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Jeffrey Lee authored
Detail: s/ARMops - In Analyse_WB_CR7_Lx, we need to check against Cache_Lx_MaxLevel*2, because the cache size selection register counts I + D caches separately Admin: Tested on IGEPv5 Version 5.35, 4.79.2.281. Tagged as 'Kernel-5_35-4_79_2_281'
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