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; > TestSrc.ARM3
TTL RISC OS 2+ POST ARM version determination
;
; Reads ARM3 version register, returns 0 if ARM 2 fitted.
;
;------------------------------------------------------------------------
; History
;
; Date Name Comment
; ---- ---- -------
; 20-Apr-89 ArtG Initial version
;
;
;------------------------------------------------------------------------
A3Cid CN 0
A3Cfls CN 1
A3Cmod CN 2
A3Ccac CN 3
A3Cupd CN 4
A3Cdis CN 5
A3CON CP 15
ts_ARM_type
MOV r13,lr
;
; First, set up an undefined instruction vector to catch an ARM 2
; (or a faulty ARM 3 ??) when the copro instruction is run.
; Only applies on systems where ROM isn't mapped at zero.
[ CPU_Type = "ARM2" :LOR: CPU_Type = "ARM3"
MOV r0,#0 ; set a page at logical 0
MOV r1,r0
BL ts_set_cam
ADR r0,ts_ARM_undefined
LDMIA r0,{r2,r3}
MOV r1,#4
STMIA r1,{r2,r3} ; set the undefined instruction trap
]
;
; Read ARM3C0 version I.D.
;
MOV r0, #(-1) ; should always be altered
MRC A3CON,0,r0,A3Cid,A3Cid ; Read control register 0
MOV r12, r0
[ CPU_Type = "ARM2" :LOR: CPU_Type = "ARM3"
MOV r1,#0
BL ts_set_cam_idle ; remove the vector page again
]
MOVS r0, r12 ; return the ID (0 for ARM 2)
MOV pc,r13
;
; Trap to be taken when ARM 2 is fitted
;
ts_ARM_undefined
MOV r0,#0
MOVS pc,r14_svc
10
ASSERT ((%10 - ts_ARM_undefined) / 4 = 2)
END