• Jeffrey Lee's avatar
    Add ARMops for PL310 L2 cache controller · 6eb6ee2a
    Jeffrey Lee authored
    Detail:
      Unlike on the Cortex-A8 or Cortex-A15, the L2 cache that's used with the Cortex-A9 isn't hooked up to the standard ARMv7 CP15 cache maintenance ops. Instead, memory-mapped registers must be used to program and maintain the cache.
      Since the PL310 can't be detected automatically, this change adds support for a 'cache controller' HAL device which the HAL can use to advertise the presence of any external caches. If a cache device is registered during HAL_InitDevices the kernel will then check it against a list of known cache types and replace the appropriate ARMop routines with the alternatives for that controller.
      File changes:
      - hdr/PL310 - New header containing PL310 register listing
      - Makefile - Add export for PL310 header. Reorder exports to be alphabetical
      - hdr/HALDevice - Add cache controller device type, PL310 device
      - hdr/KernelWS - Allocate some workspace for storing a pointer to the current cache HAL device
      - s/ARMops - Add code for searching for known cache types, and implementation of PL310-specific ARMops
      - s/GetAll - Get Hdr:PL310
      - s/NewReset - Look for a cache controller after calling HAL_InitDevices
    Admin:
      Tested on Pandaboard
      Fixes various assorted instability issues
    
    
    Version 5.35, 4.79.2.252. Tagged as 'Kernel-5_35-4_79_2_252'
    6eb6ee2a
KernelWS 72.6 KB