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; Copyright 2000 Pace Micro Technology plc
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
; The layout of the HAL descriptor
^ 0
HALDesc_Flags # 4
HALDesc_Start # 4
HALDesc_Size # 4
HALDesc_Entries # 4
HALDesc_NumEntries # 4
HALDesc_Workspace # 4
HALDesc_VideoRAMSize # 4
HALDesc_size # 4
HALFlag_NCNBWorkspace * 1:SHL:0
HALFlag_LimitVideoRAM * 1:SHL:1
; Entries to the HAL from the OS
^ 0
EntryNo_HAL_Init # 1 ; 0
EntryNo_HAL_IRQEnable # 1 ; 1
EntryNo_HAL_IRQDisable # 1 ; 2
EntryNo_HAL_IRQClear # 1 ; 3
EntryNo_HAL_IRQSource # 1 ; 4
EntryNo_HAL_IRQStatus # 1 ; 5
EntryNo_HAL_FIQEnable # 1 ; 6
EntryNo_HAL_FIQDisable # 1 ; 7
EntryNo_HAL_FIQDisableAll # 1 ; 8
EntryNo_HAL_FIQClear # 1 ; 9
EntryNo_HAL_FIQSource # 1 ; 10
EntryNo_HAL_FIQStatus # 1 ; 11
EntryNo_HAL_Timers # 1 ; 12
EntryNo_HAL_TimerDevice # 1 ; 13
EntryNo_HAL_TimerGranularity # 1 ; 14
EntryNo_HAL_TimerMaxPeriod # 1 ; 15
EntryNo_HAL_TimerSetPeriod # 1 ; 16
EntryNo_HAL_TimerPeriod # 1 ; 17
EntryNo_HAL_TimerReadCountdown # 1 ; 18
EntryNo_HAL_CounterRate # 1 ; 19
EntryNo_HAL_CounterPeriod # 1 ; 20
EntryNo_HAL_CounterRead # 1 ; 21
EntryNo_HAL_CounterDelay # 1 ; 22
EntryNo_HAL_NVMemoryType # 1 ; 23
EntryNo_HAL_NVMemorySize # 1 ; 24
EntryNo_HAL_NVMemoryPageSize # 1 ; 25
EntryNo_HAL_NVMemoryProtectedSize # 1 ; 26
EntryNo_HAL_NVMemoryProtection # 1 ; 27
EntryNo_HAL_NVMemoryIICAddress # 1 ; 28
EntryNo_HAL_NVMemoryRead # 1 ; 29
EntryNo_HAL_NVMemoryWrite # 1 ; 30
EntryNo_HAL_IICBuses # 1 ; 31
EntryNo_HAL_IICType # 1 ; 32
EntryNo_HAL_IICSetLines # 1 ; 33
EntryNo_HAL_IICReadLines # 1 ; 34
EntryNo_HAL_IICDevice # 1 ; 35
EntryNo_HAL_IICTransfer # 1 ; 36
EntryNo_HAL_IICMonitorTransfer # 1 ; 37
EntryNo_HAL_VideoFlybackDevice # 1 ; 38
EntryNo_HAL_VideoSetMode # 1 ; 39
EntryNo_HAL_VideoWritePaletteEntry # 1 ; 40
EntryNo_HAL_VideoWritePaletteEntries # 1 ; 41
EntryNo_HAL_VideoReadPaletteEntry # 1 ; 42
EntryNo_HAL_VideoSetInterlace # 1 ; 43
EntryNo_HAL_VideoSetBlank # 1 ; 44
EntryNo_HAL_VideoSetPowerSave # 1 ; 45
EntryNo_HAL_VideoUpdatePointer # 1 ; 46
EntryNo_HAL_VideoSetDAG # 1 ; 47
EntryNo_HAL_VideoVetMode # 1 ; 48
EntryNo_HAL_VideoPixelFormats # 1 ; 49
EntryNo_HAL_VideoFeatures # 1 ; 50
EntryNo_HAL_VideoBufferAlignment # 1 ; 51
EntryNo_HAL_VideoOutputFormat # 1 ; 52
EntryNo_HAL_IRQProperties # 1 ; 53 (was HAL_MatrixColumns)
EntryNo_HAL_IRQSetCores # 1 ; 54 (was HAL_MatrixScan)
EntryNo_HAL_IRQGetCores # 1 ; 55 (was HAL_TouchscreenType)
EntryNo_HAL_CPUCount # 1 ; 56 (was HAL_TouchscreenRead)
EntryNo_HAL_CPUNumber # 1 ; 57 (was HAL_TouchscreenMode)
EntryNo_HAL_SMPStartup # 1 ; 58 (was HAL_TouchscreenMeasure)
EntryNo_HAL_MachineID # 1 ; 59, ReadSysInfo 2
EntryNo_HAL_ControllerAddress # 1 ; 60, Memory 9
EntryNo_HAL_HardwareInfo # 1 ; 61, ReadSysInfo 2
EntryNo_HAL_SuperIOInfo # 1 ; 62, ReadSysInfo 3
EntryNo_HAL_PlatformInfo # 1 ; 63, ReadSysInfo 8
EntryNo_HAL_CleanerSpace # 1 ; 64
EntryNo_HAL_UARTPorts # 1 ; 65
EntryNo_HAL_UARTStartUp # 1 ; 66
EntryNo_HAL_UARTShutdown # 1 ; 67
EntryNo_HAL_UARTFeatures # 1 ; 68
EntryNo_HAL_UARTReceiveByte # 1 ; 69
EntryNo_HAL_UARTTransmitByte # 1 ; 70
EntryNo_HAL_UARTLineStatus # 1 ; 71
EntryNo_HAL_UARTInterruptEnable # 1 ; 72
EntryNo_HAL_UARTRate # 1 ; 73
EntryNo_HAL_UARTFormat # 1 ; 74
EntryNo_HAL_UARTFIFOSize # 1 ; 75
EntryNo_HAL_UARTFIFOClear # 1 ; 76
EntryNo_HAL_UARTFIFOEnable # 1 ; 77
EntryNo_HAL_UARTFIFOThreshold # 1 ; 78
EntryNo_HAL_UARTInterruptID # 1 ; 79
EntryNo_HAL_UARTBreak # 1 ; 80
EntryNo_HAL_UARTModemControl # 1 ; 81
EntryNo_HAL_UARTModemStatus # 1 ; 82
EntryNo_HAL_UARTDevice # 1 ; 83
EntryNo_HAL_UARTDefault # 1 ; 84
EntryNo_HAL_DebugRX # 1 ; 85
EntryNo_HAL_DebugTX # 1 ; 86
EntryNo_HAL_PCIFeatures # 1 ; 87
EntryNo_HAL_PCIReadConfigByte # 1 ; 88
EntryNo_HAL_PCIReadConfigHalfword # 1 ; 89
EntryNo_HAL_PCIReadConfigWord # 1 ; 90
EntryNo_HAL_PCIWriteConfigByte # 1 ; 91
EntryNo_HAL_PCIWriteConfigHalfword # 1 ; 92
EntryNo_HAL_PCIWriteConfigWord # 1 ; 93
EntryNo_HAL_PCISpecialCycle # 1 ; 94
EntryNo_HAL_PCISlotTable # 1 ; 95
EntryNo_HAL_PCIAddresses # 1 ; 96
EntryNo_HAL_PlatformName # 1 ; 97, ReadSysInfo 9 subreason 7 (was HAL_ATAControllerInfo)
# 1 ; 98 (was HAL_ATASetModes)
# 1 ; 99 (was HAL_ATACableID)
EntryNo_HAL_InitDevices # 1 ; 100
EntryNo_HAL_KbdScanDependencies # 1 ; 101
# 1 ; 102 (was HAL_KbdScan)
# 1 ; 103 (was HAL_KbdScanFinish)
# 1 ; 104 (was HAL_KbdScanInterrupt)
EntryNo_HAL_PhysInfo # 1 ; 105
EntryNo_HAL_Reset # 1 ; 106
EntryNo_HAL_IRQMax # 1 ; 107 (was HAL_MonitorLeadID)
EntryNo_HAL_USBControllerInfo # 1 ; 108
EntryNo_HAL_USBPortPower # 1 ; 109
EntryNo_HAL_USBPortIRQStatus # 1 ; 110
EntryNo_HAL_USBPortIRQClear # 1 ; 111
EntryNo_HAL_USBPortDevice # 1 ; 112
EntryNo_HAL_TimerIRQClear # 1 ; 113
EntryNo_HAL_TimerIRQStatus # 1 ; 114
EntryNo_HAL_ExtMachineID # 1 ; 115, ReadSysInfo 10
EntryNo_HAL_VideoFramestoreAddress # 1 ; 116
EntryNo_HAL_VideoRender # 1 ; 117
EntryNo_HAL_VideoStartupMode # 1 ; 118
EntryNo_HAL_VideoPixelFormatList # 1 ; 119
EntryNo_HAL_VideoIICOp # 1 ; 120
EntryNo_HAL_Watchdog # 1 ; 121
KnownHALEntries # 0 ; Used inside Kernel
; Various flags and constants
; OS_Hardware subreasons
^ 0
OSHW_CallHAL # 1
OSHW_LookupRoutine # 1
OSHW_DeviceAdd # 1
OSHW_DeviceRemove # 1
OSHW_DeviceEnumerate # 1
OSHW_DeviceEnumerateChrono # 1
OSHW_MaxSubreason # 1 ; Used in despatch inside Kernel
; PhysInfo
^ 0
PhysInfo_GetTableSize # 1
PhysInfo_WriteTable # 1
PhysInfo_HardROM # 1
; NVMemory
NVMemoryFlag_None * 0
NVMemoryFlag_MaybeIIC * 1
NVMemoryFlag_IIC * 2
NVMemoryFlag_HAL * 3
NVMemoryFlag_Provision * &FF ; mask for provision
NVMemoryFlag_ProtectAtEnd * 1:SHL:8 ; Protected region at end
NVMemoryFlag_Deprotectable * 1:SHL:9
NVMemoryFlag_LowRead * 1:SHL:10 ; locations 0-15 are readable
NVMemoryFlag_LowWrite * 1:SHL:11 ; locations 0-15 are writeable
; IIC
IICFlag_LowLevel * 1:SHL:0
IICFlag_HighLevel * 1:SHL:1
IICFlag_MultiMaster * 1:SHL:2
IICFlag_Slave * 1:SHL:3
IICFlag_Background * 1:SHL:4
IICFlag_Fast * 1:SHL:16
IICFlag_HighSpeed * 1:SHL:17
IICFlag_ProtocolVersionShift * 20
IICFlag_ProtocolVersionMask * &FFF ; IIC protocol version x100
^ 0
IICStatus_Completed # 1 ; High level API return codes
IICStatus_InProgress # 1
IICStatus_NoACK # 1
IICStatus_Busy # 1
IICStatus_Slave # 1
IICStatus_Error # 1
; USB
^ 0
HALUSBControllerInfo_Type # 4 ; As below
HALUSBControllerInfo_Flags # 4 ; As below
HALUSBControllerInfo_HW # 4 ; Hardware base address
HALUSBControllerInfo_DevNo # 4 ; IRQ device number
HALUSBControllerInfo_SizeOf # 0 ; Size of base structure
^ HALUSBControllerInfo_SizeOf
HALUSBControllerInfo_DMAOffset # 4 ; Offset from ARM physical -> DMA addresses
HALUSBControllerInfo_HW_MPHI # 4 ; Message based Parallel Host Interface base address
HALUSBControllerInfo_DevNo_MPHI # 4 ; IRQ device number
HALUSBControllerInfo_SizeOfType3 # 0 ; Size of extended structure for Synopsys DWC
HALUSBControllerType_OHCI * 0
HALUSBControllerType_EHCI * 1
HALUSBControllerType_MUSBMHDRC * 2
HALUSBControllerType_SynopsysDWC * 3
HALUSBControllerType_XHCI * 4
HALUSBControllerFlag_HAL_Port_Power * 1 ; Use HAL_USBPortPower
HALUSBControllerFlag_HAL_Over_Current * 2 ; Use HAL_USBPortDevice/IRQStatus/IRQClear
HALUSBControllerFlag_32bit_Regs * 8 ; Must use 32bit access for all registers
HALUSBControllerFlag_XHCI_No_Offset * &40000000 ; The HW base address is true
HALUSBControllerFlag_EHCI_ETTF * &80000000 ; EHCI controller has embedded TT
; IRQ
HALIRQ_Shared * &80000000 ; Used with some APIs to indicate device/IRQ number is shared by multiple devices
; HAL_IRQProperties flags:
HALIRQProperty_Multicore * &80000000 ; Interrupt can be routed to multiple cores at once
HALIRQProperty_Private * &40000000 ; Interrupt enable/disable will only have an effect if it's called on a core which the interrupt is routed to, and if it's routed to multiple cores it may not affect them all
END