Commit f969f059 authored by William Turner's avatar William Turner
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Ursula version of DualSerial with CMOS bit checking for backwards compat.

FWIW, the CMOS bit is 0x0b:7. Also set to use separate IRQs for Port1/Port2
parent 5431cfdd
......@@ -29,4 +29,34 @@ anything about the data format required.
An additional problem is that we need to retain as much backwards compatibility
as possible, namely OS_SerialOps etc.
as possible, namely OS_SerialOps etc. Here, we are faced with three basic options;
either 1) have port1 automatically change between the two at will, 2) provide
some backwards-compatibility layer over the new style, or 3) Rely on the user
to decide whether port1 is 'new' or 'old'.
The first way of doing things works from a lockout point of view when
starting to use OS_SerialOps. When the first OS_SerialOp is seen, the DeviceFS
port1 device can be opened by the OS, thus preventing its use. However, SerialOps
are not claimed/released like devicefs devices, so it is not possible to tell
when the OS_SerialOp user has finished, and it's safe to close the port1 device
such that it may be used.
The second method was tried for Daytona, and it was found to be unsuccessful, as
the OS_SerialOps work at a lower level than the new system, and thus not all
things could be implemented in a backwards compatible manner.
This leaves us with the only option of providing some sort of user interface
such that they can decide at a given time, which way port1 is going to behave.
Port2 will always be 'new' style interface. The way chosen to implement this is
to have a configure option (and cmos bit) to set it permanently (defaults to
backwards compatible), and also a *command so that it can be toggled at any
time. It may be the case that this is unnecessary if the DeviceClaim protocol
is properly followed. Investigations to follow
Investigations: It appears that if the old serial stuff is active when the new
stuff is loaded, the new stuff doesn't claim port1. So, it should be relatively
simple to have a cfg bit that prevents or not port1 initialising. As for the
'on the fly' aspect, that should be simply a case of rmreiniting old then new,
after changing the soft copy of the bit.
THE CFG BIT IS NOW IMPLEMENTED: CMOS BYTE 0x0b, bit 7. 1 indicates b/w compat
\ No newline at end of file
......@@ -7,12 +7,6 @@
<BODY BGCOLOR="#ffffff">
<CENTER>
<H1>
NOTE: THIS VERSION OF THE CODE CONTAINS IOCtls 11 AND 12, WHICH WERE ADDED FOR DAYTONA BUT ARE NOT DOCUMENTED IN THIS F.S.
</H1>
</CENTER>
<CENTER>
<H1>
Serial Interface Specification
......@@ -22,12 +16,12 @@
<HR>
<CENTER>
<TABLE BORDER=0 WIDTH=40%>
<TR><TD>Document ref: <TD>Not yet issued
<TABLE BORDER=0 WIDTH=60%>
<TR><TD>Document ref: <TD>1309,424/FS
<TR><TD>Project: <TD>
<TR><TD>Revision: <TD>0.03
<TR><TD>Date: <TD>16-Jun-1997
<TR><TD>Author(s): <TD>Rich Buckley
<TR><TD>Revision: <TD>0.04
<TR><TD>Date: <TD>18-Aug-1998
<TR><TD>Author(s): <TD>Rich Buckley, William Turner
<TR><TD>AMR: <TD>
</TABLE>
</CENTER>
......@@ -55,7 +49,7 @@
<H2> <A NAME="overview"> 1.0 Overview </A> </H2>
On a Network Computer the two serial ports supported by the SuperIO device have their interrupts wired-ORed together to form a shared interrupt. To support this change in interrupt architecture changes were required to the RiscOS serial device drivers. This resulted in a completely different machanism for handling serial type devices and passing data to and from them.
On modern Acorn hardware, there are two serial ports supported by the combo chip. In order for both these to be supported, a different mechanism for handling serial type devices and passing data to and from them is required.
<p>
This documentation describes the programmers interface provided by the new serial device driver. It is intended that any other serial/uart type devices that are to be supported under RiscOS and NC-OS will conform to this interface but use a different device name. Device names will be allocated by Acorn.
......@@ -74,7 +68,7 @@ This documentation describes the programmers interface provided by the new seria
<h3> <a name="ioctlsupport"> 3.1 IOCtl support </a> </h3>
The modules FileSwitch and DeviceFS now support IOCtl's. This allows a device driver to receive a control command from an application based on either an open file handle or a directory path in DeviceFS as required by the serial module. The following modifications have taken place to achieve this support.
The modules FileSwitch and DeviceFS now support IOCtls. This allows a device driver to receive a control command from an application based on either an open file handle or a directory path in DeviceFS as required by the serial module. The following modifications have taken place to achieve this support.
<h4> <a name="fileswitch" > 3.1.1 FileSwitch (2.36)</a> </h4>
......@@ -167,10 +161,10 @@ DeviceFS also establishes an environment variable to allow simpler access to thi
<h3> <a name="ports"> 5.2 Ports </a> </h3>
The serial module registers a number of streams (files) within the DeviceFS filing system. Any application wishing to see what ports are available would enumerate the contents of the directory <code>devices:$</code>. The following streams are present for NC hardware.
The serial module registers a number of streams (files) within the DeviceFS filing system. Any application wishing to see what ports are available would enumerate the contents of the directory <code>devices:$</code>. The following streams are present for NC and Phoebe hardware (serial1 not present on the latter if port1 is in backwards-compatible mode).
<ul>
<li> <code>serial1</code> - serial port 1 on the combo chip
<li> <code>serial2</code> - serial port 2 on the combo chip (IrDa capable depending upon device)
<li> <code>serial2</code> - serial port 2 on the combo chip
</ul>
<p>
Support for further serial devices would require device name allocations with the relavent driver registering the new device with DeviceFS alongside the existing ports. Examples would be <code>serial3:</code>, <code>modem1:</code>.
......@@ -287,6 +281,23 @@ Direct control of the serial port control lines can be achieved using the <a hre
<li> read will return an undefined value.
</ul>
<li> read IR capability of port :
<ul>
<li> bit 0 : IrDA capable
<LI> bit 1 : ConsumerIR capable
<LI> bit 2 : ASK-IR capable
<LI> bits 3-31: Reserved
</ul>
<li> set/read IR status of port :
<ul>
<li> 0 : Wired
<LI> 1 : IrDA
<LI> 2 : ConsumerIR capable
<LI> 3 : ASK-IR capable
<LI> All other values reserved
</ul>
</ol>
<h3> <a name="datatransfer"> 5.5 Data transfer </a> </h3>
......@@ -367,7 +378,7 @@ An event is generated whenever DSR or DCD change or when a line error (parity, f
<H2> <A NAME="organisation"> 8.0 Product organisation </A> </H2>
Requires modules FileSwitch (2.36), BufferManager (0.25), DeviceFS (0.34) or greater. These modules are contained within NC-OS release 1.06 and greater.
Requires modules FileSwitch (2.36), BufferManager (0.25), DeviceFS (0.34) or greater. These modules are contained within NC-OS release 1.06 and greater, and also in RISCOS 4
<HR>
......@@ -391,6 +402,7 @@ Requires modules FileSwitch (2.36), BufferManager (0.25), DeviceFS (0.34) or gre
<TR><TD>0.01 <TD>RWB <TD>22 Jan 1997 <TD> Created based on Acorn internal documentation.
<tr><td>0.02 <td>RWB <td>30 Jan 1997 <td> Reformatted.
<tr><td>0.03 <td>RWB <td>17 Jun 1997 <td> Added IOCtl 10 for flushing buffers
<TR><TD>0.04 <TD>WT <TD>18 Aug 1998 <TD> Added IOCtls 11 and 12 for Phoebe
</TABLE>
......
......@@ -4,8 +4,8 @@
GBLS VString
GBLS Date
Version SETA 020
VString SETS "0.20"
Date SETS "10 Jul 1997"
Version SETA 021
VString SETS "0.21"
Date SETS "20 Aug 1998"
END
......@@ -67,6 +67,8 @@
; 0.20 10-Jul-97 BAL Fixed problem killing module when two serial
; ports.
; Added IOCtl to flush a buffer.
; 0.21 20-Aug-98 WT Added IOCtls for IR on port2, switch to allow
; SeparateIRQs
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
......@@ -105,6 +107,12 @@ debug SETL false ; to include debug macros
border_handshake SETL false ; to flash border when handshaking
counting SETL false ; to count stuff
GBLL CMOS_BackCompat
CMOS_BackCompat SETL {TRUE}
GBLL SeparateIRQs
SeparateIRQs SETL {TRUE}
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;
; Debug header files
......
......@@ -122,6 +122,33 @@ MSR_RI_active * 1 :SHL: 6 ; RI state
MSR_DCD_active * 1 :SHL: 7 ; DCD state
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;
; Bits in Combochip SP2 IR control register
IR_RxP_High * 0 :SHL: 0
IR_RxP_Low * 1 :SHL: 0
IR_TxP_High * 0 :SHL: 1
IR_TxP_Low * 1 :SHL: 1
IR_Dpx_Full * 0 :SHL: 2
IR_Dpx_Half * 1 :SHL: 2
IR_Typ_Std * 0 :SHL: 3
IR_Typ_IrDA * 1 :SHL: 3
IR_Typ_ASK * 2 :SHL: 3
IR_Loc_SPx * 0 :SHL: 6
IR_Loc_IRx * 1 :SHL: 6
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Combo * &03010000
SMIindex * &3A8
SMIaccess * &3AC
SMIENBL1 * &0C
Serial1_DevNo * 10
Serial2_DevNo * 40
serial1_bit * 8
serial2_bit * 4
Port1_IRCapability * 0
Port2_IRCapability * 4
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;
......@@ -322,7 +349,64 @@ hardware_claim ENTRY "r0-r4"
LDR r3, Flags ; own the vector ?
TST r3, #flag_OwnIRQ
BNE %10
[ SeparateIRQs
TST r3, #flag_Port1Present
BEQ %FT05
MOV r0, #Serial1_DevNo
ADDR r1, handle_irq1
MOV r2, wp
SWI XOS_ClaimDeviceVector
STRVS r0, [sp]
PullEnv VS
BVS make_error
05
TST r3, #flag_Port2Present
BEQ %FT10
MOV r0, #Serial2_DevNo
ADDR r1, handle_irq2
MOV r2, wp
SWI XOS_ClaimDeviceVector
STRVS r0, [sp]
PullEnv VS
BVS make_error
LDR r3, Flags ; we now the vector
ORR r3, r3, #flag_OwnIRQ
STR r3, Flags
10
;Now switch the IRQs on
TST r3, #flag_Port1Present
BEQ %FT15
MOV lr, pc ; disable IRQs and FIQs
ORR r1, lr, #I_bit
ORR r1, r1, #F_bit
TEQP r1, #0
NOP
LDR r1, =Combo ; look at Combo
MOV r0, #SMIENBL1
STR r0, [r1, #SMIindex]
LDR r0, [r1, #SMIaccess]
ORR r0, r0, #serial1_bit
STR r0, [r1, #SMIaccess]
TEQP lr, #0 ; restore IRQs and FIQs
NOP
15
TST r3, #flag_Port2Present
BEQ %FT16
MOV lr, pc ; disable IRQs and FIQs
ORR r1, lr, #I_bit
ORR r1, r1, #F_bit
TEQP r1, #0
NOP
LDR r1, =Combo ; look at Combo
MOV r0, #SMIENBL1
STR r0, [r1, #SMIindex]
LDR r0, [r1, #SMIaccess]
ORR r0, r0, #serial2_bit
STR r0, [r1, #SMIaccess]
TEQP lr, #0 ; restore IRQs and FIQs
NOP
|
MOV r0, #Serial_DevNo
ADDR r1, handle_irq
MOV r2, wp
......@@ -346,9 +430,12 @@ hardware_claim ENTRY "r0-r4"
STRB r0, [r1, #IOCIRQMSKB]
TEQP lr, #0 ; restore IRQs
NOP
]
16
[ debug
; DLINE "claim complete"
]
10
EXITS
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
......@@ -363,6 +450,29 @@ hardware_release ENTRY "r0-r4"
TST r3, #flag_OwnIRQ ; own the vector
EXITS EQ
[ SeparateIRQs
; release the IRQs
TST r3, #flag_Port1Present
BEQ %FT10
MOV r0, #Serial2_DevNo
ADDR r1, handle_irq1
MOV r2, wp
SWI XOS_ReleaseDeviceVector
STRVS r0, [sp]
PullEnv VS
BVS make_error
10
TST r3, #flag_Port2Present
BEQ %FT20
MOV r0, #Serial2_DevNo
ADDR r1, handle_irq2
MOV r2, wp
SWI XOS_ReleaseDeviceVector
STRVS r0, [sp]
PullEnv VS
BVS make_error
20
|
; release the IRQ
MOV r0, #Serial_DevNo
ADDR r1, handle_irq
......@@ -375,6 +485,10 @@ hardware_release ENTRY "r0-r4"
LDR r3, Flags
BIC r3, r3, #flag_OwnIRQ
STR r3, Flags
]
LDR r3, Flags
BIC r3, r3, #flag_OwnIRQ
STR r3, Flags
EXITS
......@@ -698,6 +812,53 @@ hardware_ctrl_lines ENTRY "r0-r1,r10"
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;
; call: hardware_set_ir_type
;
; in: r0 = required IR type
; r11 = port workspace
;
; out:
;
hardware_set_ir_type ENTRY "r1-r3,r10"
CMP r11, #0
EXITS EQ
LDR r10, BaseAddress
;Need to make sure we can do what we want to do. Superfically, just check for port2 rather than port1 for phoebe
MOV r1, #(IR_RxP_High + IR_TxP_Low + IR_Dpx_Full + IR_Typ_Std + IR_Loc_IRx) ;Std wired
CMP r0, #1
MOVEQ r1, #(IR_RxP_High + IR_TxP_Low + IR_Dpx_Full + IR_Typ_IrDA + IR_Loc_IRx) ;IrDA
CMP r0, #2
MOVEQ r1, #(IR_RxP_High + IR_TxP_Low + IR_Dpx_Full + IR_Typ_ASK + IR_Loc_IRx) ;ASK-IR
;Defaults to standard wired
STRB r0, IRStatus ; store in workspace
PHPSEI ;IRQs off
;Now program this value into the relevant config register
LDR r0, =cfg_base_addr
MOV r2, #&55
STR r2, [r0] ;Enter cfg mode
MOV r2, #&07
STR r2, [r0] ;Program logical device...
MOV r2, #&05
STR r2, [r0, #4] ; Device 5 (SP2)
MOV r2, #&F1
STR r2, [r0] ;Write to register F1
STR r1, [r0, #4] ; with the new IR status
MOV r2, #&aa
STR r2, [r0] ;Exit cfg mode
PLP ;IRQs back
EXITS
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
END
......
......@@ -58,6 +58,8 @@ ioctl ROUT
B ioctl_read_bauds ; 8 return number of bauds
B ioctl_read_baud ; 9 return baud rate
B ioctl_flush_buffer ; 10 flush buffer
B ioctl_read_ir ; 11 read IR capability
B ioctl_set_ir ; 12 set IR status
20
ADDR r0, ErrorBlock_Serial_BadIOCtlReasonCode
B make_error
......@@ -377,6 +379,41 @@ ioctl_flush_buffer ENTRY "r0-r3"
10
EXITS
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
ioctl_read_ir ENTRY "r0-r3"
LDR r4, [r3, #0] ; load flags
TST r4, #ioctl_read ; make sure the read bit is set
LDRNE r0, IRCapability
STRNE r0, [r3, #4] ; dump it in the datablock for return
EXITS
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
ioctl_set_ir ENTRY "r0-r3"
LDR r4, [r3, #0] ; load flags
LDR r0, [r3, #4] ; load data
; are we writing the IR type
TST r4, #ioctl_write
BEQ %10
BL hardware_set_ir_type
10
; do we wish to read current type?
TST r4, #ioctl_read
LDRNEB r0, IRStatus
STRNE r0, [r3, #4]
EXITS
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
END
; Copyright 1998 Acorn Computers Ltd
......
......@@ -6,28 +6,23 @@
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
;
; Copyright 1996 Acorn Network Computing
;
; This material is the confidential trade secret and proprietary
; information of Acorn Network Computing. It may not be reproduced,
; used, sold, or transferred to any third party without the prior
; written consent of Acorn Network Computing. All rights reserved.
;
;
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; call: handle_irq1
;
; call: handle_irq
;
; This interrupt routine will have to handle the arbatration between the two
; interrupt sources.
; This interrupt routine is called for port1
[ SeparateIRQs
handle_irq1 ENTRY "r10-r11"
LDR r11, Port1 ; try port 1
CMP r11, #0
EXITS EQ ;Bizarre. Quit.
LDR r10, BaseAddress ; get the environment
B irq_poll_loop
handle_irq2 ENTRY "r10-r11"
LDR r11, Port2 ; now try port 2
CMP r11, #0
EXITS EQ
LDR r10, BaseAddress ; get the environment
|
handle_irq ENTRY "r10-r11"
LDR r11, Port1 ; try port 1
CMP r11, #0
......@@ -43,10 +38,9 @@ handle_irq ENTRY "r10-r11"
CMP r11, #0
EXITS EQ
LDR r10, BaseAddress ; get the environment
]
irq_poll_loop
LDRB r1, UART_interrupt_ident ; r1 = interrupt identity
20
AND r1, r1, #IIR_IRQBits ; mask off the IRQ bits
TST r1, #IIR_no_interrupt ; if no more interrupt causes
BNE irq_exit ; leave the poll loop
......
......@@ -62,24 +62,8 @@ DeviceFSBlock # 4 ; address of devicefs registration block
DeviceHandle # 4 ; handle returned from DeviceFS_Register
InputStream # 4 ; devicefs stream handle
OutputStream # 4 ; devicefs stream handle
InputFSHandle # 4 ; file switch handle of input stream
OutputFSHandle # 4 ; file switch handle of output stream
InputBuffer # 4 ; buffer manager handle
OutputBuffer # 4 ; buffer manager handle
InputBufferPrivId # 4 ; buffer managers private buffer id
OutputBufferPrivId # 4 ; buffer managers private buffer id
InputBufferSize # 4 ; buffer size in bytes
OutputBufferSize # 4 ;
InputBufferThreshold # 4 ; buffer threshold point in bytes
OutputBufferThreshold # 4 ;
BaseAddress # 4 ; base address of register set
BaudRate # 4 ; ports programmed baud rate
DataFormat # 4 ; ports programmed data format
PortFlags # 4 ; port specific flags
ControlLines # 1
TxByteCount # 1
FIFOTrigger # 1
Dummy1 # 1
IRStatus # 1 ; IR status of this port
IRCapability # 4 ; IR capability of this port
[ counting
ByteCount # 4
ErrorCount # 4
......@@ -108,12 +92,19 @@ flag_Registered * 1:SHL:9 ; registered with devicefs
;
; bit definitions for ControlLines
;
ctrl_line_dtr * 1:SHL:0
ctrl_line_rts * 1:SHL:1
ctrl_line_cts * 1:SHL:2
ctrl_line_dsr * 1:SHL:3
ctrl_line_ri * 1:SHL:4
ctrl_line_dcd * 1:SHL:5
ctrl_line_dtr * 1:SHL:0
ctrl_line_rts * 1:SHL:1
ctrl_line_cts * 1:SHL:2
ctrl_line_dsr * 1:SHL:3
ctrl_line_ri * 1:SHL:4
ctrl_line_dcd * 1:SHL:5
;
; Definitions for CMOS backwards compatibility
;
CMOS_SerCompat * &0b
SerCompat_Mask * &80
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
......@@ -251,6 +242,7 @@ default_fifo_trigger * 4
base_address1 * C710 + &3f8*4
base_address2 * C710 + &2f8*4
cfg_base_addr * C710 + &3f0*4
xonchar * &11
xoffchar * &13
......@@ -298,13 +290,26 @@ init ENTRY "r0-r11"
]
; check to see if the devices are present
[ CMOS_BackCompat
MOV r0, #161
MOV r1, #CMOS_SerCompat
SWI XOS_Byte
TST r2, #SerCompat_Mask
LDR r0, Flags
BICNE r0, r0, #flag_Port1Present
BNE %FT10 ;SerCompat set, so back-compat: don't look for port1.
LDR r10, =base_address1
BL hardware_probe
CMP r10, #0
ORRNE r0, r0, #flag_Port1Present
LDR r10, =base_address2
|
LDR r0, Flags
LDR r10, =base_address1
BL hardware_probe
CMP r10, #0
ORRNE r0, r0, #flag_Port1Present
]
10 LDR r10, =base_address2
BL hardware_probe
CMP r10, #0
ORRNE r0, r0, #flag_Port2Present
......@@ -318,6 +323,8 @@ init ENTRY "r0-r11"
BL establish_device
STRVS r0, [sp]
STR r11, Port1
MOV r3, #Port1_IRCapability
STR r3, IRCapability
BVS %40
20
TST r0, #flag_Port2Present
......@@ -327,10 +334,12 @@ init ENTRY "r0-r11"
BL establish_device
STRVS r0, [sp]
STR r11, Port2
MOV r3, #Port2_IRCapability
STR r3, IRCapability
BVS %40
30
; claim the device vector
BL hardware_claim
; claim the device vector(s)
BL hardware_claim
EXIT
; free workspace up before exit
......
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