Commit 67cd615a authored by Neil Turton's avatar Neil Turton
Browse files

Import from SrcFiler

parents
| Copyright 1996 Acorn Computers Ltd
|
| Licensed under the Apache License, Version 2.0 (the "License");
| you may not use this file except in compliance with the License.
| You may obtain a copy of the License at
|
| http://www.apache.org/licenses/LICENSE-2.0
|
| Unless required by applicable law or agreed to in writing, software
| distributed under the License is distributed on an "AS IS" BASIS,
| WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
| See the License for the specific language governing permissions and
| limitations under the License.
|
Dir <Obey$Dir>
wimpslot -min 2000k
amu_machine all
| Copyright 1996 Acorn Computers Ltd
|
| Licensed under the Apache License, Version 2.0 (the "License");
| you may not use this file except in compliance with the License.
| You may obtain a copy of the License at
|
| http://www.apache.org/licenses/LICENSE-2.0
|
| Unless required by applicable law or agreed to in writing, software
| distributed under the License is distributed on an "AS IS" BASIS,
| WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
| See the License for the specific language governing permissions and
| limitations under the License.
|
Dir <Obey$Dir>
amu_machine clean
| Copyright 1996 Acorn Computers Ltd
|
| Licensed under the Apache License, Version 2.0 (the "License");
| you may not use this file except in compliance with the License.
| You may obtain a copy of the License at
|
| http://www.apache.org/licenses/LICENSE-2.0
|
| Unless required by applicable law or agreed to in writing, software
| distributed under the License is distributed on an "AS IS" BASIS,
| WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
| See the License for the specific language governing permissions and
| limitations under the License.
|
Dir <Obey$Dir>
amu_machine export
| Copyright 1996 Acorn Computers Ltd
|
| Licensed under the Apache License, Version 2.0 (the "License");
| you may not use this file except in compliance with the License.
| You may obtain a copy of the License at
|
| http://www.apache.org/licenses/LICENSE-2.0
|
| Unless required by applicable law or agreed to in writing, software
| distributed under the License is distributed on an "AS IS" BASIS,
| WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
| See the License for the specific language governing permissions and
| limitations under the License.
|
Dir <Obey$Dir>
amu_machine rom
s/** gitlab-language=armasm linguist-language=armasm linguist-detectable=true
**/c/** gitlab-language=c linguist-language=c linguist-detectable=true
h/** gitlab-language=c linguist-language=c linguist-detectable=true
**/h/** gitlab-language=c linguist-language=c linguist-detectable=true
Apache License
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Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
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# Copyright 1996 Acorn Computers Ltd
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
# Makefile for Serial
#
# ***********************************
# *** C h a n g e L i s t ***
# ***********************************
# Date Name Description
# ---- ---- -----------
# 29-Mar-96 Rich Buckley Created
# 09-Sep-96 Rich Buckley Added export
#
#
# Paths
#
EXP_HDR = <export$dir>
EXP_C_H = <Cexport$dir>.h
EXP_C_O = <Cexport$dir>.o
#
# Generic options:
#
MKDIR = cdir
AS = aasm
CP = copy
RM = remove
CCFLAGS = -c -depend !Depend -IC:
ASFLAGS = -depend !Depend -Stamp -quit -module -To $@ -From
CPFLAGS = ~cfr~v
#
# Program specific options:
#
COMPONENT = Serial
SOURCE = s.init
SOURCESA = s.standalone
TARGET = rm.${COMPONENT}
TARGETSA = ${COMPONENT}
EXPORTS = ${EXP_C_H}.${COMPONENT}
#
# Generic rules:
#
rom: ${TARGET}
@echo ${COMPONENT}: rom module built
export: ${EXPORTS}
@echo ${COMPONENT}: export complete
install_rom: ${TARGET}
${CP} ${TARGET} ${INSTDIR}.${COMPONENT} ${CPFLAGS}
@echo ${COMPONENT}: rom module installed
install: ${TARGET}
${CP} ${TARGET} ${INSTDIR}.${COMPONENT} ${CPFLAGS}
@echo ${COMPONENT}: module installed
clean:
${RM} ${TARGET}
${RM} ${TARGETSA}
@echo ${COMPONENT}: cleaned
resources:
${MKDIR} ${RESDIR}.${COMPONENT}
${CP} Resources.${LOCALE}.Messages ${RESDIR}.${COMPONENT}.Messages ${CPFLAGS}
@echo ${COMPONENT}: resource files copied
all: ${TARGETSA}
@echo ${COMPONENT}: standalone module built
${TARGET}: ${SOURCE}
${AS} ${ASFLAGS} ${SOURCE}
${TARGETSA}: ${SOURCESA}
${AS} ${ASFLAGS} ${SOURCESA}
${EXP_C_H}.${COMPONENT}: h.${COMPONENT}
${CP} h.${COMPONENT} $@ ${CPFLAGS}
# Dynamic dependencies:
; > Version
GBLA Version
GBLS VString
GBLS Date
Version SETA 016
VString SETS "0.16"
Date SETS "25 Oct 1996"
END
/* Copyright 1996 Acorn Computers Ltd
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/************************************************************************/
/* Copyright 1996 Acorn Network Computers */
/* */
/* This material is the confidential trade secret and proprietary */
/* information of Acorn Network Computers. It may not be reproduced, */
/* used sold, or transferred to any third party without the prior */
/* written consent of Acorn Network Computers. All rights reserved. */
/* */
/************************************************************************/
#ifndef __serial_h
#define __serial_h
/*
* filenames for serial streams without modification of baud rate, etc, ...
*/
#define SERIAL_STREAM_1 "devices:$.serial1"
#define SERIAL_STREAM_2 "devices:$.serial2"
/*
* access rights to be passed to serial_open_stream
*/
#define SERIAL_INPUT (0x4f)
#define SERIAL_OUTPUT (0xcf)
/*
* ioctl reason codes supported by serial driver
*/
#define IOCTL_BAUD (1)
#define IOCTL_FORMAT (2)
#define IOCTL_HANDSHAKE (3)
#define IOCTL_BUFFER_SIZE (4)
#define IOCTL_BUFFER_THRES (5)
#define IOCTL_CTRL_LINES (6)
#define IOCTL_FIFO_TRIG (7)
#define IOCTL_READ_BAUDS (8)
#define IOCTL_READ_BAUD (9)
/*
* struct to contain data forming an ioctl, used when calling serial_ioctl
*/
typedef struct {
unsigned int reason : 16; /* ioctl reason code */
unsigned int group : 8; /* ioctl group code */
unsigned int reserved : 6; /* should be zero */
unsigned int read : 1; /* read flag */
unsigned int write : 1; /* write flag */
unsigned int data; /* actual data */
} ioctl_t;
/*
* integer giving access to bit field values used in ioctl 6. should be used
* along the lines of :
*
* serial_ctrl.bits.dtr = 1
* pchIOCtlBlock->write = 1
* pchIOCtlBlock->data = serial_ctrl.data
*/
typedef union {
unsigned int data;
struct {
unsigned int dtr : 1; /* dtr line wr */
unsigned int rts : 1; /* rts line wr */
unsigned int resv1 : 14; /* reserved */
unsigned int cts : 1; /* cts line ro */
unsigned int dsr : 1; /* dsr line ro */
unsigned int ri : 1; /* ri line ro */
unsigned int dcd : 1; /* dcd line ro */
unsigned int fifo : 1; /* fifos enabled */
unsigned int resv2 : 11; /* reserved */
} bits;
} serial_ctrl_t;
#endif
#{DictTokens}
E1:Unknown reason code passed from DeviceFS
E2:Bad baud rate
E3:Bad data format
E4:Unknown ioctl reason code
E5:Bad ioctl parameter
E6:Serial stream(s) in use
*
!.gitignore
This diff is collapsed.
; Copyright 1996 Acorn Computers Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
;
; Copyright 1996 Acorn Network Computing
;
; This material is the confidential trade secret and proprietary
; information of Acorn Network Computing. It may not be reproduced,
; used, sold, or transferred to any third party without the prior
; written consent of Acorn Network Computing. All rights reserved.
;
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
^ &80ff00
AddError Serial_BadDeviceReasonCode,"E1"
AddError Serial_BadBaud, "E2"
AddError Serial_BadData, "E3"
AddError Serial_BadIOCtlReasonCode, "E4"
AddError Serial_BadIOCtlParameter, "E5"
AddError Serial_StreamInUse, "E6"
END
; Copyright 1996 Acorn Computers Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
;
; Copyright 1996 Acorn Network Computing
;
; This material is the confidential trade secret and proprietary
; information of Acorn Network Computing. It may not be reproduced,
; used, sold, or transferred to any third party without the prior
; written consent of Acorn Network Computing. All rights reserved.
;
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
^ 0, r10
UART_data_word # 4 ; 0 RX buffer and TX holding buffer DLAB = 0
UART_interrupt_enable # 4 ; 1 IER interrupt enable register
UART_interrupt_ident # 4 ; 2 IIR interrupt identification register
UART_line_control # 4 ; 3 LCR line control register
UART_modem_control # 4 ; 4 MCR modem control register
UART_line_status # 4 ; 5 LSR line status register
UART_modem_status # 4 ; 6 MSR modem status register
UART_scratch # 4 ; 7 SCR scratchpad register
^ 0, r10
UART_baud_divisor_LSB # 4 ; 0 DLL baud rate divisor latch LSB
UART_baud_divisor_MSB # 4 ; 1 DLM baud rate divisor latch MSB
UART_FIFO_control # 4 ; 2 FCR FIFO control register (on 550s only)
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;
; Bits in UART_interrupt_enable
IER_receive_available * 1 :SHL: 0 ; set bit to enable receive interrupts
IER_transmit_empty * 1 :SHL: 1 ; set bit to enable transmit interrupts
IER_line_status * 1 :SHL: 2 ; set bit to enable error interrupts (Overrun, Parity, Framing, Break)
IER_modem_status * 1 :SHL: 3 ; set bit to enable modem line change interrupts
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;
; Bits in UART_FIFO_control
FCR_enable * 1:SHL:0 ; enable TX and RX FIFOs
FCR_RX_reset * 1:SHL:1 ; reset RX FIFO
FCR_TX_reset * 1:SHL:2 ; reset TX FIFO
FCR_RX_trigger_1 * 2_00:SHL:6 ; RX interrupt trigger level
FCR_RX_trigger_4 * 2_01:SHL:6
FCR_RX_trigger_8 * 2_10:SHL:6
FCR_RX_trigger_14 * 2_11:SHL:6
FIFO_size * 16 ; 16 byte FIFO
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;
; Values in UART_interrupt_ident
IIR_no_interrupt * 1 ; bit 0 is clear when interrupt pending
IIR_line_status * 6 ; 0110 highest priority interrupt
IIR_RX_full * 4 ; 0100 second highest priority interrupt
IIR_char_timeout * 12 ; 1100 second highest priotity interrupt
IIR_TX_empty * 2 ; 0010 third hightst priotity interrupt
IIR_modem * 0 ; 0000 lowest priority interrupt
IIR_IRQBits * 15 ; 1111
IIR_FIFOs_enabled * 2_11:SHL:6 ; set to indicate FIFOs enabled
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;
; Bits in UART_line_control
LCR_start_bit * 1 :SHL: 2
LCR_parity_bit * 1 :SHL: 3
LCR_even_parity * 1 :SHL: 4
LCR_sticky_parity * 1 :SHL: 5
LCR_break_enable * 1 :SHL: 6 ; set to enable break signal
LCR_address_divisor * 1 :SHL: 7 ; set to access baud rate divisors
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;
; Bits in UART_modem_control
MCR_DTR_active * 1 :SHL: 0 ; set turn DTR active, clear disable DTR
MCR_RTS_active * 1 :SHL: 1 ; set turn RTS active, clear disable RTS
MCR_out_1 * 1 :SHL: 2 ; control OUT1 line
MCR_out_2 * 1 :SHL: 3 ; control OUT2 line
MCR_loopback * 1 :SHL: 4 ; turn on loopback facility
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;
; Bits in UART_line_status
LSR_data_ready * 1 :SHL: 0 ; 1 => character is in receive buffer
LSR_overrun * 1 :SHL: 1 ; 1 => overrun error
LSR_parity * 1 :SHL: 2 ; 1 => parity error
LSR_framing * 1 :SHL: 3 ; 1 => framing error
LSR_break * 1 :SHL: 4 ; 1 => break error
LSR_TX_empty * 1 :SHL: 5 ; 1 => tx buffer empty
LSR_TX_shift_empty * 1 :SHL: 6 ; 1 => tx buffer and shift reg empty
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;
; Bits in UART_modem_status
MSR_CTS_changed * 1 :SHL: 0 ; 1 => CTS has changed state
MSR_DSR_changed * 1 :SHL: 1 ; 1 => DSR has changed state
MSR_TERI_changed * 1 :SHL: 2 ; 1 => TERI has gone from 0 to 1
MSR_DCD_changed * 1 :SHL: 3 ; 1 => DCD has changed state
MSR_CTS_active * 1 :SHL: 4 ; CTS state
MSR_DSR_active * 1 :SHL: 5 ; DSR state
MSR_RI_active * 1 :SHL: 6 ; RI state
MSR_DCD_active * 1 :SHL: 7 ; DCD state
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;
; call: hardware_probe
;
; in : r10 hardware base address
;
; out : r10 address if port is present, 0 otherwise
;
; enable the UART loopback mode, assert DTR and wait for the looped back signal
; to assert DSR (with timeout).
hardware_probe ENTRY "r0-r5"
[ debug
; DREG r10, "probe : "
]
; do we have a base address
CMP r10, #0
EXITS EQ
; setup ready for scratch register
MOV r5, #&ff
; turn on loopback
MOV r4, #MCR_loopback
STRB r4, UART_modem_control
; assert DTR
ORR r4, r4, #MCR_DTR_active
STRB r4, UART_modem_control
; wait for DSR to be asserted
SWI XOS_ReadMonotonicTime
ADD r2, r0, #50 ; timeout period (cs)
10
LDRB r3, UART_modem_status
TST r3, #MSR_DSR_active
BNE %20
SWI XOS_ReadMonotonicTime
CMP r0, r2
BLE %10
B %30
20
; turn off DTR
BIC r4, r4, #MCR_DTR_active
STRB r4, UART_modem_control
; wait for DSR to be cleared
SWI XOS_ReadMonotonicTime
ADD r2, r0, #50 ; timeout period (cs)
STRB r5, UART_scratch
25
LDRB r3, UART_modem_status
TST r3, #MSR_DSR_active
BEQ %26
SWI XOS_ReadMonotonicTime
CMP r0, r2
BLE %25
B %30
26
; turn off loopback
BIC r4, r4, #MCR_loopback
STRB r4, UART_modem_control
EXITS
; show that we have not found anything
30
MOV r10, #0
EXITS
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;
; handle the command *SerialTest
;
; in : r0 port name
; r11 port workspace
;
hardware_test ENTRY "r1-r4,r10"
CMP r11, #0
EXITS EQ
; write the port name
SWI XOS_Write0
SWI XOS_NewLine
; do we have a base address
CMP r10, #0
EXITS EQ
; turn on loopback
MOV r4, #MCR_loopback
STRB r4, UART_modem_control
; turn off loopback
BIC r4, r4, #MCR_loopback
STRB r4, UART_modem_control
EXITS
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;
; call: hardware_initialise
;
; in : r11 port workspace
;
hardware_initialise ENTRY "r0-r1, r10"
[ debug
; DREG r11, "init : "
]
CMP r11, #0
EXITS EQ
LDR r10, BaseAddress
; enable FIFOs
MOV r1, #FCR_enable
STRB r1, UART_FIFO_control
; check them
LDRB r0, UART_interrupt_ident
TST r0, #IIR_FIFOs_enabled
BEQ %10 ; branch if not present
LDR r0, PortFlags
ORR r0, r0, #flag_FIFOsPresent
STR r0, PortFlags
; reset the FIFOs
ORR r1, r1, #FCR_RX_reset:OR:FCR_TX_reset
STRB r1, UART_FIFO_control
LDR r0, =default_fifo_trigger
BL hardware_set_fifo_trigger
10
LDR r0, =default_baud
BL hardware_set_baud
MOV r0, #default_data
BL hardware_set_data
MOV r0, #default_stop
BL hardware_stop_bit
MOV r0, #default_parity
BL hardware_parity
; enable all interrupts on port
MOV r0, #IER_receive_available:OR:IER_transmit_empty:OR:IER_line_status:OR:IER_modem_status
STRB r0, UART_interrupt_enable
MOV r0, #MCR_out_2
STRB r0, UART_modem_control
PHPSEI ; disable interrupts
LDRB r0, ControlLines
ORR r0, r0, #ctrl_line_dtr:OR:ctrl_line_rts
STRB r0, ControlLines
PLP ; enable interrupts
BL hardware_ctrl_lines
EXITS
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;
; call: hardware_remove
;
; in : r11 port workspace
;
hardware_remove ENTRY "r0,r10"
CMP r11, #0
EXITS EQ
LDR r10, BaseAddress
; drop rts and dtr when quitting
PHPSEI ; disable interrupts
LDRB r0, ControlLines
BIC r0, r0, #ctrl_line_dtr:OR:ctrl_line_rts
STRB r0, ControlLines
PLP ; enable interrupts
BL hardware_ctrl_lines
; disable port interrupts
MOV r0, #0 ; disable all interrupts
STRB r0, UART_interrupt_enable
EXITS
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;
; call: hardware_claim
;
hardware_claim ENTRY "r0-r4"
[ debug
; DLINE "claim"
]
; claim device vector
LDR r3, Flags ; own the vector ?
TST r3, #flag_OwnIRQ
BNE %10
MOV r0, #Serial_DevNo
ADDR r1, handle_irq
MOV r2, wp
SWI XOS_ClaimDeviceVector
STRVS r0, [sp]
PullEnv VS
BVS make_error
LDR r3, Flags ; we now the vector
ORR r3, r3, #flag_OwnIRQ
STR r3, Flags
10
; podule IRQ bit needs to be set in IOC
MOV lr, pc ; disable IRQs
ORR r1, lr, #I_bit
TEQP r1, #0
NOP
LDR r1, =IOC ; look at IOC
LDRB r0, [r1, #IOCIRQMSKB]
ORR r0, r0, #serial_bit
STRB r0, [r1, #IOCIRQMSKB]
TEQP lr, #0 ; restore IRQs
NOP
[ debug
; DLINE "claim complete"
]
EXITS
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;
; call: hardware_release
;
hardware_release ENTRY "r0-r4"
LDR r3, Flags
TST r3, #flag_OwnIRQ ; own the vector
EXITS EQ
; release the IRQ
MOV r0, #Serial_DevNo
ADDR r1, handle_irq
MOV r2, wp
SWI XOS_ReleaseDeviceVector
STRVS r0, [sp]
PullEnv VS
BVS make_error
LDR r3, Flags
BIC r3, r3, #flag_OwnIRQ
STR r3, Flags
EXITS
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;
; call: hardware_set_fifo_trigger
;
; in: r0 = required trigger value
; r11 = port workspace
;
; out: r0 = actual value
;
hardware_set_fifo_trigger ENTRY "r1,r10"
CMP r11, #0
EXITS EQ
; range check the fifo trigger values
CMP r0, #1
CMPNE r0, #4
CMPNE r0, #8
CMPNE r0, #14
LDRNEB r0, FIFOTrigger
EXITS NE
; set up the port
STRB r0, FIFOTrigger
LDR r10, BaseAddress
PHPSEI ; disable interrupts
MOV r1, #0
CMP r0, #1
ORREQ r1, r1, #FCR_RX_trigger_1
CMP r0, #4
ORREQ r1, r1, #FCR_RX_trigger_4
CMP r0, #8
ORREQ r1, r1, #FCR_RX_trigger_8
CMP r0, #14
ORREQ r1, r1, #FCR_RX_trigger_14
; ensure fifos are enabled and reset
LDR r0, PortFlags
TST r0, #flag_FIFOsPresent
ORRNE r1, r1, #FCR_enable:OR:FCR_RX_reset
STRB r1, UART_FIFO_control
PLP ; enable interrupts
EXITS
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;
; call: hardware_set_baud
;
; in: r0 = required baud rate
; r11 = port workspace
;
; out:
;
hardware_set_baud ENTRY "r1-r3,r10"
CMP r11, #0
EXITS EQ
LDR r10, BaseAddress
ADR r2, baud_table
ADR r3, baud_table_end
SUB r3, r3, #8
10
ADD r2, r2, #8 ; move to next entry
LDR r1, [r2, #0]
CMP r0, r1 ; does it match
BEQ %20
CMP r2, r3 ; are we at the end ?
BLT %10
; make an error
ADR r0, ErrorBlock_Serial_BadBaud
PullEnv
B make_error
20
; now program the UART to use this baud rate divisor
STR r0, BaudRate ; store in workspace
LDR r1, [r2, #4] ; load baud rate divisor
PHPSEI ; disable interrupts
; set DRAB
LDRB r2, UART_line_control
ORR r2, r2, #LCR_address_divisor
STRB r2, UART_line_control
STRB r1, UART_baud_divisor_LSB ; store lower byte
MOV r1, r1, LSR #8 ; shift down one byte
STRB r1, UART_baud_divisor_MSB ; write upper byte
; clear DRAB
BIC r2, r2, #LCR_address_divisor
STRB r2, UART_line_control
PLP ; enable interrupts
EXITS
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
MakeErrorBlock Serial_BadBaud
baud_table ; frequency, divisor value
DCD 50, 2304
DCD 75, 1536
DCD 110, 1047
DCD 150, 768
DCD 300, 384
DCD 600, 192
DCD 1200, 96
DCD 1800, 64
DCD 2400, 48
DCD 3600, 32
DCD 4800, 24
DCD 7200, 16
DCD 9600, 12
DCD 19200, 6
DCD 38400, 3
DCD 57600, 2
DCD 115200, 1
baud_table_end
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;
; call: hardware_set_data
;
; in: r0 = data size
; r10 = port workspace
; out:
;
hardware_set_data ENTRY "r1-r2,r10"
CMP r11, #0
EXITS EQ
LDR r10, BaseAddress
CMP r0, #5 ; is it less than 5
BLT %5
CMP r0, #8 ; or greater than 8
BLE %10
; make an error
5
ADR r0, ErrorBlock_Serial_BadData
PullEnv
B make_error
10
LDR r1, DataFormat ; stash results away
BIC r1, r1, #&ff
ORR r1, r1, r0
STR r1, DataFormat
SUB r1, r0, #5 ; 5 maps to 0, 6 to 1, etc
PHPSEI ; disable interrupts
LDRB r2, UART_line_control
BIC r2, r2, #3
ORR r2, r2, r1
STRB r2, UART_line_control
PLP ; enable interrupts
EXITS
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
MakeErrorBlock Serial_BadData
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;
; call: hardware_stop_bit
;
; in: r0 = number of start/stop bits
; r11 = port workspace
; out:
;
hardware_stop_bit ENTRY "r1-r2,r10"
CMP r11, #0
EXITS EQ
LDR r10, BaseAddress
PHPSEI ; disable interrupts
LDRB r1, UART_line_control
CMP r0, #2 ; 2 stop bits ?
MOVNE r0, #1 ; otherwise 1
ORREQ r1, r1, #LCR_start_bit ; 2 stop bits
BICNE r1, r1, #LCR_start_bit ; 1 stop bit
STRB r1, UART_line_control
PLP ; enable interrupts
; store away now as we may have modded it above
LDR r1, DataFormat
MOV r2, r0, LSL #8
BIC r1, r1, #&ff00
ORR r1, r1, r2
STR r1, DataFormat
EXITS
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;
; call: hardware_parity
;
; in: r0 = parity : none=0, even=1, odd=2
; r11 = port workspace
; out:
;
hardware_parity ENTRY "r1-r2,r10"
CMP r11, #0
EXITS EQ
LDR r10, BaseAddress
; normalise the value
CMP r0, #2
MOVGT r0, #2
CMP r0, #0
MOVLT r0, #0
LDR r1, DataFormat ; stash results away
MOV r2, r0, LSL #16
BIC r1, r1, #&ff0000
ORR r1, r1, r2
STR r1, DataFormat
PHPSEI ; disable interrupts
LDRB r1, UART_line_control
CMP r0, #0 ; no parity ?
BICEQ r1, r1, #LCR_parity_bit
ORRNE r1, r1, #LCR_parity_bit
CMP r0, #1 ; even parity ?
ORREQ r1, r1, #LCR_even_parity
BICNE r1, r1, #LCR_even_parity
STRB r1, UART_line_control
PLP ; enable interrupts
EXITS
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;
; call: hardware_ctrl_line
;
; in: r11 = port workspace
; out:
;
; check the dtr and rts bits in the control line flags byte and set hardware
; accordingly.
;
hardware_ctrl_lines ENTRY "r0-r1,r10"
CMP r11, #0
EXITS EQ
LDR r10, BaseAddress
; sort out the read/writables in the modem control register
PHPSEI ; disable interrupts
LDRB r0, ControlLines
LDRB r1, UART_modem_control
TST r0, #ctrl_line_dtr
ORRNE r1, r1, #MCR_DTR_active
BICEQ r1, r1, #MCR_DTR_active
TST r0, #ctrl_line_rts
ORRNE r1, r1, #MCR_RTS_active
BICEQ r1, r1, #MCR_RTS_active
STRB r1, UART_modem_control
PLP ; enable interrupts
; now the read onlys in the modem status register
LDRB r1, UART_modem_status
TST r1, #MSR_CTS_active ; check cts
ORRNE r0, r0, #ctrl_line_cts
BICEQ r0, r0, #ctrl_line_cts
TST r1, #MSR_DSR_active ; check dsr
ORRNE r0, r0, #ctrl_line_dsr
BICEQ r0, r0, #ctrl_line_dsr
TST r1, #MSR_RI_active ; check ri
ORRNE r0, r0, #ctrl_line_ri
BICEQ r0, r0, #ctrl_line_ri
TST r1, #MSR_DCD_active ; check dcd
ORRNE r0, r0, #ctrl_line_dcd
BICEQ r0, r0, #ctrl_line_dcd
STRB r0, ControlLines
PLP ; enable interrupts
EXITS
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
END
; Copyright 1996 Acorn Computers Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
;
; Copyright 1996 Acorn Network Computing
;
; This material is the confidential trade secret and proprietary
; information of Acorn Network Computing. It may not be reproduced,
; used, sold, or transferred to any third party without the prior
; written consent of Acorn Network Computing. All rights reserved.
;
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;
; Author : R.W.Buckley
; Date : 22-Apr-96
;
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;
; Modification History
;
; Ver Date Who Description
; 0.02 21-May-96 RWB Slight tweeks to ioctls
; 0.03 22-May-96 RWB Sorted out redundant error messages
; 0.04 22-May-96 RWB Default to 9600 baud
; Register for threshold upcalls on in/out streams
; Check stream handles on threshold halt/resume
; 0.05 28-May-96 RWB Register for device upcalls from DeviceFS
; Re-assert handshake control lines on new stream
; 0.06 31-May-96 SMC Fixed module help string for brain-dead Kernel
; 0.07 03-Jun-96 RWB Generate serial event on serial error
; 0.08 06-Jun-96 RWB Corrected some error reporting, changed probe
; slightly.
; 0.09 10-Jun-96 RWB Fixed bug that occured when errors are found
; during module initialisation.
; 0.10 14-Jun-96 RWB Added file handle to Error event call
; 0.11 01-Jul-96 RWB Changed date format in version file
; 0.12 23-Jul-96 SC,RWB Moved release device vector in finalisation code
; 0.13 02-Aug-96 RWB Discovered the messages file was being put in
; the wrong place.
; Added check for open streams on module finalis.
; 0.14 05-Aug-96 RWB Use allocated error block number for errors.
; 0.15 06-Aug-96 RWB Only register with devicefs if not alrealy
; registered. This was a problem when service call
; DeviceFSStarting goes round.
; Changed the value for an invalid internal buffer
; handle.
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;
; Global header files
;
GET Hdr:ListOpts
OPT OptNoList
GET Hdr:NdrDebug ; definition of true
GET Hdr:Macros ; system wide macro definitions
GET Hdr:System ; swis and hardware declarations
GET Hdr:Machine.<Machine> ; for machine-specific flags
GET Hdr:ModHand ; Module handler reason codes
GET Hdr:HighFSI ; high level filing system
GET Hdr:DevNos ; device no for new IRQ handling
GET Hdr:Services ; service call info
GET Hdr:Symbols ; constants TRUE, FALSE, VFlag
GET Hdr:MsgTrans ; MessageTrans constants
GET Hdr:Proc ; ENTRY and EXIT macros
GET Hdr:Buffer
GET Hdr:ResourceFS
GET Hdr:DeviceFS ; reason code definitions
GET Hdr:IO.IOEB
GET Hdr:RS423 ; need serial error flags
$GetIO ; I need IOMD declarations etc
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;
; Global variables
;
GBLL debug
GBLL border_handshake
GBLL counting
debug SETL false ; to include debug macros
border_handshake SETL false ; to flash border when handshaking
counting SETL false ; to count stuff
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;
; Debug header files
;
GBLS conditional_get
[ debug
conditional_get SETS "GET Hdr:Debug" ; Standard debug macros
|
conditional_get SETS ""
]
$conditional_get
[ :LNOT: :DEF: standalonemessages
GBLL standalonemessages
standalonemessages SETL {FALSE}
]
LEADR Module_LoadAddr
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;
; User header files
;
OPT OptList
GET Version
GET s.errors ; error handling stuff
GET s.macros ; some useful macros
GET s.main ; module interfaces
GET s.hardware ; hardware detection and irq stuff
GET s.interrupts ; handle irqs
GET s.devicecall ; handle devicefs stuff
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;
; Debug routine code
;
[ debug
InsertDebugRoutines ; ensure this is after module header !
]
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
END
; Copyright 1996 Acorn Computers Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
;
; Copyright 1996 Acorn Network Computing
;
; This material is the confidential trade secret and proprietary
; information of Acorn Network Computing. It may not be reproduced,
; used, sold, or transferred to any third party without the prior
; written consent of Acorn Network Computing. All rights reserved.
;
;
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;
; call: handle_irq
;
; This interrupt routine will have to handle the arbatration between the two
; interrupt sources.
handle_irq ENTRY "r10-r11"
LDR r11, Port1 ; try port 1
CMP r11, #0
BEQ %10
LDR r10, BaseAddress ; get the environment
LDRB r1, UART_interrupt_ident ; clears tx empty ints
TST r1, #IIR_no_interrupt ; any interrupts ?
BEQ %20
10
LDR r11, Port2 ; now try port 2
CMP r11, #0
EXITS EQ
LDR r10, BaseAddress ; get the environment
irq_poll_loop
LDRB r1, UART_interrupt_ident ; r1 = interrupt identity
20
AND r1, r1, #IIR_IRQBits ; mask off the IRQ bits
TST r1, #IIR_no_interrupt ; if no more interrupt causes
BNE irq_exit ; leave the poll loop
[ counting
LDR r0, InterruptCount
ADD r0, r0, #1
STR r0, InterruptCount
]
TEQ r1, #IIR_line_status
BEQ handle_line_status
TEQ r1, #IIR_RX_full
BEQ handle_rx_full
TEQ r1, #IIR_char_timeout
BEQ handle_rx_full
TEQ r1, #IIR_TX_empty
BEQ handle_tx_empty
; if none of the above, it must be...
;
; one of the modem control lines has changed, update our soft copy.
;
handle_modem_status
LDRB r0, UART_modem_status ; clear interrupt
; we need to update the ControlLines information since something has changed
LDRB r3, ControlLines
TST r0, #MSR_CTS_active
ORRNE r3, r3, #ctrl_line_cts
BLNE wakeup_tx ; need to start tx
BICEQ r3, r3, #ctrl_line_cts
TST r0, #MSR_DSR_active
ORRNE r3, r3, #ctrl_line_dsr
BLNE wakeup_tx ; need to start tx
BICEQ r3, r3, #ctrl_line_dsr
TST r0, #MSR_RI_active
ORRNE r3, r3, #ctrl_line_ri
BICEQ r3, r3, #ctrl_line_ri
TST r0, #MSR_DCD_active
ORRNE r3, r3, #ctrl_line_dcd
BICEQ r3, r3, #ctrl_line_dcd
STRB r3, ControlLines
MOV r1, #0 ; nothing yet
TST r0, #MSR_DSR_changed
ORRNE r1, r1, #SerialError_DSR
TST r0, #MSR_DCD_changed
ORRNE r1, r1, #SerialError_DCD
CMP r1, #0
BLNE give_event
B irq_poll_loop
; handle line status interrupt
handle_line_status
[ counting
LDR r0, ErrorCount
ADD r0, r0, #1
STR r0, ErrorCount
]
LDRB r0, UART_line_status ; clear interrupt
LDRB r1, UART_data_word ; clear byte
MOV r1, #0
TST r0, #LSR_overrun
ORRNE r1, r1, #SerialError_Overrun
TST r0, #LSR_parity
ORRNE r1, r1, #SerialError_Parity
TST r0, #LSR_framing
ORRNE r1, r1, #SerialError_Framing
CMP r1, #0
BLNE give_event
[ counting
TST r0, #LSR_overrun
LDRNE r1, OverrunCount
ADDNE r1, r1, #1
STRNE r1, OverrunCount
TST r0, #LSR_parity
LDRNE r1, ParityCount
ADDNE r1, r1, #1
STRNE r1, ParityCount
TST r0, #LSR_framing
LDRNE r1, FramingCount
ADDNE r1, r1, #1
STRNE r1, FramingCount
]
B irq_poll_loop
; handle receive interrupt (even in FIFO mode we must go round poll loop for
; each char in case of errors)
handle_rx_full
[ counting
LDR r2, ByteCount
ADD r2, r2, #1
STR r2, ByteCount
]
LDRB r2, UART_data_word ; get byte received into r0
; deal with xon/xoff handshaking
LDR r3, PortFlags ; update flags
TST r3, #flag_UseXon
BEQ %25
; handle it then
CMP r2, #xoffchar ; do we have an xoff
CMPNE r2, #xonchar ; or an xon
BNE %25 ; no, then skip
CMP r2, #xoffchar
ORREQ r3, r3, #flag_TxXoffed
BICNE r3, r3, #flag_TxXoffed
BLNE wakeup_tx ; wake the device up
STR r3, PortFlags
B irq_poll_loop ; and loop again
25
LDR r1, InputBufferPrivId
CMP r1, #-1
BEQ irq_poll_loop
MOV r0, #BufferReason_InsertByte
CallBuffMan
[ counting
LDRCS r0, BufferOverrun
ADDCS r0, r0, #1
STRCS r0, BufferOverrun
]
B irq_poll_loop
; handle transmit interrupt (in FIFO mode we can send FIFO_Size bytes)
handle_tx_empty
LDR r3, PortFlags
TST r3, #flag_FIFOsPresent
MOVEQ r0, #0 ; can only send one byte
MOVNE r0, #FIFO_size-1
STRB r0, TxByteCount
BL irq_tx_byte
B irq_poll_loop
irq_tx_byte
; are we using handshaking
TST r3, #flag_UseRTS:OR:flag_UseXon:OR:flag_UseDTR
BEQ %60
; is it xon/xoff
TST r3, #flag_UseXon
BEQ %55
TST r3, #flag_TxXon ; transmit xon
MOVNE r2, #xonchar ; setup character
BICNE r3, r3, #flag_TxXon ; clear bit
STRNE r3, PortFlags
BNE %65 ; jump to tx character
TST r3, #flag_TxXoff ; transmit xoff
MOVNE r2, #xoffchar ; setup character
BICNE r3, r3, #flag_TxXoff ; clear bit
STRNE r3, PortFlags
BNE %65 ; jump to tx character
; have I been xoffed
TST r3, #flag_TxXoffed
BNE %70 ; goto sleep
B %60 ; continue
55
; so must be rts or dtr
LDRB r2, ControlLines
TST r3, #flag_UseRTS
BEQ %56 ; skip
TST r2, #ctrl_line_cts ; not free to send
BEQ %70 ; goto sleep
56
TST r3, #flag_UseDTR
BEQ %60 ; skip
TST r2, #ctrl_line_dtr ; not free to send
BEQ %70 ; goto sleep
60
; need to pull some data from the buffer
LDR r1, OutputBufferPrivId
CMP r1, #-1
BEQ %FT70 ; sleep and disable TXI
MOV r0, #BufferReason_RemoveByte
CallBuffMan
BCS %FT70
65
STRB r2, UART_data_word
MOV pc, lr
70
ORR r3, r3, #flag_TxDormant ; go to sleep
STR r3, PortFlags
80
LDRB r1, UART_interrupt_enable
BIC r1, r1, #IER_transmit_empty
STRB r1, UART_interrupt_enable
MOV r1, #0 ; no more bytes
STRB r1, TxByteCount
MOV pc, lr
; no more interrupt causes at present so see if we have any more bytes to stuff
; in the FIFO (if there is one) this is done here so that filling any FIFO
; takes a lower priority than servicing other interrupts
irq_exit
LDRB r1, UART_line_status
TST r1, #LSR_data_ready
BNE handle_rx_full
LDRB r1, TxByteCount
SUBS r1, r1, #1
EXITS CC ; no more bytes to be sent
STRB r1, TxByteCount ; otherwise, update count
LDR r3, PortFlags ; and send another byte
BL irq_tx_byte
B irq_poll_loop ; check for more interrupts
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;
; call: give_event
;
; in: r1 = DCD, DSR, PE, OV and FE bits where you want them
; r11 = port workspace
;
; This code generates an event about a serial error ie framing error, overrun,
; parity error or DCD high
;
give_event ENTRY "r0-r3"
LDR r2, InputFSHandle ; get file handle
MOV lr, pc
AND lr, lr, #3
EOR r3, lr, #SVC_mode ; switch into SVC mode
TEQP r3, pc
NOP
Push "lr"
MOV r0, #Event_RS423Error
SWI XOS_GenerateEvent ; and then generate event
Pull "lr" ; preserve SVC LR
TEQP r3, pc ; restore original mode
NOP
EXITS
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
END
; Copyright 1996 Acorn Computers Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
;
; Copyright 1996 Acorn Network Computing
;
; This material is the confidential trade secret and proprietary
; information of Acorn Network Computing. It may not be reproduced,
; used, sold, or transferred to any third party without the prior
; written consent of Acorn Network Computing. All rights reserved.
;
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;
; Sets border colour
;
colour_off * &40000000
colour_red * &400000ff
colour_blue * &40ff0000
colour_green * &4000ff00
MACRO
$label SetColour $colour
$label
[ debug
Push "r0-r1"
MOV r0, #&3500000
LDR r1, =colour_$colour
STR r1, [r0]
Pull "r0-r1"
]
MEND
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;
; Calls buffer manager service routine
;
MACRO
$label CallBuffMan $cc
$label Push "r12,lr" ; save our workspace ptr
ADR$cc r12, BuffManWkSpace ; buffman workspace and entry
MOV$cc lr, pc ; return address
ASSERT BuffManService = BuffManWkSpace+4
LDM$cc.IA r12, {r12, pc} ; load buffman wkspace and entry
Pull "r12,lr" ; restore our workspace ptr
MEND
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
END
This diff is collapsed.
; Copyright 1996 Acorn Computers Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
;
; Copyright 1996 Acorn Network Computing
;
; This material is the confidential trade secret and proprietary
; information of Acorn Network Computing. It may not be reproduced,
; used, sold, or transferred to any third party without the prior
; written consent of Acorn Network Computing. All rights reserved.
;
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;
; Makes version of module with messages bound in
GBLL standalonemessages
standalonemessages SETL {TRUE}
LNK s.init
| Copyright 1996 Acorn Computers Ltd
|
| Licensed under the Apache License, Version 2.0 (the "License");
| you may not use this file except in compliance with the License.
| You may obtain a copy of the License at
|
| http://www.apache.org/licenses/LICENSE-2.0
|
| Unless required by applicable law or agreed to in writing, software
| distributed under the License is distributed on an "AS IS" BASIS,
| WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
| See the License for the specific language governing permissions and
| limitations under the License.
|
Dir <Obey$Dir>
amu_machine all
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