Clarify status flags docs

Confusing wording with double negatives reworded to read more easily.
Retagged as DMA-0_20.

Doc/HAL_DMAAPI

@@ -221,12 +221,28 @@ IRQClear
 
 Status
   Returns status bits for the current channel:
-  bit 0 set => there are no transfers programmed but not yet started
-               (for a double-buffered controller, this is set when interrupting
-               or for a single-buffered controller, this is always set)
-  bit 1 set => channel has not yet been used, or is in over/underrun state
-               (set on every interrupt for single-buffered DMA controllers)
-  bit 2 set => channel entered over/underrun state before last call to
+  bit 0 clr => there are transfers programmed that are waiting to begin
+        set => there are no transfers programmed that are waiting to begin
+               A double-buffered controller may exist as
+               II: Both buffers are unprogrammed and idle, both transfers
+                   have completed and an over/underrun condition exists
+               AP/PA: One buffer is active doing a transfer, the other buffer
+                   is programmed ready and waiting to begin
+               AI/IA: One buffer is active doing a transfer, the other buffer
+                   is unprogrammed and idle
+               AA: Both buffers are active, this is of course impossible
+               the II/AI/IA conditions set this flag bit since they are
+               the only ones where there are no pending programmed transfers.
+               For a single-buffered controller, any programmed channel must
+               immediately transition to active. Since there is only one buffer
+               it can never be in state 'P', so this flag bit is always set.
+  bit 1 clr => no over/underrun condition exists
+        set => channel has not yet been used, or is in over/underrun state
+               Set when both buffers are idle for double-buffered DMA
+               controllers.
+               Set on every interrupt for single-buffered DMA controllers.
+  bit 2 clr => channel does not need reprogramming via SetCurrentTransfer
+        set => channel entered over/underrun state before last call to
                SetNextTransfer had effect (devices may determine this by
                monitoring any handle they may have on the physical double
                buffers, or failing this by calculating the final value of the