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Commit 77cdce3b authored by Ben Avison's avatar Ben Avison
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One new feature, required by ADFS, and lots of silly bugfixes. 

Detail:
  * Flag bit 3 passed to DMA_QueueTransfer indicates that the DMA Manager
    shouldn't update the scatter list itself, even when a circular transfer
    is not specifier
  * When using a bounce buffer, the source/destination isn't marked
    uncacheable any more
  * r2 was being corrupted by the call to the device Reset entry
  * Flags passed to device SetOptions entry were always 0, which meant that
    you could never write to any device
  * Test for whether to write to the bounce buffer was wrong in two ways
  * Updating the scatter list was wrong if the amount to update by was
    larger than the first entry (ie after a bounce buffer had been
    completed) - the whole difference was applied to the first entry
Admin:
  Tested in use with ADFS.

Version 0.15, 4.4.2.5. Tagged as 'DMA-0_15-4_4_2_5'
parent 24b8fc82
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Showing with 50 additions and 19 deletions
Doc/HAL_DMAAPI
View file @ 77cdce3b
......@@ -173,7 +173,7 @@ SetOptions
bit 0 set => memory to device, clear => device to memory
(ignored for any memory-to-memory channel)
bits 1-5 => transfer unit width, typically 1, 2 or 4 bytes
(16 bytes is used for IOMD)
(16 bytes can also be used for IOMD)
bits 6-8 => cycle speed, on an arbitrary scale from 0-7
(0-3 maps to A-D cycles on IOMD)
bits 9-12 => minimum delay required after a DMA transfer before the same
......
VersionASM
View file @ 77cdce3b
......@@ -13,11 +13,11 @@
GBLS Module_ComponentPath
Module_MajorVersion SETS "0.15"
Module_Version SETA 15
Module_MinorVersion SETS "4.4.2.4"
Module_Date SETS "25 Oct 2002"
Module_ApplicationDate SETS "25-Oct-02"
Module_MinorVersion SETS "4.4.2.5"
Module_Date SETS "22 Nov 2002"
Module_ApplicationDate SETS "22-Nov-02"
Module_ComponentName SETS "DMA"
Module_ComponentPath SETS "RiscOS/Sources/HWSupport/DMA"
Module_FullVersion SETS "0.15 (4.4.2.4)"
Module_HelpVersion SETS "0.15 (25 Oct 2002) 4.4.2.4"
Module_FullVersion SETS "0.15 (4.4.2.5)"
Module_HelpVersion SETS "0.15 (22 Nov 2002) 4.4.2.5"
END
VersionNum
View file @ 77cdce3b
......@@ -5,19 +5,19 @@
*
*/
#define Module_MajorVersion_CMHG 0.15
#define Module_MinorVersion_CMHG 4.4.2.4
#define Module_Date_CMHG 25 Oct 2002
#define Module_MinorVersion_CMHG 4.4.2.5
#define Module_Date_CMHG 22 Nov 2002
#define Module_MajorVersion "0.15"
#define Module_Version 15
#define Module_MinorVersion "4.4.2.4"
#define Module_Date "25 Oct 2002"
#define Module_MinorVersion "4.4.2.5"
#define Module_Date "22 Nov 2002"
#define Module_ApplicationDate "25-Oct-02"
#define Module_ApplicationDate "22-Nov-02"
#define Module_ComponentName "DMA"
#define Module_ComponentPath "RiscOS/Sources/HWSupport/DMA"
#define Module_FullVersion "0.15 (4.4.2.4)"
#define Module_HelpVersion "0.15 (25 Oct 2002) 4.4.2.4"
#define Module_FullVersion "0.15 (4.4.2.5)"
#define Module_HelpVersion "0.15 (22 Nov 2002) 4.4.2.5"
#define Module_LibraryVersionInfo "0:15"
s/DMA
View file @ 77cdce3b
......@@ -626,7 +626,8 @@ DMACreatePageTable
;-----------------------------------------------------------------------------
; DMAConvertPageTable
; In: r10 ->DMA request block
; In: r9 ->DMA queue
; r10 ->DMA request block
;
; Fill in physical addresses in page table and mark pages as uncacheable
; if reading to memory.
......@@ -644,6 +645,11 @@ DMAConvertPageTable
TEQ r1, #0 ; If no page table yet then
BLEQ DMACreatePageTable ; create one.
EXIT VS
[ HAL
LDR lr, [r9, #dmaq_BounceBuff + ptab_Logical]
TEQ lr, #0 ; If using a bounce buffer,
EXIT NE ; don't mark source/destination as uncacheable!!
]
LDR r2, [r10, #dmar_PageCount]
LDR r3, [r10, #dmar_Flags]
[ WriteBackCache
......@@ -798,6 +804,7 @@ DMAForceActivate
]
STR lr, [r9, #dmaq_LastBuff]
LDR r2, [r10, #dmar_Flags]
TST r2, #dmarf_BeenActive ; If resuming a suspended request then
BNE %FT10 ; don't initialise any more.
......@@ -830,7 +837,7 @@ DMAForceActivate
ASSERT dmarf_Direction = 1
LDREQ r2, [r8, #lcb_PeripheralRead]
LDRNE r2, [r8, #lcb_PeripheralWrite]
AND r1, r1, r3, LSL #1 ; note lcbf_Registered is shifted off end, and lcbf_Blocked will be clear
ORR r1, r1, r3, LSL #1 ; note lcbf_Registered is shifted off end, and lcbf_Blocked will be clear
MOV r0, r5
CallHAL DMA_SetOptions
LDR r12, [sp, #28+Proc_RegOffset] ; Restore our workspace pointer.
......@@ -866,6 +873,9 @@ DMAForceActivate
]
LDR r1, UnsafePageTable
TEQ r1, #0 ; If no unsafe page table then
[ HAL
LDREQ r1, [r10, #dmar_Flags]
]
BEQ %FT30 ; start the transfer.
MOV r2, r1 ; Otherwise, scan the page table for unsafe pages.
......@@ -879,7 +889,7 @@ DMAForceActivate
]
30
[ HAL
TST lr, #dmarf_Direction ; If a write operation
TST r1, #dmarf_Direction ; If a write operation
LDRNE lr, [r9, #dmaq_BounceBuff + ptab_Logical]
TEQNE lr, #0 ; and there's a bounce buffer for this physical channel
BLNE CopyToBounceBuffer ; then we need to fill in the bounce buffer.
......@@ -2318,7 +2328,11 @@ update
; r8 = DMA request flags
; r10 = ptr to DMA request block
;
[ HAL
Entry "r0-r3"
|
Entry "r0-r2"
]
LDR r2, [r0, #buff_Len] ; Get amount done.
Debug int," update by",r2
......@@ -2335,7 +2349,7 @@ update
ADDNE lr, lr, r2
STRNE lr, [r10, #dmar_Gap]
TST r8, #dmarf_Circular ; If circular then
TST r8, #dmarf_Circular :OR: dmarf_DontUpdate ; If circular, or so requested, then
EXIT NE ; don't update scatter list.
LDR lr, [r10, #dmar_ScatterList]
......@@ -2351,12 +2365,26 @@ update
STREQ lr, [r10, #dmar_ScatterList]
BEQ %BT10
[ HAL
CMP r2, r1
MOVHI r3, r1
MOVLS r3, r2 ; r3 = amount to update this scatter entry by
ADD r0, r0, r3
SUB r1, r1, r3
STMIA lr, {r0,r1}
EXIT LS ; Do we need to update the next scatter entry too?
SUB r2, r2, r3
ADD lr, lr, #8
STR lr, [r10, #dmar_ScatterList]
B %BT10
|
ADD r0, r0, r2 ; Update addr and len by amount done.
SUB r1, r1, r2
STMIA lr, {r0,r1}
DebugTab r2,lr,#&12,r0,r1
EXIT
]
program ROUT
......
s/Front
View file @ 77cdce3b
......@@ -133,7 +133,8 @@ DMARSize * :INDEX:@
dmarf_Direction * &00000001 ; Direction bit (0=read, 1=write).
dmarf_Circular * &00000002 ; Scatter list is a circular buffer.
dmarf_Sync * &00000004 ; Call DMASync callback.
dmarf_Infinite * &00000008 ; Transfer is infinite length (must be circular).
dmarf_DontUpdate * &00000008 ; Don't update scatter list even if non-circular.
dmarf_Infinite * &00000010 ; Transfer is infinite length (must be circular).
dmarf_Uncacheable * &04000000 ; Pages for transfer have been marked as uncacheable.
dmarf_Halted * &08000000 ; Transfer has been halted due to Service_PagesUnsafe.
dmarf_Blocking * &10000000 ; DMA request blocking logical queue.
......
s/GetAll
View file @ 77cdce3b
......@@ -54,7 +54,7 @@ Module_BaseAddr
GBLL hostvdu
debug SETL false
hostvdu SETL false
hostvdu SETL true
mod SETD false
dma SETD false
unsf SETD false
......@@ -66,6 +66,8 @@ term SETD false
purge SETD false
tmp SETD false
debug_irqsafe SETL true
GBLL WriteBackCache
WriteBackCache SETL true ; Needed for StrongARM, and unless we add
; some way to set pages as write-though
......
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