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Created by Phil Pemberton@ppembertonDeveloper
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Add Bush Internet TV Set-top Box (IBX100) support

Note: This MR has several dependencies which must be merged before it:

Forum thread: https://www.riscosopen.org/forum/forums/3/topics/18881

This fairly large PR adds support for the Bush Internet TV set-top box to the IOMD HAL.

  • Add a new IOSystemType for the Bush IBX series.
  • Add support for the SMC 37C669 Super I/O (Combo) chip which seems unique to the Bush boxes.
  • Pass the Super I/O chip type correctly in HAL_SuperIOInfo
  • Extend HAL_PlatformName to include the set-top box (it previously called it an A7000)
  • The Bush IBX has an Atmel 32Kbit Serial EEPROM instead of the Philips real-time clock. Indicate to the Kernel that it needs to scan the I2C bus instead of assuming there's a Philips chip. (This should only happen if a 37C669 super-I/O and an ARM7500 or ARM7500FE are detected together)
  • The Virq self-test doesn't work on the IBX because of the missing VCO - so I've followed how things were done on the NC branch and disabled it for set-top-box builds running on ARM7500 and ARM7500FE.
    • I believe the test exists to prove that VIDC was basically functioning; the main issues (on RISC PC/Medusa/Kryten) being breaks in the Virq and Sirq connections between IOMD and VIDC, or a failure of the VIDC VCO. The other possible failure is a track break or loss of sound clock on the RPC.
      • None of the disconnection failure modes are applicable to an ARM7500 SoC because everything is on a single chip.
      • The VCO isn't present in Bush boxes, so the clock is derived from the I/O clock. If the I/O clock is down, then a lot of other stuff is going to be broken.
      • Therefore: turning this off is fairly low risk, except on an A7000, which has a VCO, and where a VCO failure is still a reasonable failure mode.
    • The reason for the failure is the VIDC falls back to using RCLK/2 (half the I/O clock) which is 16 MHz.
      • The target VCO frequency is around 50 MHz.
      • Running at 16 means the video signal is much slower than it should be. Virq interrupts happen once per frame, so will arrive much more slowly.

If disabling the Virq test is unreasonable, I can calculate the 'perfect' timing result (in 2MHz ticks) for the RCLK/2 clock, and check for that as a fallback if the Virq test fails with the ideal VCO clock. This should be safe as I don't think VIDC has a clock failure detector that would cause an oscillator switch.

Edited by Phil Pemberton