Build/Hdr2H,102

@@ -93,6 +93,14 @@ sub processfile {
 
 END
   while(<IN>) {
+    if(/^;NoHdr2H\{/) {		# Skip blocks that we're told to skip
+      while (<IN>) {
+        if (/^;NoHdr2H\}/) {
+          last;
+        }
+      }
+      next;
+    }
     s/\;.*//;
     next unless /\S/;
     s/\s+$//;

Build/InstViaRG,102

+#!/usr/bin/perl -w
+
+# Copyright (c) 2015, RISC OS Open Ltd
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met: 
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+#     * Redistributions in binary form must reproduce the above copyright
+#       notice, this list of conditions and the following disclaimer in the
+#       documentation and/or other materials provided with the distribution.
+#     * Neither the name of RISC OS Open Ltd nor the names of its contributors
+#       may be used to endorse or promote products derived from this software
+#       without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+
+# Script to produce a 'resgen' compatible via file of the resources that
+# would be exported by a C modules during the 'resources' phase, useful to
+# allow the module to have a RAM loading 'standalone' variant too.
+
+use strict;
+
+my $posix = -e '.';
+my $verbose = 0;
+my $localdir;
+my $resfsdir;
+my $viafile;
+
+sub usage
+{
+	die(<<EOF);
+Usage: $0 [-h] [-v] <local dir> <ResourceFS dir> <viafile>
+-h               Print this help.
+-v               Verbose.
+<local dir>      Directory where the files reside.
+                 This must use the system's native filesystem syntax.
+<ResourceFS dir> Target directory in ResourceFS.
+                 This should be in RISC OS format - directory separator is '.'
+<viafile>        Where to write the result.                 
+                 This must use the system's native filesystem syntax.
+EOF
+}
+
+sub scandir
+{
+	my $src = $_[0];
+	my $dst = $_[1];
+	my $srcpath;
+	my $dstpath;
+	my $sep = $posix ? '/' : '.';
+	my $leafname;
+	my $baselen = length($_[2]);
+	my $via = $_[3];
+	local (*DIR);
+
+	# Catalogue the candidate directory
+	opendir(DIR, $src) or die $!;
+	while ($leafname = readdir(DIR))
+	{
+		# Hide '.' names on Posix
+		next if ($leafname =~ m/^\./);
+		$srcpath = $src . $sep . $leafname;
+		$dstpath = $dst . substr($srcpath, $baselen);
+		if (-f $srcpath)
+		{
+			# It's a file, append to the via file
+			open(VIA, ">>$via") or die $!;
+			print VIA "$srcpath $dstpath\n";
+			close(VIA);
+		}
+		else
+		{
+			# The wobbly Perl 5.001 (distributed by ROOL) seems to explode
+			# all to easily when recursing even if just moving args about
+			scandir($srcpath, $_[1], $_[2], $_[3]);
+		}
+	}
+	closedir(DIR);
+}
+
+# Parse the command line
+
+usage() unless (@ARGV);
+
+while (1)
+{
+	$_ = $ARGV[0];
+	last if /^[^-]/;
+	shift;
+	# -h or --help
+	usage() if (/^-h$/ || /^--help$/);
+	# -v
+	$verbose += /^-v$/;
+}
+usage() unless (@ARGV);
+$localdir = shift;
+usage() unless (@ARGV);
+$resfsdir = shift;
+usage() unless (@ARGV);
+$viafile = shift;
+
+# Output a via file relating candidate leafnames to ResourceFS paths
+
+print "Scan $localdir for files to put in $resfsdir\n" if $verbose;
+unlink($viafile);
+scandir($localdir, $resfsdir, $localdir, $viafile);
+exit(0);

InstallTools,fd7

@@ -45,10 +45,6 @@ Echo
 Echo Installing the C Module Header Generator...
 Copy <SetPaths32$Dir>.Lib32.cmhg <Obey$Dir>.Acorn.cmhg A~C~D~FLN~P~Q~R~S~T~V
 
-Echo
-Echo Installing the Linker...
-Copy <SetPaths32$Dir>.Lib32.link <Obey$Dir>.Acorn.link A~C~D~FLN~P~Q~R~S~T~V
-
 Echo
 Echo Installing the Acorn Object File Decoder...
 Copy <SetPaths32$Dir>.Lib32.decaof <Obey$Dir>.Acorn.decaof A~C~D~FLN~P~Q~R~S~T~V
@@ -57,10 +53,22 @@ Echo
 Echo Installing the Library File Processor...
 Copy <SetPaths32$Dir>.Lib32.libfile <Obey$Dir>.Acorn.libfile A~C~D~FLN~P~Q~R~S~T~V
 
+Echo
+Echo Installing the Linker...
+Copy <SetPaths32$Dir>.Lib32.link <Obey$Dir>.Acorn.link A~C~D~FLN~P~Q~R~S~T~V
+
 Echo
 Echo Installing the Object Assembler...
 Copy <SetPaths32$Dir>.Lib32.objasm <Obey$Dir>.Acorn.objasm A~C~D~FLN~P~Q~R~S~T~V
 
+Echo
+Echo Installing the Object File Statistics Tool...
+Copy <SetPaths32$Dir>.Lib32.objsize <Obey$Dir>.Acorn.objsize A~C~D~FLN~P~Q~R~S~T~V
+
+Echo
+Echo Installing the Resource Area Generator...
+Copy <SetPaths32$Dir>.Lib32.ResGen <Obey$Dir>.Acorn.ResGen A~C~D~FLN~P~Q~R~S~T~V
+
 Echo
 Echo Installing the pre-built C++ libraries...
 CDir <Obey$Dir>.^.Export

Makefile

@@ -21,11 +21,13 @@ install_:
 install_DDE: install_Dir
 	${MKDIR} ${INSTDIR}.Build
 	${MKDIR} ${INSTDIR}.Unix
-	${CP} Build.canonical  ${INSTDIR}.canonical     ${CPFLAGS}
-	${CP} Build.stripdepnd ${INSTDIR}.stripdepnd    ${CPFLAGS}
-	${CP} Unix.chmod       ${INSTDIR}.Unix.chmod    ${CPFLAGS}
-	${CP} Unix.mkdir       ${INSTDIR}.mkdir         ${CPFLAGS}
-	${CP} Build.InstRes    ${INSTDIR}.Build.InstRes ${CPFLAGS}
+	${CP} Build.canonical  ${INSTDIR}.canonical       ${CPFLAGS}
+	${CP} Build.stripdepnd ${INSTDIR}.stripdepnd      ${CPFLAGS}
+	${CP} Unix.chmod       ${INSTDIR}.Unix.chmod      ${CPFLAGS}
+	${CP} Unix.mkdir       ${INSTDIR}.mkdir           ${CPFLAGS}
+	${CP} Build.FAppend    ${INSTDIR}.FAppend         ${CPFLAGS}
+	${CP} Build.InstRes    ${INSTDIR}.Build.InstRes   ${CPFLAGS}
+	${CP} Build.InstViaRG  ${INSTDIR}.Build.InstViaRG ${CPFLAGS}
 
 install_STB: install_Dir
 	${CP} Unix.chmod ${INSTDIR}.chmod ${CPFLAGS}

Misc/decgen/!ReadMe

-decgen - Instruction set decoder generator - V1.41, 2014/02/07
+decgen - Instruction set decoder generator - V1.41b, 2017/04/15
 ======
 
 
@@ -494,6 +494,9 @@ From time to time decgen may throw an assert, or even worse, crash. This is like
 History
 =======
 
+V1.41b - 2017/04/15
+  * Rebuilt RISC OS binary with GCCSDK 4.7.4 release 3, to produce an ARMv8 compatible binary
+  * No other changes
 V1.41 - 2014/02/07
   * Fixed bug in regular code generator that would result in the wrong paths being taken for many trees
   * Improved action handling so that identical actions will be merged together

Misc/decgen/encodings/ARMv7

@@ -15,14 +15,12 @@
 (cond:4)0001(op:4)(:12)1001(:4)	{ne(cond,15)} {lt(op,8)} {band(op,3)}	UNDEFINED
 
 # A5.2.11
-(cond:4)00110(op)10(op1:4)(:8)(op2:8)	{ne(cond,15)} {lnot(op)} {lnot(op1)} {gt(op2,4)} {lt(op2,0xf0)}	UNALLOCATED_HINT
+(cond:4)00110(op)10(op1:4)(:8)(op2:8)	{ne(cond,15)} {lnot(op)} {lnot(op1)} {gt(op2,5)} {lt(op2,0xf0)}	UNALLOCATED_HINT
 
 # A5.2.12
 (cond:4)00010(op:2)0(op1:4)(:8)0(op2:3)(:4)	{ne(cond,15)} {eq(op2,1)} {lnot(band(op,1))}	UNDEFINED
 (cond:4)00010(op:2)0(op1:4)(:8)0(op2:3)(:4)	{ne(cond,15)} {eq(band(op2,6),2)} {ne(op,1)}	UNDEFINED
-(cond:4)00010(op:2)0(op1:4)(:8)0(op2:3)(:4)	{ne(cond,15)} {eq(op2,4)}	UNDEFINED
 (cond:4)00010(op:2)0(op1:4)(:8)0(op2:3)(:4)	{ne(cond,15)} {eq(op2,6)} {ne(op,3)}	UNDEFINED
-(cond:4)00010(op:2)0(op1:4)(:8)0(op2:3)(:4)	{ne(cond,15)} {eq(op2,7)} {lnot(op)}	UNDEFINED
 
 # A5.4
 (cond:4)011(op1:5)(:4)(Rd:4)(:4)(op2:3)1(Rn:4)	{lt(cond,14)} {eq(op1,31)} {eq(op2,7)}	PERMA_UNDEFINED
@@ -328,20 +326,10 @@
 (cond:4)000PU0W0(Rn:4)(Rt:4)(0000)1101(Rm:4)	{ne(cond,15)} {lor(opcode<24>,lnot(opcode<21>))}	LDRD_reg_A1 # Note manual disambiguation (see A5.2)
 
 # A8.8.75 LDREX
-# A1 ARMv6*, ARMv7
-(cond:4)00011001(Rn:4)(Rt:4)(1111)1001(1111)	{ne(cond,15)}	LDREX_A1
-
 # A8.8.76 LDREXB
-# A1 ARMv6K, ARMv7
-(cond:4)00011101(Rn:4)(Rt:4)(1111)1001(1111)	{ne(cond,15)}	LDREXB_A1
-
 # A8.8.77 LDREXD
-# A1 ARMv6K, ARMv7
-(cond:4)00011011(Rn:4)(Rt:4)(1111)1001(1111)	{ne(cond,15)}	LDREXD_A1
-
 # A8.8.78 LDREXH
-# A1 ARMv6K, ARMv7
-(cond:4)00011111(Rn:4)(Rt:4)(1111)1001(1111)	{ne(cond,15)}	LDREXH_A1
+# See ARMv8/nARMv8 for the differing encodings of these instructions
 
 # A8.8.80 LDRH (immediate, ARM)
 # A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
@@ -848,20 +836,10 @@
 (cond:4)000PU0W0(Rn:4)(Rt:4)(0000)1111(Rm:4)	{ne(cond,15)} {lor(opcode<24>,lnot(opcode<21>))}	STRD_reg_A1 # Note manual disambiguation (see A5.2)
 
 # A8.8.212 STREX
-# A1 ARMv6*, ARMv7
-(cond:4)00011000(Rn:4)(Rd:4)(1111)1001(Rt:4)	{ne(cond,15)}	STREX_A1
-
 # A8.8.213 STREXB
-# A1 ARMv6K, ARMv7
-(cond:4)00011100(Rn:4)(Rd:4)(1111)1001(Rt:4)	{ne(cond,15)}	STREXB_A1
-
 # A8.8.214 STREXD
-# A1 ARMv6K, ARMv7
-(cond:4)00011010(Rn:4)(Rd:4)(1111)1001(Rt:4)	{ne(cond,15)}	STREXD_A1
-
 # A8.8.215 STREXH
-# A1 ARMv6K, ARMv7
-(cond:4)00011110(Rn:4)(Rd:4)(1111)1001(Rt:4)	{ne(cond,15)}	STREXH_A1
+# See ARMv8/nARMv8 for the differing encodings of these instructions
 
 # A8.8.217 STRH (immediate, ARM)
 # A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7

Misc/decgen/encodings/ARMv8_AArch32

+# From DDI 0487A.g section J5
+# Can be overlaid directly on top of the ARMv7 encodings
+
+# F6.1.54 Load-Aquire
+(cond:4)00011(sz:2)1(Rn:4)(Rt:4)(11)001001(1111)	{ne(cond,15)} {ne(sz,1)}	LDA_A1
+
+# F6.1.210 Store-Release
+(cond:4)00011(sz:2)0(Rn:4)(1111)(11)001001(Rt:4)	{ne(cond,15)} {ne(sz,1)}	STL_A1
+
+# F6.1.56 Load-Aquire Exclusive
+(cond:4)00011001(Rn:4)(Rt:4)(11)101001(1111)	{ne(cond,15)}	LDAEX_A1
+(cond:4)00011011(Rn:4)(Rt:4)(11)101001(1111)	{ne(cond,15)}	LDAEXD_A1
+(cond:4)00011101(Rn:4)(Rt:4)(11)101001(1111)	{ne(cond,15)}	LDAEXB_A1
+(cond:4)00011111(Rn:4)(Rt:4)(11)101001(1111)	{ne(cond,15)}	LDAEXH_A1
+
+# F6.1.212 Store-Release Exclusive
+(cond:4)00011000(Rn:4)(Rd:4)(11)101001(Rt:4)	{ne(cond,15)}	STLEX_A1
+(cond:4)00011010(Rn:4)(Rd:4)(11)101001(Rt:4)	{ne(cond,15)}	STLEXD_A1
+(cond:4)00011100(Rn:4)(Rd:4)(11)101001(Rt:4)	{ne(cond,15)}	STLEXB_A1
+(cond:4)00011110(Rn:4)(Rd:4)(11)101001(Rt:4)	{ne(cond,15)}	STLEXH_A1
+
+# Table J5.7.1 External Debug
+# DCPS1/2/3 has no A32 encoding
+
+# F6.1.50 Halting breakpoint
+(cond:4)00010(op:2)0(imm12:12)0(op2:3)(imm4:4)	{ne(cond,15)} {eq(op2,7)} {lnot(op)}	HLT_A1
+
+# Table J5.7.2 Barriers and hints
+# DMB OSHLD/NSHLD/ISHLD/LD see F6.1.44, same encoding as ARMv7
+# DSB OSHLD/NSHLD/ISHLD/LD see F6.1.45, same encoding as ARMv7
+
+# F6.1.179 Send event local
+(cond:4)001100100000(11110000)00000101	{ne(cond,15)}	SEVL_A1
+
+# Table J5.7.3 TLB maintenance
+# Accessed using MCR operations, so no new opcodes
+
+# F6.1.40 CRC
+(cond:4)00010(sz:2)0(Rn:4)(Rd:4)(0)(0)C(0)0(op2:3)(Rm:4)	{ne(cond,15)} {eq(op2,4)}	CRC_A1
+
+# Note that [LDR|STR]EX[B|H|D] appear here because previously
+# bits 8-11 SBO, but that recommendation has changed because
+# ARMv8 has added [LDA|STL]EX[B|H|D] in the same instruction space.
+
+# F4.2.10
+(cond:4)0001(op:4)(:8)(11)(op1:2)1001(:4)	{ne(cond,15)} {lor(eq(op,8),eq(op,9))} {eq(op1,1)}	UNDEFINED
+(cond:4)0001(op:4)(:8)(11)(op1:2)1001(:4)	{ne(cond,15)} {lor(eq(op,10),eq(op,11))} {lnot(band(op1,2))}	UNDEFINED
+(cond:4)0001(op:4)(:8)(11)(op1:2)1001(:4)	{ne(cond,15)} {ge(op,12)} {eq(op1,1)}	UNDEFINED
+
+# F6.1.229 STREX
+# A1 ARMv6*, ARMv7
+(cond:4)00011000(Rn:4)(Rd:4)(11)111001(Rt:4)	{ne(cond,15)}	STREX_A1
+
+# F6.1.230 STREXB
+# A1 ARMv6K, ARMv7
+(cond:4)00011100(Rn:4)(Rd:4)(11)111001(Rt:4)	{ne(cond,15)}	STREXB_A1
+
+# F6.1.231 STREXD
+# A1 ARMv6K, ARMv7
+(cond:4)00011010(Rn:4)(Rd:4)(11)111001(Rt:4)	{ne(cond,15)}	STREXD_A1
+
+# F6.1.232 STREXH
+# A1 ARMv6K, ARMv7
+(cond:4)00011110(Rn:4)(Rd:4)(11)111001(Rt:4)	{ne(cond,15)}	STREXH_A1
+
+# F6.1.79 LDREX
+# A1 ARMv6*, ARMv7
+(cond:4)00011001(Rn:4)(Rt:4)(11)111001(1111)	{ne(cond,15)}	LDREX_A1
+
+# F6.1.80 LDREXB
+# A1 ARMv6K, ARMv7
+(cond:4)00011101(Rn:4)(Rt:4)(11)111001(1111)	{ne(cond,15)}	LDREXB_A1
+
+# F6.1.81 LDREXD
+# A1 ARMv6K, ARMv7
+(cond:4)00011011(Rn:4)(Rt:4)(11)111001(1111)	{ne(cond,15)}	LDREXD_A1
+
+# F6.1.82 LDREXH
+# A1 ARMv6K, ARMv7
+(cond:4)00011111(Rn:4)(Rt:4)(11)111001(1111)	{ne(cond,15)}	LDREXH_A1

Misc/decgen/encodings/ARMv8_nAArch32

+# From DDI 0487A.g section J5
+# Overlay this with ARMv7 encodings to fill the holes where ARMv8 additions are
+
+# F6.1.54 Load-Aquire
+# F6.1.210 Store-Release
+# F6.1.56 Load-Aquire Exclusive
+# F6.1.212 Store-Release Exclusive
+# These alias into the LDREX/STREX family (see below)
+
+# F6.1.50 Halting breakpoint
+(cond:4)00010(op:2)0(op1:4)(:8)0(op2:3)(:4)	{ne(cond,15)} {eq(op2,7)} {lnot(op)}	UNDEFINED
+
+# F6.1.179 Send event local
+(cond:4)001100100000(11110000)00000101	{ne(cond,15)}	UNALLOCATED_MEM_HINT
+
+# F6.1.40 CRC
+(cond:4)00010(op:2)0(op1:4)(:8)0(op2:3)(:4)	{ne(cond,15)} {eq(op2,4)}	UNDEFINED
+
+# Note that [LDR|STR]EX[B|H|D] appear here because previously
+# bits 8-11 SBO, but that recommendation has changed because
+# ARMv8 has added [LDA|STL]EX[B|H|D] in the same instruction space.
+
+# A8.8.212 in DDI 0406C STREX
+# A1 ARMv6*, ARMv7
+(cond:4)00011000(Rn:4)(Rd:4)(1111)1001(Rt:4)	{ne(cond,15)}	STREX_A1
+
+# A8.8.213 in DDI 0406C STREXB
+# A1 ARMv6K, ARMv7
+(cond:4)00011100(Rn:4)(Rd:4)(1111)1001(Rt:4)	{ne(cond,15)}	STREXB_A1
+
+# A8.8.214 in DDI 0406C STREXD
+# A1 ARMv6K, ARMv7
+(cond:4)00011010(Rn:4)(Rd:4)(1111)1001(Rt:4)	{ne(cond,15)}	STREXD_A1
+
+# A8.8.215 in DDI 0406C STREXH
+# A1 ARMv6K, ARMv7
+(cond:4)00011110(Rn:4)(Rd:4)(1111)1001(Rt:4)	{ne(cond,15)}	STREXH_A1
+
+# A8.8.75 in DDI 0406C LDREX
+# A1 ARMv6*, ARMv7
+(cond:4)00011001(Rn:4)(Rt:4)(1111)1001(1111)	{ne(cond,15)}	LDREX_A1
+
+# A8.8.76 in DDI 0406C LDREXB
+# A1 ARMv6K, ARMv7
+(cond:4)00011101(Rn:4)(Rt:4)(1111)1001(1111)	{ne(cond,15)}	LDREXB_A1
+
+# A8.8.77 in DDI 0406C LDREXD
+# A1 ARMv6K, ARMv7
+(cond:4)00011011(Rn:4)(Rt:4)(1111)1001(1111)	{ne(cond,15)}	LDREXD_A1
+
+# A8.8.78 in DDI 0406C LDREXH
+# A1 ARMv6K, ARMv7
+(cond:4)00011111(Rn:4)(Rt:4)(1111)1001(1111)	{ne(cond,15)}	LDREXH_A1

ToolOptions/APCS-32,feb

@@ -18,28 +18,26 @@
                                  Set Alias$CC %%CC -APCS 3/32bit/fpe3 -memaccess -L22-S22-L41 %%*0
 If "<Machine>"="Archimedes" then Set Alias$CC %%CC -APCS 3/32bit/fpe3 -memaccess -L22-S22+L41 %%*0
 If "<Machine>"="All32"      then Set Alias$CC %%CC -APCS 3/32bit/fpe3 -cpu 3 -memaccess -L22-S22-L41 %%*0
+If "<Machine>"="26"         then Set Alias$CC %%CC -APCS 3/32bit/fpe3 -memaccess -L22-S22+L41 %%*0
 If "<Machine>"="32"         then Set Alias$CC %%CC -APCS 3/32bit/fpe3 -cpu 3 -memaccess -L22-S22+L41 %%*0
 If "<Machine>"="Tungsten"   then Set Alias$CC %%CC -APCS 3/32bit/fpe3 -cpu 5TE -memaccess +L22+S22+L41 %%*0
 If "<Machine>"="ARM11ZF"    then Set Alias$CC %%CC -APCS 3/32bit/fpe3 -cpu 6 -memaccess +L22+S22-L41 %%*0
 If "<Machine>"="RPi"        then Set Alias$CC %%CC -APCS 3/32bit/fpe3 -cpu 6 -memaccess +L22+S22-L41 %%*0
-If "<Machine>"="CortexA8"   then Set Alias$CC %%CC -APCS 3/32bit/fpe3 -cpu 6 -memaccess +L22+S22-L41 %%*0
-If "<Machine>"="CortexA9"   then Set Alias$CC %%CC -APCS 3/32bit/fpe3 -cpu 6 -memaccess +L22+S22-L41 %%*0
-                                 Set Alias$ObjAsm %%ObjAsm -APCS 3/32bit %%*0
-if "<Machine>"="All32"      then Set Alias$ObjAsm %%ObjAsm -APCS 3/32bit -cpu 3 %%*0
-if "<Machine>"="32"         then Set Alias$ObjAsm %%ObjAsm -APCS 3/32bit -cpu 3 %%*0
-if "<Machine>"="Tungsten"   then Set Alias$ObjAsm %%ObjAsm -APCS 3/32bit -cpu 5TE %%*0
-if "<Machine>"="ARM11ZF"    then Set Alias$ObjAsm %%ObjAsm -APCS 3/32bit/fpe3 -cpu 6Z --fpu VFPv2 %%*0
-if "<Machine>"="RPi"        then Set Alias$ObjAsm %%ObjAsm -APCS 3/32bit/fpe3 -cpu 6Z --fpu VFPv2 %%*0
-if "<Machine>"="CortexA8"   then Set Alias$ObjAsm %%ObjAsm -APCS 3/32bit/fpe3 -cpu Cortex-A8 %%*0
-if "<Machine>"="CortexA9"   then Set Alias$ObjAsm %%ObjAsm -APCS 3/32bit/fpe3 -cpu Cortex-A9 %%*0
-| Fall back to -cpu 5TEJ for older versions of objasm
-objasm -h { > <Wimp$ScrapDir>.ToolOptions }
-| 1 will be returned for unrecognised parameters, e.g. -fpu
-if "<Sys$ReturnCode>"="1"   then Set Alias$ObjAsm %%ObjAsm -APCS 3/32bit -cpu 5TEJ %%*0
-| 0 will be returned for unrecognised -cpu options, so check any warning output
-grep -F "Target cpu not recognised" <Wimp$ScrapDir>.ToolOptions { > null: }
-if "<Sys$ReturnCode>"="0"   then Set Alias$ObjAsm %%ObjAsm -APCS 3/32bit -cpu 5TEJ %%*0
-remove <Wimp$ScrapDir>.ToolOptions 
+If "<Machine>"="CortexA8"   then Set Alias$CC %%CC -APCS 3/32bit/fpe3 -cpu 7 -memaccess +L22+S22-L41 %%*0
+If "<Machine>"="CortexA9"   then Set Alias$CC %%CC -APCS 3/32bit/fpe3 -cpu 7 -memaccess +L22+S22-L41 %%*0
+If "<Machine>"="CortexA7"   then Set Alias$CC %%CC -APCS 3/32bit/fpe3 -cpu 7 -memaccess +L22+S22-L41 %%*0
+Unset Build$ObjAsmCPU
+if "<Machine>"="All32"      then Set Build$ObjAsmCPU -cpu 3
+if "<Machine>"="32"         then Set Build$ObjAsmCPU -cpu 3
+if "<Machine>"="Tungsten"   then Set Build$ObjAsmCPU -cpu 5TE
+if "<Machine>"="ARM11ZF"    then Set Build$ObjAsmCPU -cpu 6Z --fpu VFPv2
+if "<Machine>"="RPi"        then Set Build$ObjAsmCPU -cpu 6Z --fpu VFPv2
+if "<Machine>"="CortexA8"   then Set Build$ObjAsmCPU -cpu Cortex-A8
+if "<Machine>"="CortexA9"   then Set Build$ObjAsmCPU -cpu Cortex-A9
+if "<Machine>"="CortexA7"   then Set Build$ObjAsmCPU -cpu Cortex-A7
+Set Alias$ObjAsm %%ObjAsm -APCS 3/32bit/fpe3 <Build$ObjAsmCPU> %%*0
+| Declare an alias for VFP APCS variants (necessary to get the correct word ordering with DCFD)
+Set Alias$ObjAsmVFP %%ObjAsm -APCS 3/32bit/vfp <Build$ObjAsmCPU> %%*0
 Set Alias$CMHG %%CMHG -32bit %%*0
 Set Alias$ResGen %%ResGen -32bit %%*0
 Set Alias$DefMod %%DefMod.!Run -32bit %%*0