Commit 9d64f9a2 authored by Kevin Bracey's avatar Kevin Bracey

Version RO_3_71 taken

parent 4c986483
......@@ -222,7 +222,10 @@ install_Configure:
${CP} Configure.Monitors.Acorn.AKF52 ${RESOURCES}.Configure.Monitors.Acorn.AKF52 ${CPFLAGS}
${CP} Configure.Monitors.Acorn.AKF53 ${RESOURCES}.Configure.Monitors.Acorn.AKF53 ${CPFLAGS}
${CP} Configure.Monitors.Acorn.AKF60 ${RESOURCES}.Configure.Monitors.Acorn.AKF60 ${CPFLAGS}
${CP} Configure.Monitors.Acorn.AKF65 ${RESOURCES}.Configure.Monitors.Acorn.AKF65 ${CPFLAGS}
${CP} Configure.Monitors.Acorn.AKF85 ${RESOURCES}.Configure.Monitors.Acorn.AKF85 ${CPFLAGS}
${CP} Configure.Monitors.Acorn.AKF91 ${RESOURCES}.Configure.Monitors.Acorn.AKF91 ${CPFLAGS}
${CP} Configure.Monitors.Acorn.AKF92 ${RESOURCES}.Configure.Monitors.Acorn.AKF92 ${CPFLAGS}
${CP} Configure.Textures ${RESOURCES}.Configure.Textures ${CPFLAGS}
install_BootVars: Utils.BootVars
......
/<Obey$Dir>.BandLimit 38000 76000 152000 80000
/<Obey$Dir>.SetPreDesk
/BootResources:Configure.ClrMonitor
/<PreDesk$Configure>
......@@ -13,4 +13,4 @@
| limitations under the License.
|
LoadModeFile BootResources:Configure.Monitors.Acorn.AKF60
WimpMode X800 Y600 C16
WimpMode X800 Y600 C256
Area:ROM-Patches
Version:1.17D (30. Nov 1994)
E00:Diese Patches können nur mit RISC OS Version 3.50 verwendet werden
E01:Das ROM ist bereits nachgebessert worden
E02:Es wurde ein ungültiges ROM gefunden
E03:Es konnte kein Speicher für die Patches bereitgestellt werden
| Copyright 1996 Acorn Computers Ltd
| Copyright 1997 Acorn Computers Ltd
|
| Licensed under the Apache License, Version 2.0 (the "License");
| you may not use this file except in compliance with the License.
......@@ -12,7 +12,5 @@
| See the License for the specific language governing permissions and
| limitations under the License.
|
| > !Run
Set ROMPatch$Dir <Obey$Dir>
WimpSlot -min 128K -max 128K
If "<Territory>"="7" OR "<Territory>"="35" Then Run <ROMPatch$Dir>.Germany.!RunImage Else Run <ROMPatch$Dir>.UK.!RunImage
WimpSlot -min 128K
Run <Obey$Dir>.ROMPatch.!RunImage
| Copyright 1996 Acorn Computers Ltd
| Copyright 1997 Acorn Computers Ltd
|
| Licensed under the Apache License, Version 2.0 (the "License");
| you may not use this file except in compliance with the License.
......@@ -12,7 +12,4 @@
| See the License for the specific language governing permissions and
| limitations under the License.
|
| > !Run
Set ROMPatch$Dir <Obey$Dir>
WimpSlot -min 128K -max 128K
Run <ROMPatch$Dir>.UK.!RunImage
|do nothing
# Copyright 1997 Acorn Computers Ltd
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
# Project: rompatch
# Toolflags:
CCflags = -c -depend !Depend -IC: -throwback -ff
C++flags = -c -depend !Depend -IC: -throwback
Linkflags = -aif -c++ -o $@
ObjAsmflags = -throwback -NoCache -depend !Depend
CMHGflags =
LibFileflags = -c -o $@
Squeezeflags = -o $@
# Final targets:
@.Install.ROMPatch.!RunImage: @.binary.!RunImageU
squeeze $(squeezeflags) @.binary.!RunImageU
@.binary.!RunImageU: @.o.debug @.o.rompatch @.o.asmutils @.o.module \
ADFS::HardDisc4.$.AcornC_C++.Libraries.clib.o.Stubs
link $(linkflags) @.o.debug @.o.rompatch @.o.asmutils @.o.module \
ADFS::HardDisc4.$.AcornC_C++.Libraries.clib.o.Stubs
# User-editable dependencies:
# Static dependencies:
@.o.debug: @.c.debug
cc $(ccflags) -o @.o.debug @.c.debug
@.o.rompatch: @.c.rompatch
cc $(ccflags) -o @.o.rompatch @.c.rompatch
@.o.asmutils: @.s.asmutils
objasm $(objasmflags) -from @.s.asmutils -to @.o.asmutils
@.o.module: @.s.module
objasm $(objasmflags) -from @.s.module -to @.o.module
# Dynamic dependencies:
New version of ROMPatch, introduced to patch 3.70,
and added to source tree for 3.71.
*** There is no proper make install - if changed, the ***
*** new !!ROMPatch obey file and ROMPatch directory ***
*** (from Install directory) should be placed in: ***
*** ***
*** Sources.SystemRes.Boot.RO360Hook.Boot.PreDesk ***
[ This release of ROMPatches also supports patching 3.60.
To achieve this, the !!ROMPatch obey file and the ROMPatch
directory should be in !Boot.Choices.Boot.Tasks in the
3.6 !Boot. ]
Area:ROM patches
Version:1.17 (30 Nov 1994)
E00:These patches can only be applied to RISC OS 3.50
E01:ROM already patched
E02:Incorrect ROM image
E03:Couldn't allocate memory for patches
About ROMPatch
--------------
This is an entirely new version of ROMpatch, coded in C and assembler,
and using an improved mapping strategy. It breaks ROM mapping into
sections, large pages and pages, retaining larger mappings where
possible (the restriction being that patch hits must appear in
pages). The old version always breaks the ROM entirely into pages.
The advantage of retaining larger mapping granularity is that it
is potentially far less likely to provoke MMU TLB misses (the
unpatched ROM is mapped very efficiently, as 4x 1Mb sections).
Version 2.02 supports patches for multiple ROMs (within reason).
A brief description of files in this directory follows:
binary holds interim build target(s); just the
unsqueezed runimage in this case
c.rompatch most of C code
c.debug routines for debugging only
docs.xxx other documents, including info on StrongARM bug, and
results of binary and source code searches
h.debug defs used only for debugging
h.defs types and defs
Install target stuff for distribution; the obey file
!!ROMPatch and the directory ROMPatch should be
placed in the user's !Boot.Choices.Boot.PreDesk, to
implement patches; the make builds ROMPatch.!RunImage;
a ReadMe and TechNote for distribution are also there
patches.h.patch structure that collects all patch groups for all ROMs together
patches.370.h.* all patches for RISC OS 3.70
patches.360.h.* all patches for RISC OS 3.60
pdiff contains C app that can compare two 4Mb ROM files,
and output difference list in style required for
a patches.h file
s.asmutils routines implemented in assembler (they require
supervisor status)
s.module construction of module that is inserted to handle
patches dynamic area (mainly, to remove patches on reset)
UK compile-time internationalisation (yeah, want to make
something of it?)
Adding a ROM supported by patches
---------------------------------
See patches.h.patch. Should be straightforward, but note that some code may
be affected by OS variable placement changes (see h.defs and the assembler source
in the s directory). Only 4 Mb ROMs are currently supported.
Adding a patch group:
---------------------
See patches.360.h.* and patches.370.h.* for examples. Each ROM has an h.patch
file that collects the patches together. Each patch must define a procedure of
the form:
static patchentry_t *somepatches_proc(void *handle)
{
/* return either a list of patchentry_t triplets, terminated by {0,0,0},
or NULL meaning this group not required in this configuration */
}
The generic handle is currently not used (always passed as NULL).
This function is then of type patchlist_proc, and suitable for inclusion
in the list of functions (terminated by NULL), in h.patch.
Note that the function must be callable more than once.
See patches.370.h.STMHpatch for an example of a patch conditional on current
configuration. See patches.370.h.RTCAfix for an example of a 'patch' that
doesn't output a patch, but applies a runtime fix.
---
mjs/issue 2, 24 Feb 97
From brash@AM.RDGENG.REO.RDGENG.RDGMTS.mts.dec.com Tue Oct 15 12:26:29 1996
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Date: Tue, 15 Oct 1996 12:18:35 +0000 (GMT)
From: BRASH DTN 830-6163 <brash@AM.RDGENG.REO.mts.dec.com>
Subject: FWD: Re: StrongARM bug (fwd) (fwd)
To: Mike Stephens <mstephens>
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From: Stephen Streater <sbs@eidos.co.uk>
Subject: Re: StrongARM bug (fwd) (fwd)
To: "david.brash" <david.brash@reo.mts.dec.com>
Cc: sbs <sbs@eidos.co.uk>
Reply-to: sbs <sbs@eidos.co.uk>
Message-id: <1641@eidos.co.uk>
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Forwarded message follows:
I think this is what you need. We have verified that this does in
fact fix all the known problems which we have been having at Eidos.
> > > > This is related to other (fixed) bugs on earlier revisions of
> > > > the silicon, and shows up in Rev J (Eidos prototypes) and Rev K
> > > > (as distributed by ART). This program is a RISC PC+SA program
> > > > which tests out the STM on line 220 until it breaks once or it
> > > > succeeds 100,000 times.
> > > >
> > > > Summary of the bug:
> > > > In SVC26 or SVC32 modes, STM with a ^ storing both USR and SVC
> > > > mode registers (R10-R12 USR and R13-R14 SVC) can store R11 twice
> > > > instead of R11 and R12.
> > > >
> > > > This bug does not seem to occur if the STM is to memory in the
> > > > cache.
> > > >
> > > > On uncached memory, this code seems to go wrong only about 1/800
> > > > of the time - could this be something to do with the D-CACHE
> > > > size - it seems reasonably consistent where it goes wrong.
> > > >
> > > > The alignment of the STM affects the bug - the code is assembled
> > > > 8 times at 4 byte intervals, and half of them work consistently,
> > > > half of them don't work.
> > > >
> > > > Draining the write buffer after the STM does not affect the
> > > > reliablity of the program.
>
>
> Stephen,
>
> Rich Witek and I believe we have located and reproduced the bug. It
> is, we believe, a fairly easy metal 1 fix. Temporarily, the following
> software workaround should fix the problem:
>
> Where you have:
> stmia r9, {r10-r14}^
>
> Replace with:
> mcr MMUCP, 0, r9, MMUIDReg, c0
> stmia r9, {r10-r14}^
>
> along with the definitions:
> MMUCP CP 15
> MMUIDReg CN 0
>
> This will effectively insert a nop (a store TO the chip ID register)
> which will not fault and allow the stmia enough time to complete
> properly. This has been verified on our behavioral model.
>
> There are some internal workings associated with the mcr that make
> it necessary to insert this opcode instead of a simple nop. We have
> also verified that non-hat stmia opcodes do not exhibit this behavior.
>
> Please try this in your environment and let Rich and I know the results.
> Rich is at witek@pa.dec.com.
>
> Thanks for your help and we'll get back to you as soon as we finalize
> the actual fix.
>
>
> ken
> +-----------------------------------------------------------------+
> | Any comments or opinions are solely those of the author |
> | and not Digital Equipment Corporation. |
> +-----------------------------------------------------------------+
> | Ken Patton patton@pa.dec.com |
> | Digital Semiconductor |
> | Austin Research & Design Center Austin, Texas |
> +-----------------------------------------------------------------+
> | I have seen enough to know that I have seen too much. |
> +-----------------------------------------------------------------+
>
>
Stephen Streater
From brash@AM.RDGENG.REO.RDGENG.RDGMTS.mts.dec.com Tue Oct 15 13:32:36 1996
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Date: Tue, 15 Oct 1996 12:33:40 +0000 (GMT)
From: BRASH DTN 830-6163 <brash@AM.RDGENG.REO.mts.dec.com>
Subject: Re: STM^ Problem....generic problem description and fix
In-reply-to: <G202028C414OCT199616231719@valmts.vbe.dec.com>
To: Mike Stephens <mstephens>, Joe Barrett <joe.barrett@armltd.co.uk>,
David Jaggar <dave.jaggar@armltd.co.uk>, Sophie Wilson <swilson>
Cc: Anthony Berent <"anthony berent"@REO.mts.dec.com>,
David Rusling <"david rusling"@REO.mts.dec.com>,
Michael Quinn <"michael quinn"@REO.mts.dec.com>,
Neal Crook <"neal crook"@REO.mts.dec.com>,
Sean Reynolds <"sean reynolds"@REO.mts.dec.com>
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11-Oct-1996
The SA110 with ID register (CP15 Register 1)
revision less than 3 have a bug in User Register Store Multiple
instruction (STM^). This is the PRIVILEGED MODE STM that is used to store
user mode registers while in a privileged mode. If the STM^ is executed
while a data cache fill is completing the store address for all but the
first register may be wrong.
This is fix in the SA110 revision 3 and the following software work around
can be used on revision 2 parts. Precede the STM^ with
any of the following, a store that is not a STM^, a MCR, or an MRC.
Note a "MCR P15, 0, r0, c0, c0, 0", which is a write to the ID register
and on the SA110 is a NOP will fix the problem and uses no registers,
nor does any writes to memory.
"ADFS::HardDisc5.$.jag810.sources.Lib.RISC_OSLib.kernel.s.k_body", line 768: STMIB r14, {r1-r14}^
"ADFS::HardDisc5.$.jag810.sources.Lib.RISC_OSLib.kernel.s.k_body", line 1360: STMIA r14, {r0-r14}^
"ADFS::HardDisc5.$.jag810.sources.Lib.RISC_OSLib.kernel.s.k_body", line 1396: STMDB r11, {r13}^
"ADFS::HardDisc5.$.jag810.sources.NetWorking.Econet.s.Receive", line 626: STMIA r9!, { r0-r14 } ^ ; Put down user R0 to R14, R9 now has address of R15
"ADFS::HardDisc5.$.jag810.sources.OS_Core.Desktop.TaskWindow.s.Taskman", line 3720: STMIA r14, {r0-r14}^
"ADFS::HardDisc5.$.jag810.sources.OS_Core.FileSys.FileSwitch.s.FSControl", line 430: STMIA r2, {r6-r9, r13-r14}^ ; Must preserve r13_usr and r14_usr
"ADFS::HardDisc5.$.jag810.sources.OS_Core.HWSupport.FPASC.coresrc.s.fpaundef", line 49: STMIA Rsp,{R0-R14}^ ; use writeback on such STMs
"ADFS::HardDisc5.$.jag810.sources.OS_Core.HWSupport.FPASC.coresrc.s.fpeundef", line 49: STMIA Rsp,{R0-R14}^ ; use writeback on such STMs
"ADFS::HardDisc5.$.jag810.sources.OS_Core.Kernel.s.ARM600", line 2634: STMEQIA r2, {r8-r14}^
"ADFS::HardDisc5.$.jag810.sources.OS_Core.Kernel.s.ARM600", line 2651: STMIA sp_svc, {r8-r15}^ ; save USR bank in case STM ^, and also so we can corrupt them
"ADFS::HardDisc5.$.jag810.sources.OS_Core.Kernel.s.Kernel", line 801: STMIA r14, {r0-r14}^ ; user registers
"ADFS::HardDisc5.$.jag810.sources.OS_Core.Kernel.s.Middle", line 240: STMIA r0, {r1-r12, r13_usr, r14_usr}^ ; user mode case done.
"ADFS::HardDisc5.$.jag810.sources.OS_Core.Kernel.s.Middle", line 586: STMEQIA R0, {R8-R14}^ ; user mode case done.
"ADFS::HardDisc5.$.jag810.sources.Printing.Printers.Modules.PDModules.s.PDriverDP.Private", line 154: STMFD SP,{LR}^ ;preserve user LR
RISC OS 3.70 binary searches, StrongARM STM{}^ problem
------------------------------------------------------
03803A10 . : E8CE7FFF : STMIA R14,{R0-R14}^ ; sources.OS_Core.Kernel.s.Kernel, line 801
03813520 . : E8C07FFE : STMIA R0,{R1-R14}^ ; sources.OS_Core.Kernel.s.Middle, line 240
038138A0 ... : 08C07F00 : STMEQIA R0,{R8-R14}^ ; sources.OS_Core.Kernel.s.Middle, line 586
038162C0 ... : 08C27F00 : STMEQIA R2,{R8-R14}^ ; sources.OS_Core.Kernel.s.ARM600, line 2533
038162EC . : E8CDFF00 : STMIA R13,{R8-PC}^ ; sources.OS_Core.Kernel.s.ARM600, line 2550
03835160 c : E8C263C0 : STMIA R2,{R6-R9,R13,R14}^ ; sources.OS_Core.FileSys.FileSwitch.s.FSControl, line 430
03938FB0 . : E8E97FFF : STMIA R9!,{R0-R14}^ ; sources.NetWorking.Econet.s.Receive, line 626
0396A30C . : E8CD7FFF : STMIA R13,{R0-R14}^ ; sources.OS_Core.HWSupport.FPASC.coresrc.s.fpaundef, line 49
0396AEA0 . : E8CD7FFF : STMIA R13,{R0-R14}^ ; sources.OS_Core.HWSupport.FPASC.coresrc.s.fpeundef, line 49
039E8690 . : E8CE7FFF : STMIA R14,{R0-R14}^ ; sources.OS_Core.Desktop.TaskWindow.s.Taskman, line 3720
03A165D8 . : E9CE7FFE : STMIB R14,{R1-R14}^ ; sources.Lib.RISC_OSLib.kernel.s.k_body, line 768
03A16B5C . : E8CE7FFF : STMIA R14,{R0-R14}^ ; sources.Lib.RISC_OSLib.kernel.s.k_body, line 1360
03A16BCC . K : E94B2000 : STMDB R11,{R13}^ ; sources.Lib.RISC_OSLib.kernel.s.k_body, line 1396
03B49140 .@M : E94D4000 : STMDB R13,{R14}^ ; sources.Printing.Printers.Modules.PDModules.s.PDriverDP.Private, line 154
RISC OS 3.70 binary searches, parallel port timeout problem (HP printers)
-------------------------------------------------------------------------
03984B40 . : E3A02014 : MOV R2,#&14 ;sources.OS_Core.HWSupport.Parallel.s.IOEB, line 381
*pdiff
usage: patchdiff <4M ROM 1> <4M ROM 2>
*pdiff roms.rom370 roms.patches2.rom37patch
{(uint32 *)0x03803a10, 0xe8ce7fff, 0xea004c9a},
{(uint32 *)0x0381351c, 0xe1a00000, 0xe8a01ffe},
{(uint32 *)0x03813520, 0xe8c07ffe, 0xe8c06000},
{(uint32 *)0x03813524, 0xe1a00000, 0xe2400030},
{(uint32 *)0x038138a0, 0x08c07f00, 0x0a000cfe},
{(uint32 *)0x038162c0, 0x08c27f00, 0x0a00027e},
{(uint32 *)0x038162ec, 0xe8cdff00, 0xea00027b},
{(uint32 *)0x03816c80, 0x00000000, 0xe8ae1fff},
{(uint32 *)0x03816c84, 0x00000000, 0xe8ce6000},
{(uint32 *)0x03816c88, 0x00000000, 0xe1a00000},
{(uint32 *)0x03816c8c, 0x00000000, 0xe24ee034},
{(uint32 *)0x03816c90, 0x00000000, 0xe3a0cf4f},
{(uint32 *)0x03816c94, 0x00000000, 0xe89c9000},
{(uint32 *)0x03816ca0, 0x00000000, 0xe8a01f00},
{(uint32 *)0x03816ca4, 0x00000000, 0xe8c06000},
{(uint32 *)0x03816ca8, 0x00000000, 0xe2400014},
{(uint32 *)0x03816cac, 0x00000000, 0xeafff30c},
{(uint32 *)0x03816cc0, 0x00000000, 0xe8a21f00},
{(uint32 *)0x03816cc4, 0x00000000, 0xe8c26000},
{(uint32 *)0x03816cc8, 0x00000000, 0xe2422014},
{(uint32 *)0x03816ccc, 0x00000000, 0xeafffd82},
{(uint32 *)0x03816ce0, 0x00000000, 0xe8ad1f00},
{(uint32 *)0x03816ce4, 0x00000000, 0xe8cd6000},
{(uint32 *)0x03816ce8, 0x00000000, 0xe1a00000},
{(uint32 *)0x03816cec, 0x00000000, 0xe58df008},
{(uint32 *)0x03816cf0, 0x00000000, 0xe24dd014},
{(uint32 *)0x03816cf4, 0x00000000, 0xeafffd7d},
{(uint32 *)0x03816d00, 0x00000000, 0xe8a203c0},
{(uint32 *)0x03816d04, 0x00000000, 0xe8c26000},
{(uint32 *)0x03816d08, 0x00000000, 0xe2422010},
{(uint32 *)0x03816d0c, 0x00000000, 0xea007914},
{(uint32 *)0x03835160, 0xe8c263c0, 0xeaff86e6},
{(uint32 *)0x0396a308, 0xe1a00000, 0xe8ad1fff},
{(uint32 *)0x0396a30c, 0xe8cd7fff, 0xe8cd6000},
{(uint32 *)0x0396a314, 0xe1a00000, 0xe24dd034},
{(uint32 *)0x0396ae9c, 0xe1a00000, 0xe8ad1fff},
{(uint32 *)0x0396aea0, 0xe8cd7fff, 0xe8cd6000},
{(uint32 *)0x0396aea8, 0xe1a00000, 0xe24dd034},
{(uint32 *)0x03984b40, 0xe3a02014, 0xe3a02028},
{(uint32 *)0x039e8680, 0xe1a00000, 0xe8bd4000},
{(uint32 *)0x039e8684, 0xe8bd4000, 0xe8ae1fff},
{(uint32 *)0x039e8688, 0xe1a00000, 0xe8ce6000},
{(uint32 *)0x039e8690, 0xe8ce7fff, 0xe24ee034},
{(uint32 *)0x03a165d4, 0xe1a00000, 0xe9ae1ffe},
{(uint32 *)0x03a165d8, 0xe9ce7ffe, 0xe9ce6000},
{(uint32 *)0x03a165e0, 0xe1a00000, 0xe24ee030},
{(uint32 *)0x03a16b54, 0xe1a00000, 0xe8ae1fff},
{(uint32 *)0x03a16b58, 0xe1a00000, 0xe8ce6000},
{(uint32 *)0x03a16b5c, 0xe8ce7fff, 0xe1a0c000},
{(uint32 *)0x03a16b60, 0xe1a0c000, 0xe24ee034},
*
\ No newline at end of file
/* Copyright 1997 Acorn Computers Ltd
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* debug.h */
extern void dbtrace_patchhits(int *romsection,int *romlpage,int *rompage);
extern void dbtrace_DApages(int DAN, uint32 DAbase, int DAsize);
/* Copyright 1997 Acorn Computers Ltd
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* defs.h */
#define Debug 0
#define ReallyDoRemap 1
/* exit code on error */
#define ErrorReturnCode 257
/* Caution! these defs are valid for RISC OS 3.60, 3.70, 3.71. Make
sure valid for all ROM versions supported by given release of ROMPatch.
Note that only 4Mb ROMs currently supported. */
#define CAMstart 0x1e02000 /* soft CAM */
#define PageFlags_Unavailable 0x2000 /* flag bit in CAM PPL word */
#define L1PT 0x2c0c000 /* MMU level 1 page table */
#define ROMstart 0x3800000
#define ROMphysstart 0x0
#define ROMsize 0x400000 /* code assumes 4Mb in various places */
#define ROMsections (ROMsize >> 20) /* 1M MMU sections */
#define ROMlpages (ROMsize >> 16) /* 64k MMU large pages */
#define ROMpages (ROMsize >> 12) /* 4k MMU (small) pages */
typedef unsigned char uint8;
typedef unsigned int uint32;
typedef struct
{
uint32 logaddr;
uint32 PPL; /* 'page protection level' - protection and flags */
} camentry_t;
/* for logical to physical address translation, via OS_Memory */
typedef struct