GitLab

Test/testbed.c: Remove the special case for MAR/MRA now that Debugger supports these. Don't leak raw on exit, found by cppcheck static analysis.
main.c: Don't leak prog on exit, found by cppcheck static analysis.
The apparent memory leaks are slightly academic since these are both applications and would be reclaimed on exit.

Tested with all 256M 'EQ' and 256M 'NV' condition codes, only expected differences remain such as use of hex.v.dec for small constants.
Tagged as Debugger-2_02-1 since Debugger itself is unchanged.

Detail:
  actions/ARMv8FP_AArch32, Makefile - Add disasembly for the ARMv8 VFP/NEON instructions
  actions/ARMv7_ASIMD, actions/ARMv7_VFP - Fix incorrect disassembly of VCLS, VMOVN, VRSUBHN, VFNMA, VFNMS
  c/util - Add disassembly for MVFR2 register
  s/ARM - Tweak coprocessor instruction decoding logic; ARMv8 uses some of the CDP2 instructions for VFP/NEON
  cache/vfp - Updated decgen cache file
  Test/c/testbed - Improve fopen/system error checking. Add some more rules to deal with (expected) differences between Debugger/dis2 and decaof.
Admin:
  Tested on Raspberry Pi 3
  Disassembly for new instructions (+ some nearby values) checked against BASIC 1.74 + decaof 5.18
  Requires Library-1_92


Version 2.02. Tagged as 'Debugger-2_02'

Detail:
  c/ExceptionDump - Disable unused ExcLooksLikePSR() function. Fix DescribeBlocks() printing the wrong indices for OS_Memory 16 items. Make AnnotateAll() attempt to unwind the ABT/UND stack if the abort came from that mode. Fix some cases where empty lines used for formatting were missing.
  Resources/UK/Messages, Resources/Germany/Messages, s/ExceptionDump, h/exc - Add message tokens X25 & X26 for the ABT & UND stack headers.
Admin:
  Tested on BB-xM
  German messages in need of translation


Version 2.01. Tagged as 'Debugger-2_01'

It just gives a bad SWI error since VFPSupport is missing. In practice this is IOMD and Tungsten platforms, at least in the absence of a VFPEmulator.

Version 2.00. Tagged as 'Debugger-2_00'

We don't need to invent a pre-UAL variant of HVC, since BASIC accepts HVC with or without the #.
Replace made up HVI with HVC.

Version 1.99. Tagged as 'Debugger-1_99'

Cache file update, take two. First attempt seemed to be invalid (bug when restarting tree generation?)

Version 1.98. Retagged as 'Debugger-1_98'

Submit new decgen cache file; addition of ARMv8 encodings invalidated the old one. Should result in quicker build times.

Version 1.98. Retagged as 'Debugger-1_98'

Opcodes for CRC32/HLT/SEVL/LDA/STL/LDAEX/STLEX and DMB/DSB options.
Makefile:
  Add ARMv8_AArch32 actions and encodings to dis2.
actions/ARMv7,dis2.h:
  Extend the DMS/DSB decoding to warn about ARMv8 specific ones (previously undefined)
ARM.s/ARMv6.s:
  Slot in decode.
CGlue.s/Debugger.s/Messages
  New token for "ARMv8 or later" warnings.

Tested by brute force all 256M instructions in NV space and 256M conditionals, comparing the output against dis2.
Currently missing the new VFP and SIMD opcodes.

Version 1.98. Tagged as 'Debugger-1_98'

Three instructions, MIA/MAR/MRA, 14 years late.

Version 1.97. Tagged as 'Debugger-1_97'

Reinstate the check that an immediate value that doesn't use the preferred encoding is disassembled to #value,ror such that reassembling it would give you back the original op code.
Tested with a handful of values, plus inspected all duplicates possible in Excel.

Version 1.96. Tagged as 'Debugger-1_96'

Move the disassembler bits out of the main debugger module.
Built, but not tested.

Version 1.95. Not tagged

Module_Title->Module_TitleStr from Kernel-5_54.

Version 1.95. Tagged as 'Debugger-1_95'

ARMv6.s
  Add missing conditionals on DBG.
  Add ERET (v7VE).
  Add MRS/MSR banked (v7VE), and its funky encoding of the banked register.
  Check bit 22 of SRS/RFE properly, otherwise some undefined instructions get wrongly decoded as SRS/RFE.
CGlue.s
  Use prefix 'A' for arch warnings, so they can be kept together in the messages file.
Debugger.s:
  Around line 990, refactor up front decoding to pick out NV instruction space like the ARM ARM says to do. This makes subsequent decoding much simpler to follow, and removes lots of backdoor checks on bits 28-31 scattered later on in the decode - fixes problem with CPS #mode being wrong when bit 4 set.
  Add HVI (v7MP). Note this is a made up pre-UAL form of HVC (cf. SWI->SVC, SMI->SMC) for now.
  Add PLDW (v7VE).
  Put back flags preservation on Conditions routine, otherwise TestStr preserves flags if no conditions are wanted, but doesn't if they are - was causing some of the Saturates family to be misclassified as undefined.
Test/V6V7tests
  Add samples of each of the extra instructions.
Resources/UK/Messages, Resources/Germany/Messages
  Messages files updated.
Tested with 'testbed' over the 256M EQ condition code, plus 256M NV condition code, with no unexplained mismatches.

Version 1.94. Tagged as 'Debugger-1_94'

  Line 332: Fix typo in R13_hyp table entry (was R12)
  Line 158: A missing comma meant the arch warning table was one entry too short, so any XScale media instructions would cause a NULL pointer access
actions/ARMv7
  Add missing pre-UAL forms of LDRHT LDRSBT LDRSHT STRHT, assuming they take the form [LD|ST]RccSUFFIX
  Fix decoding of banked MRS/MSR SYSm field, this is defined as m:m1, so m needs shifting up more
  Fix opcode for banked MSR, copy paste fumble
Tested using 'testbed', not tagged.

Detail:
  c/exc - The error message was being shoved into a 64 byte buffer, causing truncation. Rather than making the buffer bigger (trying to keep stack usage to a minimum), bypass the buffer and write the message straight to the output. Also add an extra newline at the end of DescribeBlocks so that the output doesn't run directly into the annotated R15/R14 that are output by AnnotateAll.
  Resources/Germany/Messages, Resources/UK/Messages - Update EXC_MSG_ERROR (X18) for the above. Remove Debugger$RawFile and Debugger$AnnotatedFile hint text from Debugger$DumpOptions syntax error message - CopyError wasn't causing the magic newline codes to be translated, and the error buffer (aka StringBuffer) is too small for such a long message anyway.
Admin:
  Tested on Raspberry Pi


Version 1.93. Tagged as 'Debugger-1_93'

Detail:
  This set of changes adds support for the following features:
  * A new code system variable, Debugger$DumpOptions, to control whether exception/crash dumps are collected from SeriousErrorV and where they should be output
  * Dump output can be in raw (binary) or annotated (text) form.
  * Annotated form provides detailed annotation of the stack(s), detecting certain constructs such as SWI invocations, IRQsema frames, CMHG veneers, APCS stack frame chains, and most forms of assembler function calls. The output isn't as easy to understand as a proper stack backtrace would be, but the low-level nature allows it to cope with corrupt or partially-overwritten stack frames, and avoids making invasive changes to components in order to make them backtrace-friendly
  * Stack annotation is able to make use of embedded ROM debug symbols (to be supported by romlinker 0.06) and Norcroft-style embedded function names in order to provide function-level loc...

Detail:
  actions/ARMv7_ASIMD - The instruction is VSRI, but the disassembly was stating VRSI. Fix.
Admin:
  Untested
  Issue reported by Fred Graute:
  https://www.riscosopen.org/forum/forums/4/topics/3956


Version 1.91. Tagged as 'Debugger-1_91'

Largely inspired/ripped off from the DebugTools module, but using OS_DynamicArea 20 for the bulk of area searching. The address to lookup goes through the usual parser for Debugger commands so can be a hex address/register/implied exception PC if no arguments given.
Removed limited lookup from *ShowRegs command; this wasn't especially useful being hardwired to PC since only data aborts have a valid PC, normally the other registers are more interesting.
Fix miscapitalisation of ShowVFPRegs syntax (presumably to avoid it using Token0) by adding a DictTokens directive, since the syntax is used by code in the module which doesn't work with Token0.
Split German messages out into CmdHelp/Messages.

Tested in an IOMD ROM build with various edge cases.

Version 1.90. Tagged as 'Debugger-1_90'

Detail:
  s/Debugger - Fix some broken logic in *ShowVFPRegs that was causing the FPSCR vector length fields to be reported incorrectly if vector stride was enabled
Admin:
  Tested on Raspberry Pi


Version 1.89. Tagged as 'Debugger-1_89'

Detail:
  *Showregs now indicated module name and offset if address is
  in a module
Admin:
  (highlight level of testing that has taken place)
  (bugfix number if appropriate)


Version 1.88. Tagged as 'Debugger-1_88'

Detail:
  s/CodeVar - Escape some dollars contained in strings to avoid warnings from objasm
Admin:
  Resulting binary unchanged


Version 1.87. Retagged as 'Debugger-1_87'

Update for BuildSys-6_60. No need to force things in ModuleLibs to blank now.

Version 1.87. Tagged as 'Debugger-1_87'

Detail:
  This adds support for the *ShowVFPRegs command, which is basically VFP equivalent of *ShowFPRegs. However unlike *ShowFPRegs it allows for any arbitrary VFP context to be viewed, not just the last context that caused an exception:
  *ShowVFPRegs [E] for showing the exception context
  *ShowVFPRegs A <address> for showing a context at a specific address
  *ShowVFPRegs C for showing the current context
  File changes:
  - HelpSrc, Resources/UK/CmdHelp - Added *ShowVFPRegs help text
  - Resources/Germany/Messages, Resources/UK/Messages - New message tokens for *ShowVFPRegs output
  - s/Debugger - *ShowVFPRegs implementation
  - actions/ARMv7_VFP - VPUSH or VPOP of >16 singleword registers were incorrectly being flagged as unpredictable; it's only the doubleword version which should have that restriction.
Admin:
  Tested on Raspberry Pi
  German messages are in need of translation


Version 1.86. Tagged as 'Debugger-1_86'

Detail:
  This change adds up-to-date VFP & NEON disassembly to the module, by way of a partially machine-generated disassembler written in C.
  It's also possible to build a standalone disassembler utility (dubbed 'dis2') which is 100% C and has support for all ARM instructions (including some obscure stuff the assembler disassembler currently lacks, e.g. XScale DSP instructions). One day this may completely replace the assembler disassembler, but at the moment it's a bit bulky and probably has a few bugs left to squash. The disassembler is also fairly flexible, supporting various output formatting options.

  Main changes:
  - Makefile - Rewritten to switch over to using the CModule makefile fragment instead of AAsmModule, to allow the C code to be included in the component. Also added 'dis2' as an alternative component to build as.
  - Resources/UK/Messages, Resources/Germany/Messages - Updated with new disassembler messages
  - s/Debugger - Add new UseCVFPNEON switch to allow control over whether the module builds with the C VFP/NEON disassembler or the original assembler VFP disassembler
  - s/CGlue - Glue code used with the C disassembler to bridge the gap between the assembler world and the C world
  - actions/* - A set of decgen action files describing what to do for each instruction the new disassembler supports. These are basically just blocks of C code - although they need to match up with the encoding names in Library/Misc/decgen/encodings
  - cache/* - Folder for decgen to cache decision trees in. Building the decision tree for the disassembler is currently a lengthy process, but caching the trees reduces the build time to a fraction of the full time.
  - c/head - Stub C file that decgen prepends to the code it generates
  - c/main - main frontend for the standalone version of the disassembler
  - c/support - Reimplementation of the standard C library functions required for the disassembler. This allows us to avoid a runtime dependency on the shared C library, and also allows us to deal with control-terminated strings from messagetrans where relevant. For convenience this file also has the main entry point that's called from assembler.
  - c/util - Utility code for outputting various forms of instruction, decoding immediate constants, etc.
  - h/dis2 - Header file for the C code
  - Test/c/testbed - Simple C testbed app to allow the output of dis2 to be compared against the Debugger module and decaof
  - !MkDis2,fd7 - Script to allow easy building of the standalone 'dis2' disassembler
  Bugfixes:
  - s/ARMv6 - Change 'ROR#' to 'ROR #' for UXTAB, etc. disassembly. Fix bitfield extract & clear instructions to detect unpredictable/invalid bitfield definitions
  Misc other changes:
  - s/* - Source files updated so s/Debugger contains a list of GETs instead of each source file LNK'ing to the next
Admin:
  Tested in ROM form on BB-xM, and as softload on Iyonix
  German messages are in need of translation
  Requires Library-1_65 and BuildSys-6_34


Version 1.85. Tagged as 'Debugger-1_85'

The debugger had some embryonic ARMv6 knowhow, switched out due to being incomplete.
Enabling and finishing off ARMv6, then adding ARMv6K, ARMv6T2, ARMv6 security extensions, and ARMv7.
That just leaves
 - ARMv7MP (multiprocessor extensions: PLDW)
 - ARMv7VE (virtualisation extensions: ERET, MRS copro, MSR copro)
 - Advanced SIMD (probably worth thinking about)
 - Thumb2 (questionable why Thumb is supported at all as the tools & OS don't use it)
The syntax follows the pre UAL spirit for the new instructions (cf. ADDCCS versus ADDSCC).
Removed binary V6test binary, replaced with more comprehensive v6/v7 source.
Tested softloaded inspecting the output in StrongEd.

Version 1.84. Tagged as 'Debugger-1_84'

Detail:
  s/Debugger - Tweaked a few LDM/STM instructions to fix some objasm 4 warnings. Disabled some 26bit code in 32bit configs to avoid more warnings. Fix BreakClr to work on 32bit systems if the breakpoint address is >=64M.
Admin:
  Tested on rev A2 BB-xM


Version 1.83. Tagged as 'Debugger-1_83'

Detail:
  s/Debugger - Try reading DebuggerSpace location using OS_ReadSysInfo 6 before falling back on legacy address. Compute appropriate MOV PC,DebuggerSpace instruction instead of using hard-coded one.
Admin:
  Tested on rev A2 BB-xM


Version 1.82. Tagged as 'Debugger-1_82'

Detail:
  s/Debugger - Reworked MemoryI_Code:
  * Avoid alignment faults when disassembling Thumb instructions by using LDRH or LDR-and-shift depending on compile-time architecture
  * Split ARM & Thumb disassembly into two seperate paths to (perhaps) increase readability
  * Cleaned up the code so it only reads each memory location once
Admin:
  Tested on rev C2 beagleboard.
  Current thumb disassembler looks like it could do with a bit of an overhaul when full support for the 32bit encodings is added.
  *memoryi code could also be made a bit nicer if we don't mind thumb disassembly failing if attempted on a CPU that can't (reliably) LDRH.


Version 1.81. Tagged as 'Debugger-1_81'

Fix code to be fully aware of 64bit parameter flags, fix accidental alignment exceptions on ARMv6/v7

Detail:
  s/Debugger - All code which calls ReadOneParm, ReadParm, etc. now correctly sets r10 to the correct value depending on whether they want to parse 64bit numbers or not. This was the cause of *InitStore malfunctioning and (presumably) trashing whatever R11 pointed to (bug #232)
  Also fixed MemoryHeader causing an unintentional alignment exception when testing if rotated or unaligned loads are in use. The CP15 registers are now interrogated instead.
Admin:
  Tested on rev C2 beagleoard. *Memory with unaligned addresses no longer aborts, and *InitStore <val> now uses the correct value, and seems to no longer trash memory
  Fixes bug #232


Version 1.80. Tagged as 'Debugger-1_80'

Detail:
  Debugger now handles registering and deregistering its messages file with
  ResourceFS when you build a RAM (standalone) variant. This obsoletes the
  DbgMess module.
Admin:
  Tested briefly

Version 1.79. Tagged as 'Debugger-1_79'

Detail:
  CPU version is no longer specified in the makefile - it's better to inherit
  it from the build environment now that we actually set it appropriately.
Admin:
  Built but not tested. Binary should be unchanged - this only affects the
  warnings generated during assembly.

Version 1.78. Not tagged

Detail:
  * Added knowledge of the ARMv5TEJ / ARMv6 CPSR flags J, GE[3:0], E and A,
    plus Monitor mode
  * *Memory, *Memory H, *MemoryA and *MemoryA H can now access unaligned
    addresses; the header line in unaligned cases adapts depending on whether
    the CPU natively rotates or does unaligned loads
  * Added *Memory D and *MemoryA D for accessing 64-bit words using LDRD / STRD
  * Removed check for 32-bit mode before doing LDRH - this is nonsensial now
    that there are 32-bit builds for IOMD-class machines. I've decided to let
    it attempt LDRH even on platforms where it might not work or might be an
    undefined instruction - this gets us "closer to the metal", and it's not
    like *Memory couldn't already throw exceptions in normal use
  * Removed redundant clauses of a few build options, it was getting
    impractical to maintain the alternate build variants
Admin:
  Tested on rev B7 beagleboard. Requires an updated kernel in order to be
  able to specify 64-bit values on the command line or interactively (but
  even on older kernels you can enter a value less than 2^32 to *MemoryA D)

Version 1.78. Tagged as 'Debugger-1_78'

Modified ASCII display in *Memory etc to read memory using the same access size as the main output. This helps with some hardware registers that only support, say, word-sized accesses. Note that the memory locations are still read a second time for the ASCII display, so it's still not ideal for read-sensitive hardware.

Added some ARMv6 support to disassembly, but this is incomplete and switched
out at the moment.

Version 1.77. Tagged as 'Debugger-1_77'

Detail:
  * Added 'H' flag to *Memory and *MemoryA to allow half-word memory accesses.
    On 26-bit machines, this is emulated using 32-bit reads and read-modify-
    writes; on 32-bit machines, LDRH and STRH are used. Address header in
    *Memory byte mode changed to be only one digit per byte for consistency
    with word and half-word modes. *MemoryA H in interactive mode gives a
    Thumb disassembly.
  * STM Rn!,{reg_list_including_Rn} is actually allowed, provided Rn is the
    lowest register in the list. Warning code adjusted accordingly.
Admin:
  Tested on Risc PC and Tungsten.

Version 1.76. Tagged as 'Debugger-1_76'

Detail:
  * Added Q bit to *ShowRegs
  * Added FMSRR, FMRRS, FMDRR and FMRRD to VFP support
  * Shortened lots of VFP literals by treating common "F" prefix separately
  * Cirrus DSP support (switched out)
  * Piccolo support (not even linked in)
  * ARM/Thumb disassembly test programs added
  * Bugfix: code variable init code was trashing the flags that indicated
    whether zero page branch table (used for breakpoints in 32-bit mode) needs
    creating
Admin:
  Builds identical binary to 5.00 release, repository changes were build-
  related only.

Version 1.75. Tagged as 'Debugger-1_75'

Detail:
    Build would not build with this version of the module as the last change
to the makefile did not include the line needed to export the Debugger
header. This line has now been added.
    Added an !MkExport to enable testing of the export.
    Converted the existing Mk... obey files to !Mk... files.

Admin:
    Some basic testing.

Version 1.74. Tagged as 'Debugger-1_74'

* Changes to message files to correct syntax errors.
* *MemoryX P works on IOMD-based systems is OS_Memory 13 fails.
* Changed to use ObjAsm and centralised Makefiles.

Version 1.73. Tagged as 'Debugger-1_73'

memory, memorya and memoryi commands support p option, which specifies physical rather than logical addresses only functional with kernel that support OS_Memory 14 and 15

Version 1.72. Not tagged

  * Added the Disassemble$Options system variable.
Detail:
  * MakeMess now does a CDir command (in case you run it before
    running MkRom). MkClean now includes a 'stripdepnd' call.

  * There is a new system (code) variable created on module init
    called Disassemble$Options. This controls (at the moment)
    register naming for disassembly.
Admin:
  Tested on RiscOS 4 and 3.70.

Version 1.72. Tagged as 'Debugger-1_72'