1. 10 May, 2001 1 commit
    • Kevin Bracey's avatar
      * Fixed register clash warnings on SWP. · 80d99af3
      Kevin Bracey authored
      * Changes to message files to correct syntax errors.
      * *MemoryX P works on IOMD-based systems is OS_Memory 13 fails.
      * Changed to use ObjAsm and centralised Makefiles.
      Version 1.73. Tagged as 'Debugger-1_73'
  2. 09 May, 2001 1 commit
  3. 01 May, 2001 1 commit
  4. 30 Apr, 2001 1 commit
    • Steve Revill's avatar
      * Added a couple of tweaks to the MakeMess and MkClean files. · 2a735e83
      Steve Revill authored
        * Added the Disassemble$Options system variable.
        * MakeMess now does a CDir command (in case you run it before
          running MkRom). MkClean now includes a 'stripdepnd' call.
        * There is a new system (code) variable created on module init
          called Disassemble$Options. This controls (at the moment)
          register naming for disassembly.
        Tested on RiscOS 4 and 3.70.
      Version 1.72. Tagged as 'Debugger-1_72'
  5. 18 Apr, 2001 1 commit
  6. 21 Mar, 2001 3 commits
    • Steve Revill's avatar
      Optimisation of SWI stuff. · bde08062
      Steve Revill authored
        Changed wacky immediate format.
        SWI number stuff now uses an internal routine rather than a call
        to SWI OS_ConvertHex...
        When someone disassembles a wacky immediate, it is represented as
        "<OP> Rd,Rn,#&xx,x" rather than the non-standard
        "<OP> Rd,Rn,#&xx,ROR #x" format. This can then be assembled and
        conforms to ARM's standards.
        Tested on RiscPC
        My editor blew-up in the middle of srccommit on Debugger-1_69 so
        don't use that version!
      Version 1.70. Tagged as 'Debugger-1_70'
    • Steve Revill's avatar
      Optimisation of SWI stuff. · 1a5cd5a5
      Steve Revill authored
        Changed wacky immediate format.
        SWI number stuff now uses an internal routine rather than a call
      Version 1.69. Tagged as 'Debugger-1_69'
    • Steve Revill's avatar
      Modified SWI number output. · 3ab7e167
      Steve Revill authored
        SWI number stuff also implemented in Thumb mode.
        Unknown SWIs were dissasembled as an 8 nibble hexadecimal number.
        This has been reduced to a six nibble number (as the top byte is
        always zero).
        The unknown SWI disassembled as a number stuff has also been added
        to Thumb mode disassembly. Only two nibbles are displayed in this
        Tested on a RiscPC.
      Version 1.68. Tagged as 'Debugger-1_68'
  7. 15 Feb, 2001 1 commit
  8. 14 Feb, 2001 1 commit
    • Steve Revill's avatar
      Fixed SWI number disassembly. · d626d137
      Steve Revill authored
        The routine was returning the length of the disassembled instruction
        *including* the terminator. Changed to exclude it as the others do
        Tested on RiscPC
      Version 1.66. Tagged as 'Debugger-1_66'
  9. 08 Feb, 2001 1 commit
  10. 31 Jan, 2001 1 commit
  11. 30 Jan, 2001 1 commit
    • Steve Revill's avatar
      Fixed ADR and modified SWI disassembly. · 9371049f
      Steve Revill authored
        ADDS Rd,PC,#.. and SUBS Rd,PC,#.. were being incorrectly disassembled
        as ADR pseudo-instructions. Fixed.
        Unknown SWIs (such as OS_Undefined and User) are disassembled in the
        form 'SWI &<num>' so that you can re-assemble the code (and it makes
        more sense if you don't have a module loaded which defined that SWI).
        Tested on RiscPC
        I also added some notes on ARM v5TE to the Doc directory. May be of
        some use when adding compatibility for that to Debugger.
      Version 1.63. Tagged as 'Debugger-1_63'
  12. 08 Sep, 2000 1 commit
    • Kevin Bracey's avatar
      * Disassembly of VFP instruction set added. · 9f3e2d5e
      Kevin Bracey authored
      * Changed invalid instruction to &E7FFFFFF (as per ARM
        recommendation that &E7FxxxFx should be used)
      * Branch disassembly changed - when running on a
        26-bit systems, branch instructions in the lower
        64M will be wrapped within 64M, but branches
        above 64M will not.
      * PC-relative LDRH family instructions calculated
        target address incorrectly.
      Version 1.62. Tagged as 'Debugger-1_62'
  13. 11 Jul, 2000 1 commit
  14. 02 May, 2000 1 commit
    • Kevin Bracey's avatar
      * 32-bit compatibility added. · 8320aaab
      Kevin Bracey authored
      * New *ShowFPRegs command.
      * Added ARMv5 instructions (BLX, CLZ, BKPT, CDP2 et al)
      * Handling of instruction extension space adjusted as per ARMv4.
      * Fixed some Thumb instructions.
      * Added "info" form of LDC and STC.
      * NV condition code is now undefined, except for the new instructions using
      Version 1.60. Tagged as 'Debugger-1_60'
  15. 20 Apr, 1999 1 commit
  16. 19 Apr, 1999 1 commit
  17. 21 Sep, 1998 3 commits
  18. 09 May, 1997 2 commits
  19. 21 Jan, 1997 1 commit
  20. 21 Nov, 1996 1 commit
  21. 05 Nov, 1996 1 commit