GitLab

Detail:
  CPU version is no longer specified in the makefile - it's better to inherit
  it from the build environment now that we actually set it appropriately.
Admin:
  Built but not tested. Binary should be unchanged - this only affects the
  warnings generated during assembly.

Version 1.78. Not tagged

Detail:
  * Added knowledge of the ARMv5TEJ / ARMv6 CPSR flags J, GE[3:0], E and A,
    plus Monitor mode
  * *Memory, *Memory H, *MemoryA and *MemoryA H can now access unaligned
    addresses; the header line in unaligned cases adapts depending on whether
    the CPU natively rotates or does unaligned loads
  * Added *Memory D and *MemoryA D for accessing 64-bit words using LDRD / STRD
  * Removed check for 32-bit mode before doing LDRH - this is nonsensial now
    that there are 32-bit builds for IOMD-class machines. I've decided to let
    it attempt LDRH even on platforms where it might not work or might be an
    undefined instruction - this gets us "closer to the metal", and it's not
    like *Memory couldn't already throw exceptions in normal use
  * Removed redundant clauses of a few build options, it was getting
    impractical to maintain the alternate build variants
Admin:
  Tested on rev B7 beagleboard. Requires an updated kernel in order to be
  able to specify 64-bit values on the command line or interactively (but
  even on older kernels you can enter a value less than 2^32 to *MemoryA D)

Version 1.78. Tagged as 'Debugger-1_78'

Modified ASCII display in *Memory etc to read memory using the same access size as the main output. This helps with some hardware registers that only support, say, word-sized accesses. Note that the memory locations are still read a second time for the ASCII display, so it's still not ideal for read-sensitive hardware.

Added some ARMv6 support to disassembly, but this is incomplete and switched
out at the moment.

Version 1.77. Tagged as 'Debugger-1_77'

Detail:
  * Added 'H' flag to *Memory and *MemoryA to allow half-word memory accesses.
    On 26-bit machines, this is emulated using 32-bit reads and read-modify-
    writes; on 32-bit machines, LDRH and STRH are used. Address header in
    *Memory byte mode changed to be only one digit per byte for consistency
    with word and half-word modes. *MemoryA H in interactive mode gives a
    Thumb disassembly.
  * STM Rn!,{reg_list_including_Rn} is actually allowed, provided Rn is the
    lowest register in the list. Warning code adjusted accordingly.
Admin:
  Tested on Risc PC and Tungsten.

Version 1.76. Tagged as 'Debugger-1_76'

Detail:
  * Added Q bit to *ShowRegs
  * Added FMSRR, FMRRS, FMDRR and FMRRD to VFP support
  * Shortened lots of VFP literals by treating common "F" prefix separately
  * Cirrus DSP support (switched out)
  * Piccolo support (not even linked in)
  * ARM/Thumb disassembly test programs added
  * Bugfix: code variable init code was trashing the flags that indicated
    whether zero page branch table (used for breakpoints in 32-bit mode) needs
    creating
Admin:
  Builds identical binary to 5.00 release, repository changes were build-
  related only.

Version 1.75. Tagged as 'Debugger-1_75'

Detail:
    Build would not build with this version of the module as the last change
to the makefile did not include the line needed to export the Debugger
header. This line has now been added.
    Added an !MkExport to enable testing of the export.
    Converted the existing Mk... obey files to !Mk... files.

Admin:
    Some basic testing.

Version 1.74. Tagged as 'Debugger-1_74'

* Changes to message files to correct syntax errors.
* *MemoryX P works on IOMD-based systems is OS_Memory 13 fails.
* Changed to use ObjAsm and centralised Makefiles.

Version 1.73. Tagged as 'Debugger-1_73'

memory, memorya and memoryi commands support p option, which specifies physical rather than logical addresses only functional with kernel that support OS_Memory 14 and 15

Version 1.72. Not tagged

  * Added the Disassemble$Options system variable.
Detail:
  * MakeMess now does a CDir command (in case you run it before
    running MkRom). MkClean now includes a 'stripdepnd' call.

  * There is a new system (code) variable created on module init
    called Disassemble$Options. This controls (at the moment)
    register naming for disassembly.
Admin:
  Tested on RiscOS 4 and 3.70.

Version 1.72. Tagged as 'Debugger-1_72'

FPEmulators.

Version 1.71. Tagged as 'Debugger-1_71'

  Changed wacky immediate format.
Detail:
  SWI number stuff now uses an internal routine rather than a call
  to SWI OS_ConvertHex...

  When someone disassembles a wacky immediate, it is represented as
  "<OP> Rd,Rn,#&xx,x" rather than the non-standard
  "<OP> Rd,Rn,#&xx,ROR #x" format. This can then be assembled and
  conforms to ARM's standards.
Admin:
  Tested on RiscPC

  My editor blew-up in the middle of srccommit on Debugger-1_69 so
  don't use that version!

Version 1.70. Tagged as 'Debugger-1_70'

  Changed wacky immediate format.
Detail:
  SWI number stuff now uses an internal routine rather than a call
  	 SWISWI

Version 1.69. Tagged as 'Debugger-1_69'

  SWI number stuff also implemented in Thumb mode.
Detail:
  Unknown SWIs were dissasembled as an 8 nibble hexadecimal number.
  This has been reduced to a six nibble number (as the top byte is
  always zero).

  The unknown SWI disassembled as a number stuff has also been added
  to Thumb mode disassembly. Only two nibbles are displayed in this
  mode.
Admin:
  Tested on a RiscPC.

Version 1.68. Tagged as 'Debugger-1_68'

Version 1.67. Tagged as 'Debugger-1_67'

Detail:
  The routine was returning the length of the disassembled instruction
  *including* the terminator. Changed to exclude it as the others do
Admin:
  Tested on RiscPC

Version 1.66. Tagged as 'Debugger-1_66'

* *MemoryI T now disassembles 24 instructions by default rather than 48.

Version 1.65. Tagged as 'Debugger-1_65'

* Fixed disassembly of Thumb high MOV/ADD/CMP instructions.

Version 1.64. Tagged as 'Debugger-1_64'

Detail:
  ADDS Rd,PC,#.. and SUBS Rd,PC,#.. were being incorrectly disassembled
  as ADR pseudo-instructions. Fixed.

  Unknown SWIs (such as OS_Undefined and User) are disassembled in the
  form 'SWI &<num>' so that you can re-assemble the code (and it makes
  more sense if you don't have a module loaded which defined that SWI).
Admin:
  Tested on RiscPC

  I also added some notes on ARM v5TE to the Doc directory. May be of
  some use when adding compatibility for that to Debugger.

Version 1.63. Tagged as 'Debugger-1_63'

* Changed invalid instruction to &E7FFFFFF (as per ARM
  recommendation that &E7FxxxFx should be used)
* Branch disassembly changed - when running on a
  26-bit systems, branch instructions in the lower
  64M will be wrapped within 64M, but branches
  above 64M will not.
* PC-relative LDRH family instructions calculated
  target address incorrectly.

Version 1.62. Tagged as 'Debugger-1_62'

Version 1.61. Tagged as 'Debugger-1_61'

* New *ShowFPRegs command.
* Added ARMv5 instructions (BLX, CLZ, BKPT, CDP2 et al)
* Handling of instruction extension space adjusted as per ARMv4.
* Fixed some Thumb instructions.
* Added "info" form of LDC and STC.
* NV condition code is now undefined, except for the new instructions using
  it.

Version 1.60. Tagged as 'Debugger-1_60'

Version 1.59. Tagged as 'Debugger-1_59'

Version 1.58. Tagged as 'Debugger-1_58'

Version 1.57. Not tagged

Makefile changed to use LocalRes$Path.
Changed to use srccommit.

Version 1.57. Tagged as 'Debugger-1_57'

Thumb disassembly added.