1. 16 Jun, 2009 1 commit
    • Ben Avison's avatar
      Build change · 6cf22fc8
      Ben Avison authored
        CPU version is no longer specified in the makefile - it's better to inherit
        it from the build environment now that we actually set it appropriately.
        Built but not tested. Binary should be unchanged - this only affects the
        warnings generated during assembly.
      Version 1.78. Not tagged
  2. 17 May, 2009 1 commit
    • Ben Avison's avatar
      Changes to make Debugger more useful on ARMv6/v7 · d437ee15
      Ben Avison authored
        * Added knowledge of the ARMv5TEJ / ARMv6 CPSR flags J, GE[3:0], E and A,
          plus Monitor mode
        * *Memory, *Memory H, *MemoryA and *MemoryA H can now access unaligned
          addresses; the header line in unaligned cases adapts depending on whether
          the CPU natively rotates or does unaligned loads
        * Added *Memory D and *MemoryA D for accessing 64-bit words using LDRD / STRD
        * Removed check for 32-bit mode before doing LDRH - this is nonsensial now
          that there are 32-bit builds for IOMD-class machines. I've decided to let
          it attempt LDRH even on platforms where it might not work or might be an
          undefined instruction - this gets us "closer to the metal", and it's not
          like *Memory couldn't already throw exceptions in normal use
        * Removed redundant clauses of a few build options, it was getting
          impractical to maintain the alternate build variants
        Tested on rev B7 beagleboard. Requires an updated kernel in order to be
        able to specify 64-bit values on the command line or interactively (but
        even on older kernels you can enter a value less than 2^32 to *MemoryA D)
      Version 1.78. Tagged as 'Debugger-1_78'
  3. 30 Jul, 2004 1 commit
    • Kevin Bracey's avatar
      Modified ASCII display in *Memory etc to read memory using the same access... · c8f22aa6
      Kevin Bracey authored
      Modified ASCII display in *Memory etc to read memory using the same access size as the main output. This helps with some hardware registers that only support, say, word-sized accesses. Note that the memory locations are still read a second time for the ASCII display, so it's still not ideal for read-sensitive hardware.
      Added some ARMv6 support to disassembly, but this is incomplete and switched
      out at the moment.
      Version 1.77. Tagged as 'Debugger-1_77'
  4. 03 Dec, 2002 2 commits
    • Ben Avison's avatar
      A new feature and a bugfix. · 302102ca
      Ben Avison authored
        * Added 'H' flag to *Memory and *MemoryA to allow half-word memory accesses.
          On 26-bit machines, this is emulated using 32-bit reads and read-modify-
          writes; on 32-bit machines, LDRH and STRH are used. Address header in
          *Memory byte mode changed to be only one digit per byte for consistency
          with word and half-word modes. *MemoryA H in interactive mode gives a
          Thumb disassembly.
        * STM Rn!,{reg_list_including_Rn} is actually allowed, provided Rn is the
          lowest register in the list. Warning code adjusted accordingly.
        Tested on Risc PC and Tungsten.
      Version 1.76. Tagged as 'Debugger-1_76'
    • Ben Avison's avatar
      Merged in Kevin's latest version, as featured in OS release 5.00. · 0af8a6fe
      Ben Avison authored
        * Added Q bit to *ShowRegs
        * Added FMSRR, FMRRS, FMDRR and FMRRD to VFP support
        * Shortened lots of VFP literals by treating common "F" prefix separately
        * Cirrus DSP support (switched out)
        * Piccolo support (not even linked in)
        * ARM/Thumb disassembly test programs added
        * Bugfix: code variable init code was trashing the flags that indicated
          whether zero page branch table (used for breakpoints in 32-bit mode) needs
        Builds identical binary to 5.00 release, repository changes were build-
        related only.
      Version 1.75. Tagged as 'Debugger-1_75'
  5. 01 Jun, 2001 1 commit
    • David Cotton's avatar
      Header exports now work. · 814317cd
      David Cotton authored
          Build would not build with this version of the module as the last change
      to the makefile did not include the line needed to export the Debugger
      header. This line has now been added.
          Added an !MkExport to enable testing of the export.
          Converted the existing Mk... obey files to !Mk... files.
          Some basic testing.
      Version 1.74. Tagged as 'Debugger-1_74'
  6. 10 May, 2001 1 commit
    • Kevin Bracey's avatar
      * Fixed register clash warnings on SWP. · 80d99af3
      Kevin Bracey authored
      * Changes to message files to correct syntax errors.
      * *MemoryX P works on IOMD-based systems is OS_Memory 13 fails.
      * Changed to use ObjAsm and centralised Makefiles.
      Version 1.73. Tagged as 'Debugger-1_73'
  7. 09 May, 2001 1 commit
  8. 01 May, 2001 1 commit
  9. 30 Apr, 2001 1 commit
    • Steve Revill's avatar
      * Added a couple of tweaks to the MakeMess and MkClean files. · 2a735e83
      Steve Revill authored
        * Added the Disassemble$Options system variable.
        * MakeMess now does a CDir command (in case you run it before
          running MkRom). MkClean now includes a 'stripdepnd' call.
        * There is a new system (code) variable created on module init
          called Disassemble$Options. This controls (at the moment)
          register naming for disassembly.
        Tested on RiscOS 4 and 3.70.
      Version 1.72. Tagged as 'Debugger-1_72'
  10. 18 Apr, 2001 1 commit
  11. 21 Mar, 2001 3 commits
    • Steve Revill's avatar
      Optimisation of SWI stuff. · bde08062
      Steve Revill authored
        Changed wacky immediate format.
        SWI number stuff now uses an internal routine rather than a call
        to SWI OS_ConvertHex...
        When someone disassembles a wacky immediate, it is represented as
        "<OP> Rd,Rn,#&xx,x" rather than the non-standard
        "<OP> Rd,Rn,#&xx,ROR #x" format. This can then be assembled and
        conforms to ARM's standards.
        Tested on RiscPC
        My editor blew-up in the middle of srccommit on Debugger-1_69 so
        don't use that version!
      Version 1.70. Tagged as 'Debugger-1_70'
    • Steve Revill's avatar
      Optimisation of SWI stuff. · 1a5cd5a5
      Steve Revill authored
        Changed wacky immediate format.
        SWI number stuff now uses an internal routine rather than a call
      Version 1.69. Tagged as 'Debugger-1_69'
    • Steve Revill's avatar
      Modified SWI number output. · 3ab7e167
      Steve Revill authored
        SWI number stuff also implemented in Thumb mode.
        Unknown SWIs were dissasembled as an 8 nibble hexadecimal number.
        This has been reduced to a six nibble number (as the top byte is
        always zero).
        The unknown SWI disassembled as a number stuff has also been added
        to Thumb mode disassembly. Only two nibbles are displayed in this
        Tested on a RiscPC.
      Version 1.68. Tagged as 'Debugger-1_68'
  12. 15 Feb, 2001 1 commit
  13. 14 Feb, 2001 1 commit
    • Steve Revill's avatar
      Fixed SWI number disassembly. · d626d137
      Steve Revill authored
        The routine was returning the length of the disassembled instruction
        *including* the terminator. Changed to exclude it as the others do
        Tested on RiscPC
      Version 1.66. Tagged as 'Debugger-1_66'
  14. 08 Feb, 2001 1 commit
  15. 31 Jan, 2001 1 commit
  16. 30 Jan, 2001 1 commit
    • Steve Revill's avatar
      Fixed ADR and modified SWI disassembly. · 9371049f
      Steve Revill authored
        ADDS Rd,PC,#.. and SUBS Rd,PC,#.. were being incorrectly disassembled
        as ADR pseudo-instructions. Fixed.
        Unknown SWIs (such as OS_Undefined and User) are disassembled in the
        form 'SWI &<num>' so that you can re-assemble the code (and it makes
        more sense if you don't have a module loaded which defined that SWI).
        Tested on RiscPC
        I also added some notes on ARM v5TE to the Doc directory. May be of
        some use when adding compatibility for that to Debugger.
      Version 1.63. Tagged as 'Debugger-1_63'
  17. 08 Sep, 2000 1 commit
    • Kevin Bracey's avatar
      * Disassembly of VFP instruction set added. · 9f3e2d5e
      Kevin Bracey authored
      * Changed invalid instruction to &E7FFFFFF (as per ARM
        recommendation that &E7FxxxFx should be used)
      * Branch disassembly changed - when running on a
        26-bit systems, branch instructions in the lower
        64M will be wrapped within 64M, but branches
        above 64M will not.
      * PC-relative LDRH family instructions calculated
        target address incorrectly.
      Version 1.62. Tagged as 'Debugger-1_62'
  18. 11 Jul, 2000 1 commit
  19. 02 May, 2000 1 commit
    • Kevin Bracey's avatar
      * 32-bit compatibility added. · 8320aaab
      Kevin Bracey authored
      * New *ShowFPRegs command.
      * Added ARMv5 instructions (BLX, CLZ, BKPT, CDP2 et al)
      * Handling of instruction extension space adjusted as per ARMv4.
      * Fixed some Thumb instructions.
      * Added "info" form of LDC and STC.
      * NV condition code is now undefined, except for the new instructions using
      Version 1.60. Tagged as 'Debugger-1_60'
  20. 20 Apr, 1999 1 commit
  21. 19 Apr, 1999 1 commit
  22. 21 Sep, 1998 3 commits
  23. 09 May, 1997 2 commits
  24. 21 Jan, 1997 1 commit
  25. 21 Nov, 1996 1 commit
  26. 05 Nov, 1996 1 commit