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memory, memorya and memoryi commands support p option, which specifies physical rather than logical addresses only functional with kernel that support OS_Memory 14 and 15

Version 1.72. Not tagged

  * Added the Disassemble$Options system variable.
Detail:
  * MakeMess now does a CDir command (in case you run it before
    running MkRom). MkClean now includes a 'stripdepnd' call.

  * There is a new system (code) variable created on module init
    called Disassemble$Options. This controls (at the moment)
    register naming for disassembly.
Admin:
  Tested on RiscOS 4 and 3.70.

Version 1.72. Tagged as 'Debugger-1_72'

FPEmulators.

Version 1.71. Tagged as 'Debugger-1_71'

  Changed wacky immediate format.
Detail:
  SWI number stuff now uses an internal routine rather than a call
  to SWI OS_ConvertHex...

  When someone disassembles a wacky immediate, it is represented as
  "<OP> Rd,Rn,#&xx,x" rather than the non-standard
  "<OP> Rd,Rn,#&xx,ROR #x" format. This can then be assembled and
  conforms to ARM's standards.
Admin:
  Tested on RiscPC

  My editor blew-up in the middle of srccommit on Debugger-1_69 so
  don't use that version!

Version 1.70. Tagged as 'Debugger-1_70'

  Changed wacky immediate format.
Detail:
  SWI number stuff now uses an internal routine rather than a call
  	 SWISWI

Version 1.69. Tagged as 'Debugger-1_69'

  SWI number stuff also implemented in Thumb mode.
Detail:
  Unknown SWIs were dissasembled as an 8 nibble hexadecimal number.
  This has been reduced to a six nibble number (as the top byte is
  always zero).

  The unknown SWI disassembled as a number stuff has also been added
  to Thumb mode disassembly. Only two nibbles are displayed in this
  mode.
Admin:
  Tested on a RiscPC.

Version 1.68. Tagged as 'Debugger-1_68'

Version 1.67. Tagged as 'Debugger-1_67'

Detail:
  The routine was returning the length of the disassembled instruction
  *including* the terminator. Changed to exclude it as the others do
Admin:
  Tested on RiscPC

Version 1.66. Tagged as 'Debugger-1_66'

* *MemoryI T now disassembles 24 instructions by default rather than 48.

Version 1.65. Tagged as 'Debugger-1_65'

* Fixed disassembly of Thumb high MOV/ADD/CMP instructions.

Version 1.64. Tagged as 'Debugger-1_64'

Detail:
  ADDS Rd,PC,#.. and SUBS Rd,PC,#.. were being incorrectly disassembled
  as ADR pseudo-instructions. Fixed.

  Unknown SWIs (such as OS_Undefined and User) are disassembled in the
  form 'SWI &<num>' so that you can re-assemble the code (and it makes
  more sense if you don't have a module loaded which defined that SWI).
Admin:
  Tested on RiscPC

  I also added some notes on ARM v5TE to the Doc directory. May be of
  some use when adding compatibility for that to Debugger.

Version 1.63. Tagged as 'Debugger-1_63'

* Changed invalid instruction to &E7FFFFFF (as per ARM
  recommendation that &E7FxxxFx should be used)
* Branch disassembly changed - when running on a
  26-bit systems, branch instructions in the lower
  64M will be wrapped within 64M, but branches
  above 64M will not.
* PC-relative LDRH family instructions calculated
  target address incorrectly.

Version 1.62. Tagged as 'Debugger-1_62'

Version 1.61. Tagged as 'Debugger-1_61'

* New *ShowFPRegs command.
* Added ARMv5 instructions (BLX, CLZ, BKPT, CDP2 et al)
* Handling of instruction extension space adjusted as per ARMv4.
* Fixed some Thumb instructions.
* Added "info" form of LDC and STC.
* NV condition code is now undefined, except for the new instructions using
  it.

Version 1.60. Tagged as 'Debugger-1_60'

Version 1.59. Tagged as 'Debugger-1_59'

Version 1.58. Tagged as 'Debugger-1_58'

Version 1.57. Not tagged

Makefile changed to use LocalRes$Path.
Changed to use srccommit.

Version 1.57. Tagged as 'Debugger-1_57'

Thumb disassembly added.