ARMv6/v7 disassembly accuracy improvements, ARMv7MP ARMv7VE additions
ARMv6.s Add missing conditionals on DBG. Add ERET (v7VE). Add MRS/MSR banked (v7VE), and its funky encoding of the banked register. Check bit 22 of SRS/RFE properly, otherwise some undefined instructions get wrongly decoded as SRS/RFE. CGlue.s Use prefix 'A' for arch warnings, so they can be kept together in the messages file. Debugger.s: Around line 990, refactor up front decoding to pick out NV instruction space like the ARM ARM says to do. This makes subsequent decoding much simpler to follow, and removes lots of backdoor checks on bits 28-31 scattered later on in the decode - fixes problem with CPS #mode being wrong when bit 4 set. Add HVI (v7MP). Note this is a made up pre-UAL form of HVC (cf. SWI->SVC, SMI->SMC) for now. Add PLDW (v7VE). Put back flags preservation on Conditions routine, otherwise TestStr preserves flags if no conditions are wanted, but doesn't if they are - was causing some of the Saturates family to be misclassified as undefined. Test/V6V7tests Add samples of each of the extra instructions. Resources/UK/Messages, Resources/Germany/Messages Messages files updated. Tested with 'testbed' over the 256M EQ condition code, plus 256M NV condition code, with no unexplained mismatches. Version 1.94. Tagged as 'Debugger-1_94'
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