Commit c8be9de2 authored by Robert Sprowson's avatar Robert Sprowson

Split 6k line source file

Move the disassembler bits out of the main debugger module.
Built, but not tested.

Version 1.95. Not tagged
parent 012dae05
......@@ -19,6 +19,18 @@ Debugger RM.
***************************************************************************
; 1.18 SKS Fixed disassembly of #xx,yy operands
; 1.19 SKS Fixed disassembly of LSR #32, ASR #32
; Comment where LDR pc relative comes from
; 1.20 SKS Fixed fp/coproc disassembly, memoryi/memorya parameters
; 1.21 SKS Fixed *debug response wrt ESCape
; 1.22 SKS Fixed memory wrt wrapping at 64M
; ---- Released for Arthur 2.00 ----
; 1.22 TMD 22-Nov-89 Fixed source to assemble again with new headers,
; and with new AAsm which objects to DCD rel.sym.
; (shouldn't affect object file)
Change Log:
===========
......@@ -167,6 +179,15 @@ Fixed access to banked register after LDM forcing user bank.
Version: 1.37 Mon 02-Dec-91 Alan Glover
Fix Bug RP-0512 - give the Debugger some address validation at last!
; Add address validation as below
; &0000000-&1ffffff - Use OS_ValidateAddress
; &2000000-&2ffffff - No checks (always present)
; &3000000-&33fffff - No access (I/O areas)
; &3400000-&3ffffff - Read access only (ROMs)
; (writes=VIDC or MEMC)
; MEMORYA will trap interactive mode going into
; a read-only/no access area too.
---------------------------------------------------------------------------
Version: 1.38 Fri 24-Jan-92 Alan Glover
......@@ -178,6 +199,8 @@ Version: 1.39 Mon 13-Apr-92 Alan Glover
Fix Bug RP-1082 - Revert RP-0512 fix.
; ---- Released for RISC OS 3.10 ----
---------------------------------------------------------------------------
Version: 1.40 Tue 06-Jul-93 Tim Dobson
......@@ -210,6 +233,9 @@ Version: 1.44 Thu 03-Feb-94 Alan Glover
Add a flag to allow a non-international help & syntax version to be built.
Add new ARM6/ARM7DM instructions. Tighten up checking on undefined
instructions.
MRS, MSR, MULL, MLAL and check conformance with FPA10 spec. Tighten up
tests for MUL/MULL/SWP - now insist b7:b4=2_1001
***************************************************************************
MEDUSA - RISC OS 3.50 build
......@@ -251,3 +277,42 @@ Version: 1.45 Fri 28-Oct-94 Steve Cormie
* Added directed comments to Messages file for message tokenisation.
* Moved command help/syntax from Global.Messages to Messages file.
; ---- Released for RISC OS 3.60 ----
; 1.46 WT 07-Feb-96 Made StrongARM compatible (breakpoint code breaks IDcache)
; 1.48 KJB 04-Jun-96 Added ARMv4 instructions (BX, LDR[H|SH|SB], STRH)
; SWP wasn't being disassembled
; CP15 comments amended to ARMv4
; ARM3 warning removed from SWP (after all, MRS,
; MULL etc don't have warnings!)
; ---- Released for RISC OS 3.70 ----
; 1.49 KJB 07-Oct-96 Operation code of MRC, MCR was shown times 2.
; FLT was showing wrong dest reg, with registers
; shown in wrong order.
; WFC etc were showing precision.
; Unknown FP opcodes now shown as normal coprocessor
; operations.
; LDC/STC (and FP derivatives) didn't detect
; post-indexing with no writeback. Now reported as
; undefined instructions.
; UMULLEQS no longer pushes registers into the
; comment field.
; MSR/MRS now specified as described in ARM
; Architecture Reference 4.
; 1.50 KJB 10-Oct-96 Lots of warnings added.
; More FP opcodes tightened up.
; PC-relative load/store with writeback no longer
; shown as simple ADR.
; Thumb disassembly added.
; 1.51 KJB 29-Oct-96 Bugs introduced by 1.49 and 1.50 fixed.
; Warnings added to the LDRH family to match LDC and LDR.
; Warning about StrongARM STM^ bug added.
; Source code tidied up and simplified with macros.
; 1.52 KJB 06-Nov-96 More bug fixes.
; StrongARM warning revised following Digital guidelines.
; 1.53 KJB 11-Nov-96 SWI called checkreg for no apparent reason.
; Stopped Addr26 screwing up Thumb disassembly.
; Set Addr26 to True.
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