Commit 85396cb2 authored by Robert Sprowson's avatar Robert Sprowson

Add the later ARMv8 AArch32 opcodes

ARM have added SETPAN, ESB, TSB, CSDB, PSSBB, SSBB since the earlier ARM ARM that Debugger-1_98 was based on.
ARMv6.s: Decode and show the 6 new instructions
actions/ARMv7,actions/ARMv8_AArch32: C equivalents for dis2
Resources,Debugger.s,CGlue.s,ARM.s,dis2.h: 3 new messages to warn for v8.1 v8.2 v8.4

cache/vfp also updated based on encodings in Library-1_97.

Version 2.03. Tagged as 'Debugger-2_03'
parent 9a09a855
No preview for this file type
......@@ -121,9 +121,9 @@
DCI &F57FF063 ; ISB OSH, as SY but unpredictable
DCI &F57FF000 ; Unallocated, unpredictable
10
PLD %BT10
PLD %BT10
PLD [R1, #-1000]
PLD [R1, R2]
PLD [R1, R2]
DCI &F45FF014 ; Objasm 4.01 bug, this is "PLI %BT10"
PLI [R1, #-1000]
PLI [R1, R2]
......@@ -201,7 +201,7 @@
USAD8 r2, r3, r4
USADA8 r2, r3, r4, r5
USADA8CC r2, r3, r4, r5
; Media extensions
SEL r5, r6, r7
SELCC r5, PC, r7 ; Not PC
......@@ -253,7 +253,7 @@
MRS r5, LR_mon
ERETNE
HVC &1234
; V8 additions
DCI &E1043045 ; CRC32B r3, r4, r5
DCI &11043245 ; CRC32CBNE r3, r4, r5
......@@ -278,4 +278,18 @@
STLEX r0, r1, [r2]
STLEXNE r0, pc, [r2]
; V8.1 addition
DCI &F1100000 ; SETPAN #0
DCI &F1100200 ; SETPAN #1
; V8.2 addition
DCI &E320F010 ; ESB
DCI &2320F010 ; ESBCS unpredictable
; V8.4 additions
DCI &E320F012 ; TSB CSYNC
DCI &E320F014 ; CSDB
DCI &F57FF040 ; SSBB
DCI &F57FF044 ; PSSBB
END
;
; This file is automatically maintained by srccommit, do not edit manually.
; Last processed by srccommit version: 1.1.
;
GBLS Module_MajorVersion
GBLA Module_Version
......@@ -10,14 +9,12 @@
GBLS Module_ApplicationDate
GBLS Module_HelpVersion
GBLS Module_ComponentName
GBLS Module_ComponentPath
Module_MajorVersion SETS "2.02"
Module_Version SETA 202
Module_MajorVersion SETS "2.03"
Module_Version SETA 203
Module_MinorVersion SETS ""
Module_Date SETS "25 Feb 2018"
Module_ApplicationDate SETS "25-Feb-18"
Module_Date SETS "06 Jul 2019"
Module_ApplicationDate SETS "06-Jul-19"
Module_ComponentName SETS "Debugger"
Module_ComponentPath SETS "castle/RiscOS/Sources/Programmer/Debugger"
Module_FullVersion SETS "2.02"
Module_HelpVersion SETS "2.02 (25 Feb 2018)"
Module_FullVersion SETS "2.03"
Module_HelpVersion SETS "2.03 (06 Jul 2019)"
END
/* (2.02)
/* (2.03)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 2.02
#define Module_MajorVersion_CMHG 2.03
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 25 Feb 2018
#define Module_Date_CMHG 06 Jul 2019
#define Module_MajorVersion "2.02"
#define Module_Version 202
#define Module_MajorVersion "2.03"
#define Module_Version 203
#define Module_MinorVersion ""
#define Module_Date "25 Feb 2018"
#define Module_Date "06 Jul 2019"
#define Module_ApplicationDate "25-Feb-18"
#define Module_ApplicationDate "06-Jul-19"
#define Module_ComponentName "Debugger"
#define Module_ComponentPath "castle/RiscOS/Sources/Programmer/Debugger"
#define Module_FullVersion "2.02"
#define Module_HelpVersion "2.02 (25 Feb 2018)"
#define Module_LibraryVersionInfo "2:2"
#define Module_FullVersion "2.03"
#define Module_HelpVersion "2.03 (06 Jul 2019)"
#define Module_LibraryVersionInfo "2:3"
......@@ -357,13 +357,22 @@ DMB_A1(option,nonstandard)
DSB_A1(option,nonstandard)
{
COMMON
ONLY1(ARMv7);
if(!dmb_dsb_opt[option].valid)
warning(JUSTPARAMS,WARN_BAD_DMB_DSB_ISB_OPTION);
/* Special mention OSHLD/NSHLD/ISHLD/LD */
if((option==1)||(option==5)||(option==9)||(option==13))
ONLY1(ARMv8);
sprintf(params->buf,"DSB\t%s",dmb_dsb_opt[option].str);
if((option&0xb)==0)
{
/* PSSBB and SSBB hidden in DSB space */
ONLY1(ARMv8p4);
sprintf(params->buf,"%sSSBB",option?"P":"");
}
else
{
ONLY1(ARMv7);
if(!dmb_dsb_opt[option].valid)
warning(JUSTPARAMS,WARN_BAD_DMB_DSB_ISB_OPTION);
/* Special mention OSHLD/NSHLD/ISHLD/LD */
if((option==1)||(option==5)||(option==9)||(option==13))
ONLY1(ARMv8);
sprintf(params->buf,"DSB\t%s",dmb_dsb_opt[option].str);
}
return;
}
......
......@@ -33,6 +33,33 @@ SEVL_A1(cond,nonstandard)
return;
}
ESB_A1(cond,nonstandard)
{
COMMON
ONLY1(ARMv8p2);
_UNPREDICTABLE(cond!=14);
sprintf(params->buf,"ESB%s",condition(JUSTPARAMS,cond));
return;
}
TSB_A1(cond,nonstandard)
{
COMMON
ONLY1(ARMv8p4);
_UNPREDICTABLE(cond!=14);
sprintf(params->buf,"TSB%s\tCSYNC",condition(JUSTPARAMS,cond));
return;
}
CSDB_A1(cond,nonstandard)
{
COMMON
ONLY1(ARMv8p4);
_UNPREDICTABLE(cond!=14);
sprintf(params->buf,"CSDB%s",condition(JUSTPARAMS,cond));
return;
}
HLT_A1(cond,imm12:imm4,nonstandard)
{
COMMON
......@@ -135,3 +162,11 @@ STL_A1(cond,sz,Rn,Rt,nonstandard)
sprintf(params->buf,"STL%s%s\t%s,[%s]",condition(JUSTPARAMS,cond),(sz==0)?"":(sz==2)?"B":"H",REG(Rt),REG(Rn));
return;
}
SETPAN_A1(I,nonstandard)
{
COMMON
ONLY1(ARMv8p1);
sprintf(params->buf,"SETPAN\t#%d",I);
return;
}
No preview for this file type
......@@ -249,6 +249,9 @@ typedef enum {
FPA,
XScaleDSP,
ARMv8,
ARMv8p1,
ARMv8p2,
ARMv8p4,
ARCH_MAX
} earch;
......
......@@ -2385,6 +2385,9 @@ Silly
= "M49",0 ; Odd base of pair
= "A17",0 ; XScale DSP
= "A18",0 ; ARMv8 or later
= "A19",0 ; ARMv8.1 or later
= "A20",0 ; ARMv8.2 or later
= "A21",0 ; ARMv8.4 or later
ALIGN
......
......@@ -200,6 +200,21 @@ Maintenance_uncond ROUT
B InstructionEnd
is_DSB_DMB_ISB
TSTS r4, #2_111011
BNE %FT10
; arrive here with 1111 0101 0111 1111 1111 0000 0100 0p00
;
; [P]SSBB
TSTS r4, #1:SHL:2
AddChar "P",NE
AddStr Ssbb
[ WarnARMv8
MOV r14, #Mistake_ARMv8p4
STR r14, Mistake
]
BL Tab
B InstructionEnd
10
; arrive here with 1111 0101 0111 1111 1111 0000 01im tttt
;
; <DSB|DMB|ISB> type
......@@ -266,6 +281,7 @@ is_CLREX
UnpredArm
DCB "M65", 0
Ssbb DCB "SSBB", 0
Clrex DCB "CLREX", 0
Typest DCB "ST", 0
Typeld DCB "LD", 0
......@@ -291,8 +307,32 @@ Hints ROUT
]
ANDS r5, r4, #&FF ; Isolate op2
CMPS r5, #2_11110000 ; DBG
BCS %FT10
BCS %FT20
TEQS r5, #&10 ; ESB
TEQNES r5, #&12 ; TSB
TEQNES r5, #&14 ; CSDB
BNE %FT10
CMPS r5, #&12
ADRCC r10, EsbH
ADREQ r10, TsbH
ADRHI r10, CsdbH
[ WarnARMv8
MOVCC r14, #Mistake_ARMv8p2
MOVCS r14, #Mistake_ARMv8p4
STR r14, Mistake
]
AND r8, r4, #2_1111:SHL:28
TEQS r8, #2_1110:SHL:28 ; Note conditional is unpredictable
MOVNE r14, #Mistake_Unpred
STRNE r14, Mistake
BL SaveStringConditions
BL Tab
TEQS r5, #&12
AddStr CsyncH,EQ ; Who cooks up this stuff?
B InstructionEnd
10
CMPS r5, #5
ADR r10, NopH
ADDLS r14, r5, r5, LSL #1 ; x3
......@@ -306,7 +346,7 @@ Hints ROUT
BL SaveStringConditions
BL Tab
B InstructionEnd
10
20
[ WarnARMv7
MOV r14, #Mistake_ARMv7 ; DBG
STR r14, Mistake
......@@ -323,6 +363,11 @@ WfeH DCB "WFE", 0, 0, 0
WfiH DCB "WFI", 0, 0, 0
SevH DCB "SEV", 0, 0, 0
SevlH DCB "SEVL", 0, 0
EsbH DCB "ESB", 0
TsbH DCB "TSB", 0
CsdbH DCB "CSDB", 0
CsyncH DCB "CSYNC", 0
DbgH DCB "DBG", 0
ALIGN
......@@ -699,8 +744,29 @@ ControlExtension_uncond
; arrive here with 1111 0001 xxxx xxxx xxxx xxxx xxxx xxxx
TSTS r4, #2_11111100:SHL:8
TSTEQS r4, #2_1111:SHL:20
BEQ %FT04
BIC r5, r4, #1:SHL:9
BIC r5, r5, #&FF:SHL:24
TEQ r5, #1:SHL:20
BNE Undefined
; arrive here with 1111 0001 0001 0000 0000 00x0 0000 0000
; format is 1111 0001 0001 0000 0000 00i0 0000 0000
;
; SETPAN #i
;
; where i = immediate
[ WarnARMv8
MOV r14, #Mistake_ARMv8p1
STR r14, Mistake
]
AddStr Setpan
BL Tab
AddChar "#"
TestBit 9,"1","0"
B InstructionEnd
04
[ WarnARMv6
MOV r14, #Mistake_ARMv6 ; all instructions here are ARMv6
STR r14, Mistake
......@@ -776,6 +842,7 @@ ControlExtension_uncond
AddChar "E"
B InstructionEnd
Setpan DCB "SETPAN",0
Setend DCB "SETEND",0
ChgSt DCB "CPS",0
ALIGN
......
......@@ -156,5 +156,8 @@ archwarnings
= "M00", 0 ; FPA (impossible with VFP-only build)
= "A17", 0 ; XScaleDSP
= "A18", 0 ; ARMv8
= "A19", 0 ; ARMv8.1
= "A20", 0 ; ARMv8.2
= "A21", 0 ; ARMv8.4
END
......@@ -258,6 +258,9 @@ Mistake_ARMv7MP # 1
Mistake_BaseOdd # 1
Mistake_XScaleDSP # 1
Mistake_ARMv8 # 1
Mistake_ARMv8p1 # 1
Mistake_ARMv8p2 # 1
Mistake_ARMv8p4 # 1
^ -1
Potential_SWICDP # -1
......
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