Commit 3d2718aa authored by Robert Sprowson's avatar Robert Sprowson

Add XScale DSP disassembly

Three instructions, MIA/MAR/MRA, 14 years late.

Version 1.97. Tagged as 'Debugger-1_97'
parent d8cf3817
No preview for this file type
......@@ -11,13 +11,13 @@
GBLS Module_HelpVersion
GBLS Module_ComponentName
GBLS Module_ComponentPath
Module_MajorVersion SETS "1.96"
Module_Version SETA 196
Module_MajorVersion SETS "1.97"
Module_Version SETA 197
Module_MinorVersion SETS ""
Module_Date SETS "24 Jul 2016"
Module_ApplicationDate SETS "24-Jul-16"
Module_Date SETS "11 Nov 2016"
Module_ApplicationDate SETS "11-Nov-16"
Module_ComponentName SETS "Debugger"
Module_ComponentPath SETS "castle/RiscOS/Sources/Programmer/Debugger"
Module_FullVersion SETS "1.96"
Module_HelpVersion SETS "1.96 (24 Jul 2016)"
Module_FullVersion SETS "1.97"
Module_HelpVersion SETS "1.97 (11 Nov 2016)"
END
/* (1.96)
/* (1.97)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 1.96
#define Module_MajorVersion_CMHG 1.97
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 24 Jul 2016
#define Module_Date_CMHG 11 Nov 2016
#define Module_MajorVersion "1.96"
#define Module_Version 196
#define Module_MajorVersion "1.97"
#define Module_Version 197
#define Module_MinorVersion ""
#define Module_Date "24 Jul 2016"
#define Module_Date "11 Nov 2016"
#define Module_ApplicationDate "24-Jul-16"
#define Module_ApplicationDate "11-Nov-16"
#define Module_ComponentName "Debugger"
#define Module_ComponentPath "castle/RiscOS/Sources/Programmer/Debugger"
#define Module_FullVersion "1.96"
#define Module_HelpVersion "1.96 (24 Jul 2016)"
#define Module_LibraryVersionInfo "1:96"
#define Module_FullVersion "1.97"
#define Module_HelpVersion "1.97 (11 Nov 2016)"
#define Module_LibraryVersionInfo "1:97"
......@@ -1789,13 +1789,17 @@ Coprocessor
TEQ r2, #15
BEQ Coprocessor_NotFP
AND r2, r4, #2_1111 :SHL: 8 ; r2 := CP# << 8
ANDS r2, r4, #2_1111 :SHL: 8 ; r2 := CP# << 8
[ XScaleDSP
BEQ XScaleDSPInstruction ; Coprocessor 0
]
TEQS r2, #1 :SHL: 8
BEQ Floating_Point ; [Floating Point coprocessor]
TEQS r2, #2 :SHL: 8
BEQ New_FPA ;new FPA
BEQ New_FPA ; New FPA
TEQS r2, #10 :SHL: 8
TEQNES r2, #11 :SHL: 8
......@@ -1805,7 +1809,7 @@ Coprocessor
CMPS r2, #4 :SHL: 8
BLO Coprocessor_NotFP
CMPS r2, #6 :SHL: 8
BLS CirrusDSPInstruction
BLS CirrusDSPInstruction ; Coprocessor 4-6
]
Coprocessor_NotFP
......@@ -2366,6 +2370,7 @@ Silly
= "A15",0 ; ARMv7VE or later
= "A16",0 ; ARMv7MP or later
= "M49",0 ; Odd base of pair
= "A17",0 ; XScale DSP
ALIGN
......
......@@ -154,6 +154,6 @@ archwarnings
= "A12", 0 ; ASIMDFP
= "A13", 0 ; ASIMDv2FP
= "M00", 0 ; FPA (impossible with VFP-only build)
= "M00", 0 ; XScaleDSP (impossible with VFP-only build)
= "A17", 0 ; XScaleDSP
END
......@@ -598,5 +598,5 @@ ExitSFPR
Pull "r1"
WFS r1 ; restore FPSR
EXIT
LNK s.Thumb
]
END
......@@ -72,6 +72,9 @@ WarnARMv5 SETL {TRUE} ; Indicate ARMv5 or later instructions
GBLL WarnARMv5E
WarnARMv5E SETL {TRUE} ; Indicate ARMv5E or later instructions
GBLL WarnXScaleDSP
WarnXScaleDSP SETL {TRUE} ; Indicate XScale DSP instructions
GBLL WarnARMv6
WarnARMv6 SETL {TRUE} ; Indicate ARMv6 or later instructions
......@@ -91,10 +94,16 @@ WarnARMv7VE SETL {TRUE} ; Indicate ARMv7VE or later instructions
WarnARMv7MP SETL {TRUE} ; Indicate ARMv7MP or later instructions
GBLL Thumbv6
Thumbv6 SETL {TRUE} ; Don't do Thumbv6 yet until complete
Thumbv6 SETL {FALSE} ; Thumb v6 (incomplete)
GBLL CirrusDSP
CirrusDSP SETL {FALSE}
CirrusDSP SETL {FALSE} ; Cirrus' Maverick Crunch (incomplete)
GBLL Piccolo
Piccolo SETL {FALSE} ; ARM's 16 bit DSP (incomplete)
GBLL XScaleDSP
XScaleDSP SETL {TRUE} ; XScale multimedia extensions
GBLL UseCVFPNEON
UseCVFPNEON SETL {TRUE} ; Use the C VFP/NEON disassembler
......@@ -244,6 +253,7 @@ Mistake_ARMv7 # 1
Mistake_ARMv7VE # 1
Mistake_ARMv7MP # 1
Mistake_BaseOdd # 1
Mistake_XScaleDSP # 1
^ -1
Potential_SWICDP # -1
......@@ -3634,6 +3644,9 @@ declareresourcefsfiles
|
GET VFP.s
]
GET CirrusDSP.s
GET Piccolo.s
GET XScaleDSP.s
GET Thumb.s
GET CodeVar.s
GET ExceptionDump.s
......
; Copyright 2016 Castle Technology Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
; File: XScaleDSP.s
; Purpose: Disassembly of the XScale DSP instruction set
[ XScaleDSP
XScaleDSPInstruction
; arrive here with cccc 11oo xxxx xxxx xxxx 0000 xxxx xxxx
; where oo <> 11
[ WarnXScaleDSP
MOV r14, #Mistake_XScaleDSP
STR r14, Mistake
]
AND r2, r4, #&FE:SHL:20 ; 7 bit compare
TEQ r2, #2_11000100:SHL:20
TSTEQ r4, #2_11111000
BEQ XScaleMARMRA
AND r2, r4, #&FF:SHL:20 ; 8 bit compare
TEQ r2, #2_11100010:SHL:20
BNE Undefined
TestBit 4
BEQ Undefined
XScaleMIA ROUT
; arrive here with cccc 1110 0010 xxxx xxxx 0000 xxx1 xxxx
; arrive here with cccc 1110 0010 oooo ssss 0000 aaa1 mmmm
;
; MIA<PH|BB|BT|TB|TT>{cond} acc,Rm,Rs
;
; where cccc = condition
; oooo = Operation
; aaa = Accumulator
; mmmm = Rm
; ssss = Rs
AddStr MiaTAB
ANDS r2, r4, #15:SHL:16 ; opcode_3
BEQ %FT10 ; MIA
TEQ r2, #8:SHL:16
AddChar "P",EQ
AddChar "H",EQ
BEQ %FT10
CMP r2, #12:SHL:16
[ WarnXScaleDSP
MOVCC r14, #Mistake_Unpred
STRCC r14, Mistake ; All other values of opcode_3
]
BCC %FT10
TestBit 17,"T","B"
TestBit 16,"T","B"
10
BL Conditions
BL Tab
MOV r5, r4, LSR #5
BL XScaleAcc
MOV r5, r4
BL Comma_Dis_Register
MOV r5, r4, LSR #12
BL Comma_Dis_Register
ORR r2, r5, r4, LSL #4 ; R's now adjacent
ADD r2, r2, #&11 ; Look for carry out
TST r2, #15
TSTNE r2, #15:SHL:4
MOVEQ r14, #Mistake_R15 ; Either using PC
STREQ r14, Mistake
B InstructionEnd
XScaleMARMRA ROUT
; arrive here with cccc 1100 010x xxxx xxxx 0000 0000 0xxx
; format is cccc 1100 010d hhhh llll 0000 0000 0aaa
;
; MAR{cond} acc,RdLo,RdHi
; MRA{cond} RdLo,RdHi,acc
;
; where cccc = condition
; aaa = Accumulator
; d = Direction
; hhhh = RdHi
; llll = RdLo
TestStr 20,MraTAB,MarTAB,conds
BL Tab
TestBit 20
MOVEQ r5, r4 ; MAR
BLEQ XScaleAcc ; MAR
MOV r5, r4, LSR #12
BLEQ Comma_Dis_Register ; MAR
BLNE Dis_Register ; MRA
MOV r5, r4, LSR #16
BL Comma_Dis_Register
BLNE AddComma
MOVNE r5, r4 ; MRA
BLNE XScaleAcc ; MRA
BEQ %FT10 ; MAR
EOR r2, r4, r4, LSL #4
TST r2, #15:SHL:16
MOVEQ r14, #Mistake_RdLoRdHi ; MRA with RdLo=RdHi
STREQ r14, Mistake
10
ADD r2, r4, #&11:SHL:12 ; Look for carry out
TST r2, #15:SHL:12
TSTNE r2, #15:SHL:16
MOVEQ r14, #Mistake_R15 ; Either using PC
STREQ r14, Mistake
B InstructionEnd
MiaTAB DCB "MIA",0
MraTAB DCB "MRA",0
MarTAB DCB "MAR",0
AccTAB DCB "acc",0
ALIGN
XScaleAcc Entry "r8" ; Preserves flags
AddStr AccTAB
AND r8, r5, #7
BL StoreDecimal
EXIT
]
END
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