Commit 239b1942 authored by Ben Avison's avatar Ben Avison Committed by ROOL

Support large physical addresses

When the 'P' switch is given to *Memory, *MemoryI or *MemoryA, all address
and offset arguments are parsed as 64-bit numbers, and all physical addresses
are displayed as 40-bit numbers. (The truncation from 64 bits is to avoid the
standard width of *Memory output overflowing an 80-character-wide window, and
should be fine in practice because even LPAE is limited to 40-bit addresses.)

There is no facility for constructing physical address from a low-high
register pair on the command line. However, if you know the literal value of
the upper bits of a physical address, you could construct the offset
manually, for example:

  *Memory P r0+100000000 +100

Internally, this means all addresses are passed around as 64-bit numbers. To
limit the amount of register allocation changes required, the values of
pointers are now mostly stored on the stack. Physical address lookups are
done usng OS_Memory 22 on kernels which provide it, falling back to
OS_Memory 14 and then the logical mapping of physical space on early non-HAL
kernels. Because OS_Memory 22 can return errors, there are now many more
code paths that have to handle them.

Other bugs fixed in passing:
* Correct syntax error is printed for malformed *MemoryA commands
* PC and breakpoint markers are not displayed in physical address mode
* Errors reported from OS_WriteC within DisplayCharacters were being corrupted

Requires header export from RiscOS/Sources/Kernel!3 in order to build
(softload versions should still run elsewhere though).
parent 85396cb2
No preview for this file type
......@@ -2485,7 +2485,7 @@ MemoryI_Error
MemoryI_Code Entry "r6-r11"
MemoryI_Code Entry "r6-r11", 8+8
MOV R6,#"T"
BL MemoryCommon
......@@ -2493,24 +2493,40 @@ MemoryI_Code Entry "r6-r11"
ADR r2, MemoryI_Error
MOV r10, #0 ; arguments can only be 32-bit
LDR r10, PhysAddrWrd
TEQ r10, #0
MOVNE r10, #Command_64bitAddr :OR: Command_64bitData
MOV r9, sp
ADD r7, sp, #8
BL GetCommandParms
BLVS CopyErrorR2
LDMIA r9, {r3-r4}
TST r8, #secondparm
ADDEQ r7, r9, r6, LSL #4 ; r7 = r9 + r6 * 24
ADDEQ r7, r7, r6, LSL #3
LDMNEIA r7, {r5,lr}
; Print 24 instructions if no second parm
MOV r5, r6, LSL #4
ADD r5, r5, r6, LSL #3
ADDS r5, r3, r5
ADC lr, r4, #0
TEQ r6, #4
BICEQ r9, r9, #3 ; ensure word aligned
BICEQ r7, r7, #3
BICNE r9, r9, #1 ; ensure halfword aligned
BICNE r7, r7, #1
BICEQ r3, r3, #3 ; ensure word aligned
BICEQ r5, r5, #3
BICNE r3, r3, #1 ; ensure halfword aligned
BICNE r5, r5, #1
TEQS r9, r7 ; If same, ensure we do one word
ADDEQ r7, r7, r6
TEQ r3, r5 ; If same, ensure we do one word
TEQEQ r4, lr
ADDS r5, r5, r6
ADC lr, lr, #0
STMIA r9, {r3-r4}
STMIA r7, {r5,lr}
BL SwapAllBreakpoints
......@@ -2531,6 +2547,7 @@ MemoryI_Code Entry "r6-r11"
MOV r0, r9
BL do_readW
MOV r4, r1
BL DisplayCharactersR ; Display R6 chars contained in R4
......@@ -2545,7 +2562,7 @@ MemoryI_Code Entry "r6-r11"
BL DisplayHexWord
BLVC MarkBreakpoints
MOVVC r0, r1
MOVVC r1, r9
LDRVC r1, [r9]
SWIVC XDebugger_Disassemble
B %FT55
......@@ -2554,14 +2571,22 @@ MemoryI_Code Entry "r6-r11"
[ NoARMv5
; We may be running on a machine without LDRH, or without proper support for it (e.g. RiscPC)
; To avoid alignment faults on ARMv6+, load an aligned word and shift it ourselves
BIC r0, r9, #2
SUB sp, sp, #8
LDMIA r9, {r0,lr}
BIC r0, r0, #2
STMIA sp, {r0,lr}
MOV r0, sp
BL do_readW
TST r9, #2
ADD sp, sp, #8
LDR lr, [r9]
TST lr, #2
MOVNE r1, r1, LSR #16
; ARMv5+, safe to LDRH
MOV r0, r9
BL do_readH
MOV r4, r1
......@@ -2577,7 +2602,7 @@ MemoryI_Code Entry "r6-r11"
BL DisplayHexHalfword
BLVC MarkBreakpoints
MOVVC r0, r1
MOVVC r1, r9
LDRVC r1, [r9]
SWIVC XDebugger_DisassembleThumb
55 MOVVC r0, r1
......@@ -2586,9 +2611,14 @@ MemoryI_Code Entry "r6-r11"
ADD r9, r9, r6
LDMIA r9, {r3-r4}
LDMIA r7, {r5,lr}
ADDS r3, r3, r6
ADC r4, r4, #0
STMIA r9, {r3-r4}
TEQS r9, r7
TEQ r3, r5
TEQEQ r4, lr
......@@ -2606,18 +2636,20 @@ InitStore_Error
InitStore_Code Entry "r6-r11"
InitStore_Code Entry "r6-r11", 8
LDR wp, [r12]
MOV r1, r0
ADR r0, InitStore_Error
MOV r10, #0 ; arguments can only be 32-bit
BL ReadOneParm ; r7 := parm, r8 state
MOV r7, sp
BL ReadOneParm ; [r7] := parm, r8 state
BLVS CopyError
TST r8, #hasparm
LDRNE r7, [sp]
LDREQ r7, =&E7FFFFFF ; A nice invalid instruction
SWI XOS_GetEnv ; r1 -> end of user memory
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