Commit 0715cd51 authored by Robert Sprowson's avatar Robert Sprowson

Add ARMv8 AArch32 disassembly

Opcodes for CRC32/HLT/SEVL/LDA/STL/LDAEX/STLEX and DMB/DSB options.
Makefile:
  Add ARMv8_AArch32 actions and encodings to dis2.
actions/ARMv7,dis2.h:
  Extend the DMS/DSB decoding to warn about ARMv8 specific ones (previously undefined)
ARM.s/ARMv6.s:
  Slot in decode.
CGlue.s/Debugger.s/Messages
  New token for "ARMv8 or later" warnings.

Tested by brute force all 256M instructions in NV space and 256M conditionals, comparing the output against dis2.
Currently missing the new VFP and SIMD opcodes.

Version 1.98. Tagged as 'Debugger-1_98'
parent 3d2718aa
......@@ -81,6 +81,7 @@ ACTIONS_ARM = actions/common \
actions/ARMv7 \
actions/ARMv7_ASIMD \
actions/ARMv7_VFP \
actions/ARMv8_AArch32 \
actions/FPA \
actions/XScale_DSP
......@@ -91,6 +92,7 @@ ACTIONS_VFP = actions/common \
ENCODINGS = Build:decgen.encodings.ARMv7 \
Build:decgen.encodings.ARMv7_ASIMD \
Build:decgen.encodings.ARMv7_VFP \
Build:decgen.encodings.ARMv8_AArch32 \
Build:decgen.encodings.FPA \
Build:decgen.encodings.XScale_DSP
......
No preview for this file type
......@@ -254,4 +254,28 @@
ERETNE
HVC &1234
; V8 additions
DCI &E1043045 ; CRC32B r3, r4, r5
DCI &11043245 ; CRC32CBNE r3, r4, r5
DCI &11243245 ; CRC32CHNE r3, r4, r5
DCI &E14F3245 ; CRC32CW r3, pc, r5
DMB NSHLD
DSB LD
HLT &DEAD
SEVL
LDA r0, [r1]
LDACCB r0, [r1]
LDACCH r0, [pc]
STL r2, [r2]
LDAEXNE r0, [r1]
LDAEXD r0, r1, [r2]
LDAEXNEB r0, [pc]
LDAEXH r0, [r1]
STLEX r0, r1, [r2]
STLEXNE r0, pc, [r2]
END
......@@ -11,13 +11,13 @@
GBLS Module_HelpVersion
GBLS Module_ComponentName
GBLS Module_ComponentPath
Module_MajorVersion SETS "1.97"
Module_Version SETA 197
Module_MajorVersion SETS "1.98"
Module_Version SETA 198
Module_MinorVersion SETS ""
Module_Date SETS "11 Nov 2016"
Module_ApplicationDate SETS "11-Nov-16"
Module_ComponentName SETS "Debugger"
Module_ComponentPath SETS "castle/RiscOS/Sources/Programmer/Debugger"
Module_FullVersion SETS "1.97"
Module_HelpVersion SETS "1.97 (11 Nov 2016)"
Module_FullVersion SETS "1.98"
Module_HelpVersion SETS "1.98 (11 Nov 2016)"
END
/* (1.97)
/* (1.98)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 1.97
#define Module_MajorVersion_CMHG 1.98
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 11 Nov 2016
#define Module_MajorVersion "1.97"
#define Module_Version 197
#define Module_MajorVersion "1.98"
#define Module_Version 198
#define Module_MinorVersion ""
#define Module_Date "11 Nov 2016"
......@@ -18,6 +18,6 @@
#define Module_ComponentName "Debugger"
#define Module_ComponentPath "castle/RiscOS/Sources/Programmer/Debugger"
#define Module_FullVersion "1.97"
#define Module_HelpVersion "1.97 (11 Nov 2016)"
#define Module_LibraryVersionInfo "1:97"
#define Module_FullVersion "1.98"
#define Module_HelpVersion "1.98 (11 Nov 2016)"
#define Module_LibraryVersionInfo "1:98"
......@@ -347,6 +347,9 @@ DMB_A1(option,nonstandard)
ONLY1(ARMv7);
if(!dmb_dsb_opt[option].valid)
warning(JUSTPARAMS,WARN_BAD_DMB_DSB_ISB_OPTION);
/* Special mention OSHLD/NSHLD/ISHLD/LD */
if((option==1)||(option==5)||(option==9)||(option==13))
ONLY1(ARMv8);
sprintf(params->buf,"DMB\t%s",dmb_dsb_opt[option].str);
return;
}
......@@ -357,6 +360,9 @@ DSB_A1(option,nonstandard)
ONLY1(ARMv7);
if(!dmb_dsb_opt[option].valid)
warning(JUSTPARAMS,WARN_BAD_DMB_DSB_ISB_OPTION);
/* Special mention OSHLD/NSHLD/ISHLD/LD */
if((option==1)||(option==5)||(option==9)||(option==13))
ONLY1(ARMv8);
sprintf(params->buf,"DSB\t%s",dmb_dsb_opt[option].str);
return;
}
......
# Copyright 2016 Castle Technology Ltd
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
# Actions for ARMv8 disassembly
CRC_A1(cond,sz,Rn,Rd,C,Rm,nonstandard)
{
COMMON
static const char sizes[] = "BHWD";
ONLY1(ARMv8);
_UNPREDICTABLE((Rd==15) || (Rn==15) || (Rm==15) || (sz==3) || (cond!=14));
sprintf(params->buf,"CRC32%s%c\t%s,%s,%s",C?"C":"",sizes[sz],REG(Rd),REG(Rn),REG(Rm));
return;
}
SEVL_A1(cond,nonstandard)
{
COMMON
ONLY1(ARMv8);
sprintf(params->buf,"SEVL%s",condition(JUSTPARAMS,cond));
return;
}
HLT_A1(cond,imm12:imm4,nonstandard)
{
COMMON
ONLY1(ARMv8);
_UNPREDICTABLE(cond!=14);
sprintf(params->buf,"HLT%s\t%s%s%04X",condition(JUSTPARAMS,cond),(params->opt->ual?"#":""),HEX,imm12_imm4);
return;
}
LDAEXB_A1(cond,Rn,Rt,nonstandard)
{
COMMON
ONLY1(ARMv8);
_UNPREDICTABLE((Rt==15) || (Rn==15));
sprintf(params->buf,"LDAEXB%s\t%s,[%s]",condition(JUSTPARAMS,cond),REG(Rt),REG(Rn));
return;
}
LDAEXH_A1(cond,Rn,Rt,nonstandard)
{
COMMON
ONLY1(ARMv8);
_UNPREDICTABLE((Rt==15) || (Rn==15));
sprintf(params->buf,"LDAEXH%s\t%s,[%s]",condition(JUSTPARAMS,cond),REG(Rt),REG(Rn));
return;
}
LDAEX_A1(cond,Rn,Rt,nonstandard)
{
COMMON
ONLY1(ARMv8);
_UNPREDICTABLE((Rt==15) || (Rn==15));
sprintf(params->buf,"LDAEX%s\t%s,[%s]",condition(JUSTPARAMS,cond),REG(Rt),REG(Rn));
return;
}
LDAEXD_A1(cond,Rn,Rt,nonstandard)
{
COMMON
ONLY1(ARMv8);
_UNPREDICTABLE((Rt&1) || (Rt==14) || (Rn==15));
sprintf(params->buf,"LDAEXD%s\t%s,%s,[%s]",condition(JUSTPARAMS,cond),REG(Rt),REG((Rt+1)&0xf),REG(Rn));
return;
}
STLEXB_A1(cond,Rn,Rd,Rt,nonstandard)
{
COMMON
_UNPREDICTABLE((Rd==15) || (Rt==15) || (Rn==15));
_UNPREDICTABLE((Rd==Rn) || (Rd==Rt));
ONLY1(ARMv8);
sprintf(params->buf,"STLEXB%s\t%s,%s,[%s]",condition(JUSTPARAMS,cond),REG(Rd),REG(Rt),REG(Rn));
return;
}
STLEXH_A1(cond,Rn,Rd,Rt,nonstandard)
{
COMMON
ONLY1(ARMv8);
_UNPREDICTABLE((Rd==15) || (Rt==15) || (Rn==15));
_UNPREDICTABLE((Rd==Rn) || (Rd==Rt));
sprintf(params->buf,"STLEXH%s\t%s,%s,[%s]",condition(JUSTPARAMS,cond),REG(Rd),REG(Rt),REG(Rn));
return;
}
STLEX_A1(cond,Rn,Rd,Rt,nonstandard)
{
COMMON
_UNPREDICTABLE((Rd==15) || (Rt==15) || (Rn==15));
_UNPREDICTABLE((Rd==Rn) || (Rd==Rt));
ONLY1(ARMv8);
sprintf(params->buf,"STLEX%s\t%s,%s,[%s]",condition(JUSTPARAMS,cond),REG(Rd),REG(Rt),REG(Rn));
return;
}
STLEXD_A1(cond,Rn,Rd,Rt,nonstandard)
{
COMMON
_UNPREDICTABLE((Rd==15) || (Rt&1) || (Rt==14) || (Rn==15));
_UNPREDICTABLE((Rd==Rn) || ((Rd&0xe)==Rt));
ONLY1(ARMv8);
sprintf(params->buf,"STLEXD%s\t%s,%s,%s,[%s]",condition(JUSTPARAMS,cond),REG(Rd),REG(Rt),REG((Rt+1)&0xf),REG(Rn));
return;
}
LDA_A1(cond,sz,Rn,Rt,nonstandard)
{
COMMON
ONLY1(ARMv8);
_UNPREDICTABLE((Rt==15) || (Rn==15));
sprintf(params->buf,"LDA%s%s\t%s,[%s]",condition(JUSTPARAMS,cond),(sz==0)?"":(sz==2)?"B":"H",REG(Rt),REG(Rn));
return;
}
STL_A1(cond,sz,Rn,Rt,nonstandard)
{
COMMON
ONLY1(ARMv8);
_UNPREDICTABLE((Rt==15) || (Rn==15));
sprintf(params->buf,"STL%s%s\t%s,[%s]",condition(JUSTPARAMS,cond),(sz==0)?"":(sz==2)?"B":"H",REG(Rt),REG(Rn));
return;
}
......@@ -20,19 +20,19 @@
const optval dmb_dsb_opt[16] =
{
{ "#0", false },
{ "#1", false },
{ "OSHLD", true },
{ "OSHST", true },
{ "OSH", true },
{ "#4", false },
{ "#5", false },
{ "NSHLD", true },
{ "NSHST", true },
{ "NSH", true },
{ "#8", false },
{ "#9", false },
{ "ISHLD", true },
{ "ISHST", true },
{ "ISH", true },
{ "#12", false },
{ "#13", false },
{ "LD", true },
{ "ST", true },
{ "SY", true },
};
......@@ -155,6 +155,7 @@ const char *archwarnings[ARCH_MAX] =
"ASIMDv2 FP or later",
"FPA",
"XScale DSP instruction",
"ARMv8 or later",
};
#endif
......
......@@ -248,6 +248,7 @@ typedef enum {
ASIMDv2FP,
FPA,
XScaleDSP,
ARMv8,
ARCH_MAX
} earch;
......
......@@ -1172,6 +1172,7 @@ DataProcessing ROUT
BEQ UndefinedDataProcessing ; MUL/MLA in here too (and SWP from 1.23)
; (and MULL/MLAL from 1.44)
; (and LDRH etc from 1.48)
; (and LDA/STL from 1.98)
MOV r6, r4, LSR #21 ; r6 := dp opcode
AND r6, r6, #2_1111
......@@ -1355,6 +1356,9 @@ ControlExtension
CMP r5, #2_0011 :SHL: 4 ; 1,2,3 = CLZ/BX
BLS CLZ_BX_type
TEQ r5, #2_0100 :SHL: 4 ; 4 = CRC
BEQ is_CRC
TEQ r5, #2_0101 :SHL: 4 ; 5 = QADD etc
BEQ SaturatingArithmetic
......@@ -1364,9 +1368,6 @@ ControlExtension
TEQ r5, #2_0111 :SHL: 4 ; 7 = BKPT, HVC, SMI
BEQ MonitorCalls
CMP r5, #2_1000 :SHL: 4 ; 2,4 undefined
BLO Undefined
TST r5, #2_0001 :SHL: 4 ; 8,10,12,14 = SMUL etc
BEQ Mul16
......@@ -1578,41 +1579,45 @@ MonitorCalls
;
; format is cccc 0001 0oo0 xxxx xxxx xxxx 0111 xxxx
;
; where oo = op per DDI 0406C, A5.2.12
ANDS r5, r4, #2_11:SHL:21
BEQ Undefined ; 00 undefined still
; where oo = op per DDI 0487A, F4.2.12
AND r5, r4, #2_11:SHL:21
TEQ r5, #2_11:SHL:21
BEQ is_SMC ; 11 (SMC)
; Fall through ; 01 (BKPT) and 10 (HVC)
; Fall through ; 00 (HLT), 01 (BKPT) and 10 (HVC)
BKPT_or_HVC
BKPT_or_HVC_or_HLT
; arrive here with cccc 0001 0qq0 xxxx xxxx xxxx 0111 xxxx
; (qq != 00, qq != 11)
; (qq != 11)
;
; format is 1110 0001 0qq0 nnnn nnnn nnnn 0111 nnnn
;
; BKPT <number>
; HVI <number>
; HLT <number>
;
; where nnnn = number
; qq = qualifier (01 = BKPT, 10 = HVC)
AND r5, r4, #2_1111:SHL:28
TEQ r5, #2_1110:SHL:28
; qq = qualifier (00 = HLT, 01 = BKPT, 10 = HVC)
AND r8, r4, #2_1111:SHL:28
TEQ r8, #2_1110:SHL:28
BNE Undefined ; Note conditional is unpredictable
TestBit 22
CMP r5, #2_01:SHL:21
[ WarnARMv5
MOVEQ r10, #Mistake_ARMv5
MOVEQ r14, #Mistake_ARMv5
]
ADREQ r10, BkptTAB
[ WarnARMv7VE
MOVNE r10, #Mistake_ARMv7VE
MOVHI r14, #Mistake_ARMv7VE
]
[ WarnARMv5 :LOR: WarnARMv7VE
STR r10, Mistake
ADRHI r10, HvcTAB
[ WarnARMv8
MOVCC r14, #Mistake_ARMv8
]
TestStr 22,HvcTAB,BkptTAB
ADRCC r10, HltTAB
[ WarnARMv5 :LOR: WarnARMv7VE :LOR: WarnARMv8
STR r14, Mistake
]
BL SaveString
BL Tab
MOV r8, r4, LSR #8
......@@ -1625,6 +1630,7 @@ BKPT_or_HVC
BkptTAB DCB "BKPT",0
HvcTAB DCB "HVI",0
HltTAB DCB "HLT",0
ALIGN
SaturatingArithmetic
......@@ -2371,6 +2377,7 @@ Silly
= "A16",0 ; ARMv7MP or later
= "M49",0 ; Odd base of pair
= "A17",0 ; XScale DSP
= "A18",0 ; ARMv8 or later
ALIGN
......
......@@ -13,27 +13,32 @@
; limitations under the License.
;
; File: ARMv6.s
; Purpose: Disassembly of ARMv6 (and those few ARMv7) instructions
; Purpose: Disassembly of ARMv6 (and those few ARMv7
; and those few ARMv8 AArch32) instructions
; Author: K Bracey
; History: 23-Feb-00: KJB: created
LdrexStrex ROUT
; arrive here with cccc 0001 1xxx xxxx xxxx xxxx 1001 xxxx
; format is cccc 0001 1wwl nnnn dddd 1111 1001 mmmm
; format is cccc 0001 1wwl nnnn dddd 111r 1001 mmmm
;
; LDREX<H|B>{cond} Rd,[Rn]
; STREX<H|B>{cond} Rd,Rm,[Rn]
; LDREXD{cond} Rd,Rd+1,[Rn]
; STREXD{cond} Rd,Rm,Rm+1,[Rn]
; LD<R|A>EX<H|B>{cond} Rd,[Rn]
; ST<R|L>EX<H|B>{cond} Rd,Rm,[Rn]
; LD<R|A>EXD{cond} Rd,Rd+1,[Rn]
; ST<R|L>EXD{cond} Rd,Rm,Rm+1,[Rn]
;
; where cccc = condition
; l = Load/~Store
; r = Register/~Ordered
; ww = 00 (word) 01 (dword) 10 (byte) 11 (halfword)
; nnnn = Rn
; dddd = Rd
; mmmm = Rm (=1111 for LDREX)
AND r5, r4, #2_1111:SHL:8
TEQ r5, #2_1100:SHL:8
BEQ LdaStl
TEQ r5, #2_1111:SHL:8
TEQNE r5, #2_1110:SHL:8
BNE Undefined
[ WarnARMv6
......@@ -47,7 +52,18 @@ LdrexStrex ROUT
STR r14, Mistake
]
TestBit 8 ; Register or ordered type
BNE %FT10
[ WarnARMv8
MOV r14, #Mistake_ARMv8
STR r14, Mistake
]
TestStr 20,Ldaex,Stlex
B %FT20
10
TestStr 20,Ldrex,Strex
20
ADR r14, Exwidth
ANDS r7, r4, #2_0110:SHL:20
LDRNEB r14, [r14, r7, LSR #21]
......@@ -82,7 +98,7 @@ LdrexStrex ROUT
BL Dis_Register
TEQS r7,#2_0010:SHL:20
BNE %FT01
BNE %FT30
; Double word special
TestBit 20
......@@ -98,7 +114,7 @@ LdrexStrex ROUT
TestBit 20
ADDNE r5, r5, #1 ; Rd+1 for LDREXD
BL Comma_Dis_Register
01
30
TestBit 20
MOVEQ r5, r6
BEQ SwpCommon1
......@@ -110,6 +126,58 @@ LdrexStrex ROUT
Exwidth DCB "?", "D", "B", "H"
Ldrex DCB "LDREX", 0
Strex DCB "STREX", 0
Ldaex DCB "LDAEX", 0
Stlex DCB "STLEX", 0
ALIGN
LdaStl ROUT
; arrive here with cccc 0001 1xxx xxxx xxxx 1100 1001 xxxx
; format is cccc 0001 1wwl nnnn dddd 1100 1001 mmmm
;
; LDA{cond}<H|B> Rd,[Rn]
; STL{cond}<H|B> Rm,[Rn]
;
; where cccc = condition
; l = Load/~Store
; ww = 00 (word) 01 (dword) 10 (byte) 11 (halfword)
; nnnn = Rn
; dddd = Rd
; mmmm = Rm (=1111 for LDA)
TestBit 20
ANDNE r5, r4, #2_1111
TEQNE r5, #2_1111 ; Check mmmm for LDA
BNE Undefined
ANDS r8, r4, #2_11:SHL:21
TEQ r8, #2_01:SHL:21 ; Check for dword size (invalid)
BEQ Undefined
[ WarnARMv8
MOV r14, #Mistake_ARMv8
STR r14, Mistake
]
TestStr 20,LdaOp,StlOp,conds
ADR r14, Exwidth
MOVS r8, r8
LDRNEB r14, [r14, r8, LSR #21]
STRNEB r14, [r0], #1 ; <H|B>
TestBit 20
MOVNE r5, r4, LSR #12
MOVEQ r5, r4
BL Tab_Dis_Register
MOV r9, r4, LSR #16 ; Rn
AND r9, r9, #2_1111
TEQ r9, #15
TEQNE r5, #15
MOVEQ r14, #Mistake_R15 ; Rn or Rd or Rm = PC
STREQ r14, Mistake
B SwpCommon2
LdaOp DCB "LDA", 0
StlOp DCB "STL", 0
ALIGN
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
......@@ -148,26 +216,35 @@ is_DSB_DMB_ISB
AddChar "B"
BL Tab
AND r5, r4, #2_0011 ; 0=unpredictable, 1=LD, 2=ST, 3=all
SUBS r5, r5, #1
[ WarnARMv8
MOVEQ r14, #Mistake_ARMv8 ; LD
STREQ r14, Mistake
]
MOVMI r6, #2_1111 ; Behave as SY, but unpredictable
MOVMI r14, #Mistake_Unpred
STRMI r14, Mistake
AND r6, r4, #2_1111
TestBit 5 ; ISB
TEQNE r6, #2_1111 ; Must be SY
MOVNE r14, #Mistake_Unpred ; otherwise unpredictable
STRNE r14, Mistake
TestBit 1
MOVEQ r6, #2_1111 ; Behave as SY, but unpredictable
MOVEQ r14, #Mistake_Unpred
STREQ r14, Mistake
AND r5, r6, #2_1100 ; One of 4 in the table
; Now fits a vague pattern
TEQ r6, #2_1110 ; If it's just ST don't do SY
TEQNE r6, #2_1101 ; If it's just LD don't do SY
ANDNE r14, r6, #2_1100 ; One of 4 in the table
ADRNE r10, Barrier
ADDNE r10, r10, r5
ADDNE r10, r10, r14
BLNE SaveString
TST r6, #1
; Append LD/ST
CMP r5, #1
ADRCC r10, Typeld
ADREQ r10, Typest
BLEQ SaveString ; Append ST
BLLS SaveString
B InstructionEnd
is_CLREX
......@@ -191,6 +268,7 @@ UnpredArm
DCB "M65", 0
Clrex DCB "CLREX", 0
Typest DCB "ST", 0
Typeld DCB "LD", 0
Barrier DCB "OSH", 0, "NSH", 0, "ISH", 0, "SY", 0
; 00 01 10 11
ALIGN
......@@ -217,10 +295,14 @@ Hints ROUT
CMPS r5, #5
ADR r10, NopH
ADDCC r14, r5, r5, LSL #1 ; x3
ADDCC r10, r10, r14, LSL #1 ; x6
MOVCS r14, #Mistake_Unpred ; Behave as NOP but might change
STRCS r14, Mistake
ADDLS r14, r5, r5, LSL #1 ; x3
ADDLS r10, r10, r14, LSL #1 ; x6
MOVHI r14, #Mistake_Unpred ; Behave as NOP but might change
STRHI r14, Mistake
[ WarnARMv8
MOVEQ r14, #Mistake_ARMv8 ; SEVL
STREQ r14, Mistake
]
BL SaveStringConditions
BL Tab
B InstructionEnd
......@@ -240,6 +322,7 @@ YieldH DCB "YIELD", 0
WfeH DCB "WFE", 0, 0, 0
WfiH DCB "WFI", 0, 0, 0
SevH DCB "SEV", 0, 0, 0
SevlH DCB "SEVL", 0, 0
DbgH DCB "DBG", 0
ALIGN
......@@ -1311,4 +1394,57 @@ BitFieldExtract
AddChar "#"
B Rem_Number
is_CRC ROUT
; arrive here with cccc 0001 0xx0 xxxx xxxx xxxx 0100 xxxx
; format is cccc 0001 0ss0 nnnn dddd 00p0 0100 mmmm
;
; CRC32<C><B|H|W|D>{cond} Rd,Rn,Rm
;
; where cccc = condition
; p = polynomial
; dddd = Rd
; nnnn = Rn
; mmmm = Rm
; ss = size
TST r4, #2_1101:SHL:8
BNE Undefined
[ WarnARMv8
MOV r14, #Mistake_ARMv8
STR r14, Mistake
]
AND r5, r4, #2_1111:SHL:28
TEQ r5, #2_1110:SHL:28 ; Note conditional is unpredictable
AND r5, r4, #2_11:SHL:21
MOV r14, #Mistake_Unpred
STRNE r14, Mistake
TEQ r5, #2_11:SHL:21 ; As is 64 bit size
STREQ r14, Mistake
AddStr Crc32Op
TestBit 9,"C"
ADR r14, Crc32Sz
LDRB r10, [r14, r5, LSR #21]
STRB r10, [r0], #1
MOV r5, r4, LSR #12
BL Tab_Dis_Register
MOV r7, r5
MOV r5, r4, LSR #16
BL Comma_Dis_Register
MOV r8, r5
MOV r5, r4
BL Comma_Dis_Register
TEQ r5, #15 ; Can't use PC for nothing no more
TEQNE r7, #15
TEQNE r8, #15
MOVEQ r14, #Mistake_R15
STREQ r14, Mistake
B InstructionEnd
Crc32Op DCB "CRC32", 0
Crc32Sz DCB "BHWD"
ALIGN
END
......@@ -155,5 +155,6 @@ archwarnings
= "A13", 0 ; ASIMDv2FP
= "M00", 0 ; FPA (impossible with VFP-only build)
= "A17", 0 ; XScaleDSP
= "A18", 0 ; ARMv8
END
......@@ -93,6 +93,9 @@ WarnARMv7VE SETL {TRUE} ; Indicate ARMv7VE or later instructions
GBLL WarnARMv7MP
WarnARMv7MP SETL {TRUE} ; Indicate ARMv7MP or later instructions
GBLL WarnARMv8
WarnARMv8 SETL {TRUE} ; Indicate ARMv8 or later instructions
GBLL Thumbv6
Thumbv6 SETL {FALSE} ; Thumb v6 (incomplete)
......@@ -254,6 +257,7 @@ Mistake_ARMv7VE # 1
Mistake_ARMv7MP # 1
Mistake_BaseOdd # 1
Mistake_XScaleDSP # 1
Mistake_ARMv8 # 1
^ -1
Potential_SWICDP # -1
......
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