Commit f49f2d8c authored by Robert Sprowson's avatar Robert Sprowson Committed by ROOL
Browse files

Minor fixes and enhancements

Makefile: Add A53 to the list that don't need any support
GetAll.s: Trim some unneeded headers
Macros.s: Use instruction directly now ObjAsm supports it
Module.s: Fix stack imbalance in SupportHandlerTemplateSV, add Cortex-A72 table entry
Salvaged from a previous concept when FMACs would be fixed up by the abort handler.
parent 2f1e4f6c
......@@ -30,10 +30,10 @@
# Use machine type to determine whether support code is needed
# Can also be overridden on command line by specifying SUPPORTCODE
# Assuming we're targeting a machine capable of VFP, Cortex-A8 is currently the
# only machine type which doesn't need any support code at all
# Assuming we're targeting a machine capable of VFP, Cortex-A8 and Cortex-A53 are
# the only machine types which don't need any support code at all
DEFSUPPORTCODE = TRUE
ifneq (,$(findstring ${MACHINE},CortexA8))
ifneq (,$(findstring ${MACHINE},CortexA8 CortexA53))
DEFSUPPORTCODE = FALSE
endif
......
......@@ -29,8 +29,6 @@
GET Hdr:ListOpts
GET Hdr:Macros
GET Hdr:System
GET Hdr:Machine.<Machine>
GET Hdr:CPU.Arch
GET Hdr:ModHand
GET Hdr:NdrDebug
GET Hdr:Services
......@@ -65,10 +63,6 @@ MaxDRegs SETA 32
MaxDRegs SETA 16
]
[ SupportCode
GET hdr.shared
]
GET Structures.s
GET Macros.s
......@@ -76,6 +70,7 @@ MaxDRegs SETA 16
GET Module.s
[ SupportCode
GET hdr.shared
GET SupportCode.s
GET CSupport.s
]
......
......@@ -41,7 +41,7 @@
|
; ARMv7+, use ISB instruction (saves on temp register, but instruction is unconditional)
; Shouldn't hurt too much if we just ignore the condition code
DCI &F57FF06F ; ISB SY
ISB SY
]
MEND
......
......@@ -159,13 +159,14 @@ SupportHandlerTemplateSV
Push "r11,r12"
LDR r11, [r14, #-4] ; N.B. assuming not Thumb mode!
CMP r11, #&F0000000 ; Reject unconditional instructions
LDRHS pc, RelocOffsetSV+:INDEX:OldHandler
BHS %FT10
AND r12, r11, #&0F000000
AND r11, r11, #&00000E10
TEQ r12, #&0E000000
TEQEQ r11, #&00000A00
ADREQ r12, RelocOffsetSV
LDREQ pc, RelocOffsetSV+:INDEX:VFPSupportCodePtr
10
Pull "r11,r12"
LDR pc, RelocOffsetSV+:INDEX:OldHandler
SupportHandlerTemplateSVEnd
......@@ -381,6 +382,7 @@ HasMVFRTable
; Bottom nibble of the below values are used to store the number of implemented feature registers
DCW &20B2 ; VFP11 has MVFR0, MVFR1
DCW &4033 ; Cortex-A53 has MVFR0, MVFR1, MVFR2
DCW &4083 ; Cortex-A72 has MVFR0, MVFR1, MVFR2
DCW 0
ALIGN
......@@ -638,8 +640,8 @@ SWI_CheckContext
; in: R0 = flags
; b0 = user mode flag (0=user mode access not required, 1=user mode access required)
; b1 = application space flag (0=not in application space, 1=in application space)
; b30 = ignored (for CreateContext compatability)
; b31 = ignored (for CreateContext compatability)
; b30 = ignored (for CreateContext compatibility)
; b31 = ignored (for CreateContext compatibility)
; other bits reserved, sbz
; R1 = number of doubleword registers required (1-32)
; out: R0 = required size of context save area
......
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