Commit 48d821ca authored by Jeffrey Lee's avatar Jeffrey Lee
Browse files

Fix save/restore of contexts which have pending exceptions

Detail:
  s/Module - Fixed context save & restore code to ensure FPEXC EX & FP2V bits are clear when accessing FPSCR and the main VFP registers. Without doing this, attempting to save or restore a context which has a pending exception will trigger an exception itself.
  Test/test2,ffb - Simple test to make sure save/restore of contexts with pending exceptions works properly
  Test/test1,ffb - Added brief description, changed file from plain text to tokenised BASIC to prevent it accidentally happening later on
Admin:
  Tested on Raspberry Pi
  Programs which need support code to run or trigger math exceptions no longer trigger an undefined instruction abort from within VFPSupport


Version 0.05. Tagged as 'VFPSupport-0_05'
parent 28c505b0
No preview for this file type
File added
......@@ -11,13 +11,13 @@
GBLS Module_HelpVersion
GBLS Module_ComponentName
GBLS Module_ComponentPath
Module_MajorVersion SETS "0.04"
Module_Version SETA 4
Module_MajorVersion SETS "0.05"
Module_Version SETA 5
Module_MinorVersion SETS ""
Module_Date SETS "21 Jul 2012"
Module_ApplicationDate SETS "21-Jul-12"
Module_Date SETS "19 Oct 2012"
Module_ApplicationDate SETS "19-Oct-12"
Module_ComponentName SETS "VFPSupport"
Module_ComponentPath SETS "bsd/RiscOS/Sources/HWSupport/VFPSupport"
Module_FullVersion SETS "0.04"
Module_HelpVersion SETS "0.04 (21 Jul 2012)"
Module_FullVersion SETS "0.05"
Module_HelpVersion SETS "0.05 (19 Oct 2012)"
END
/* (0.04)
/* (0.05)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 0.04
#define Module_MajorVersion_CMHG 0.05
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 21 Jul 2012
#define Module_Date_CMHG 19 Oct 2012
#define Module_MajorVersion "0.04"
#define Module_Version 4
#define Module_MajorVersion "0.05"
#define Module_Version 5
#define Module_MinorVersion ""
#define Module_Date "21 Jul 2012"
#define Module_Date "19 Oct 2012"
#define Module_ApplicationDate "21-Jul-12"
#define Module_ApplicationDate "19-Oct-12"
#define Module_ComponentName "VFPSupport"
#define Module_ComponentPath "bsd/RiscOS/Sources/HWSupport/VFPSupport"
#define Module_FullVersion "0.04"
#define Module_HelpVersion "0.04 (21 Jul 2012)"
#define Module_LibraryVersionInfo "0:4"
#define Module_FullVersion "0.05"
#define Module_HelpVersion "0.05 (19 Oct 2012)"
#define Module_LibraryVersionInfo "0:5"
......@@ -753,11 +753,14 @@ SaveContext_R1
STR r2, [r1,#Context_FPEXC]
BPL %FT10
; Must store FPINST
myVMRS ,r2, FPINST
STR r2, [r1,#Context_FPINST]
myVMRS ,lr, FPINST
STR lr, [r1,#Context_FPINST]
; Might need to store FPINST2
myVMRS VS,r2, FPINST2
STRVS r2, [r1,#Context_FPINST2]
myVMRS VS,lr, FPINST2
STRVS lr, [r1,#Context_FPINST2]
; Must clear exception bits before we're able to store the rest
BIC r2, r2, #FPEXC_EX+FPEXC_FP2V
myVMSR ,FPEXC,r2
10
LDR lr, [r1,#Context_NumRegs]
myVMRS ,r2, FPSCR
......@@ -797,19 +800,20 @@ LoadContext_R0
ASSERT FPEXC_FP2V = V_bit
ASSERT FPEXC_EN = Z_bit ; EN bit will be clear if there are no data registers to restore (actually, entire FPEXC will be clear)
MSR CPSR_f, r2
myVMSR EQ,FPEXC, r2 ; Don't write FPEXC if EN isn't set
BIC r3, r2, #FPEXC_EX+FPEXC_FP2V ; Don't set the exception bits yet
myVMSR EQ,FPEXC, r3 ; Don't write FPEXC if EN isn't set
BPL %FT10
; Must restore FPINST
LDR r2, [r0,#Context_FPINST]
myVMSR ,FPINST, r2
LDR lr, [r0,#Context_FPINST]
myVMSR ,FPINST, lr
; Might need to restore FPINST2
LDRVS r2, [r0,#Context_FPINST2]
myVMSR VS,FPINST2, r2
LDRVS lr, [r0,#Context_FPINST2]
myVMSR VS,FPINST2, lr
10
LDR r3, [r0,#Context_FPSCR]
LDREQ lr, [r0,#Context_NumRegs]
LDR r2, [r0,#Context_FPSCR]
myVMSR ,FPSCR, r3 ; Will only work on first use of new context if we already have CP access (which we currently will)
ADDEQ r3, r0, #Context_RegDump
myVMSR ,FPSCR, r2 ; Will only work on first use of new context if we already have CP access (which we currently will)
ADDEQ pc, pc, lr, LSL #4
; If we're still here, we need to reset FPEXC to default and load 0 regs
MOV r2, #FPEXC_EN
......@@ -824,14 +828,14 @@ count SETA 1
WHILE count < 33
[ count <= 16
DCI &EC930B00 + count*2 ; VLDMIA r3,{D0-Dn}
myVMSR MI,FPEXC, r2 ; Set exception bits now that all registers are restored
EXIT
NOP
NOP
|
DCI &ECB30B20 ; VLDMIA r3!,{D0-D15} (we can only LDM 16 at once)
DCI &ECD30B00 + (count-16)*2 ; VLDMIA r3,{D16-Dn}
myVMSR MI,FPEXC, r2
EXIT
NOP
]
count SETA count+1
WEND
......
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