Commit 99066177 authored by Jeffrey Lee's avatar Jeffrey Lee
Browse files

Minor tweaks

Detail:
  c/errors, h/errors, c/init - Add a timeout to launch_core to make it easier to debug when things go wrong
  h/halcalls - Fix typo
  s/CPUInfo - Disable logging of some CP15 registers which aren't implemented on all CPUs
Admin:
  Tested on Raspberry Pi 3


Version 0.03. Tagged as 'SMP-0_03'
parent aa4c1c5c
/* (0.02)
/* (0.03)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 0.02
#define Module_MajorVersion_CMHG 0.03
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 29 Jul 2017
#define Module_Date_CMHG 10 Sep 2017
#define Module_MajorVersion "0.02"
#define Module_Version 2
#define Module_MajorVersion "0.03"
#define Module_Version 3
#define Module_MinorVersion ""
#define Module_Date "29 Jul 2017"
#define Module_Date "10 Sep 2017"
#define Module_ApplicationDate "29-Jul-17"
#define Module_ApplicationDate "10-Sep-17"
#define Module_ComponentName "SMP"
#define Module_ComponentPath "mixed/RiscOS/Sources/Programmer/SMP"
#define Module_FullVersion "0.02"
#define Module_HelpVersion "0.02 (29 Jul 2017)"
#define Module_LibraryVersionInfo "0:2"
#define Module_FullVersion "0.03"
#define Module_HelpVersion "0.03 (10 Sep 2017)"
#define Module_LibraryVersionInfo "0:3"
......@@ -55,6 +55,7 @@ static _kernel_oserror errors[Error_MAX] =
DEFERROR(ThreadNotComplete, "Thread not complete"),
DEFERROR(BadContext, "Bad context"),
DEFERROR(TerminateFailed, "Failed to terminate"),
DEFERROR(Timeout, "Timeout"),
};
_kernel_oserror *geterror(Error e)
......
......@@ -29,6 +29,7 @@
#include <string.h>
#include <stdint.h>
#include <stdbool.h>
#include <time.h>
#include "kernel.h"
#include "swis.h"
......@@ -43,6 +44,7 @@
#include "asm.h"
#include "defs.h"
#include "thread.h"
#include "errors.h"
#ifdef BOOTSTRAP_DEBUG
#include "smpkernel.h"
#endif
......@@ -222,19 +224,25 @@ static void init_bootstrap(initdata_t *initdata, corews_t *corews)
Cache_CleanInvalidateRange(initdata->bootstrap_log, (void *) ((((uint32_t) initdata->bootstrap_log) + bootstrap_len + 4095) & ~4095)); /* Just align to page boundary for simplicity */
}
static void launch_core(initdata_t *initdata, int core)
static _kernel_oserror *launch_core(initdata_t *initdata, int core)
{
dprintf(("", "launch_core: core %d\n", core));
glob.corews[core]->state = CORESTATE_RUNNING | CORESTATE_TRANSITION;
asm_dsb_isb(); /* Should we require the HAL to do this for us? */
_swix(OS_Hardware, _INR(0,1)|_INR(8,9), core, initdata->bootstrap_phys+bootstrap_bootoffset, OSHW_CallHAL, EntryNo_HAL_SMPStartup);
/* Wait for confirmation of startup */
while (glob.corews[core]->state & CORESTATE_TRANSITION)
clock_t start = clock();
while ((glob.corews[core]->state & CORESTATE_TRANSITION) && ((clock()-start) < CLOCKS_PER_SEC))
{
cpuevent_wait();
barrier_sync();
}
dprintf(("", "launch_core: done, state = %08x\n", glob.corews[core]->state));
if (glob.corews[core]->state & CORESTATE_TRANSITION)
{
return ERROR(Timeout);
}
return NULL;
}
_kernel_oserror *init_cores(void)
......@@ -354,7 +362,18 @@ _kernel_oserror *init_cores(void)
for (int i=1;i<glob.numcores;i++)
{
init_bootstrap(&initdata, glob.corews[i]);
launch_core(&initdata, i);
e = launch_core(&initdata, i);
if (e)
{
#ifdef BOOTSTRAP_DEBUG
/* Hide the error from the outer layers so that we don't quit the module */
dprintf(("", "%s\n",e->errmess));
e = NULL;
#else
/* TODO: Deal with error more sensibly */
#endif
return e;
}
}
/* Free page tables */
......
......@@ -44,6 +44,7 @@ typedef enum {
Error_ThreadNotComplete,
Error_BadContext,
Error_TerminateFailed,
Error_Timeout,
Error_MAX,
} Error;
......
......@@ -153,7 +153,7 @@ static inline RET CALL(ARG0 arg0, ARG1 arg1, ARG2 arg2) \
#else /* #ifndef HALCALLS_C */
#define HALCall0V(CALL) HALCALLs_C(CALL)
#define HALCall0V(CALL) HALCALLS_C(CALL)
#define HALCall0(CALL,RET) HALCALLS_C(CALL)
#define HALCall1V(CALL,ARG0) HALCALLS_C(CALL)
#define HALCall1(CALL,ARG0,RET) HALCALLS_C(CALL)
......
......@@ -72,17 +72,17 @@ CPUInfo
CP15Reg 0, c10, c2, 0, "PRRR"
CP15Reg 0, c10, c2, 1, "NMRR"
CP15Reg 0, c12, c0, 0, "VBAR"
CP15Reg 0, c12, c0, 1, "MVBAR"
; CP15Reg 0, c12, c0, 1, "MVBAR"
CP15Reg 0, c12, c1, 0, "ISR"
CP15Reg 0, c12, c1, 1, "VISR"
; CP15Reg 0, c12, c1, 1, "VISR"
CP15Reg 0, c13, c0, 0, "FCSEIDR"
CP15Reg 0, c13, c0, 1, "CONTEXTIDR"
CP15Reg 0, c13, c0, 2, "TPIDRURW"
CP15Reg 0, c13, c0, 3, "TPIDRURO"
CP15Reg 0, c13, c0, 4, "TIPDRPRW"
CP15Reg 0, c15, c0, 0, "Power Control Register"
CP15Reg 0, c15, c1, 0, "NEON Busy Register"
CP15Reg 4, c15, c0, 0, "Configuration Base Address"
; CP15Reg 0, c15, c0, 0, "Power Control Register"
; CP15Reg 0, c15, c1, 0, "NEON Busy Register"
; CP15Reg 4, c15, c0, 0, "Configuration Base Address"
EXIT
END
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