1. 02 Mar, 2020 1 commit
    • Robert Sprowson's avatar
      Add aligned RMA claim subreason · fd81a66c
      Robert Sprowson authored
      => R0=24
         R3=size in bytes
         R4=alignment in bytes (must be a power of 2)
      <= R2=base of request
         or error
      Tested with a handful of valid and invalid alignments, and with one grossly larger than the free RMA to trigger an RMA extend to occur.
      Version 6.35. Tagged as 'Kernel-6_35'
  2. 24 Nov, 2019 1 commit
    • Timothy E Baldwin's avatar
      Permit special field in paths passed to OS_CLI · 2ec9e04e
      Timothy E Baldwin authored
      OS_CLI permits commands to be prefixed with a temporary filing
      system, for example "ADFS:Format"
      It also passes commands unrecognised to FileSwitch to be executed,
      so "ADFS::HardDisc4.$.!Boot" first sets the temporary filing to
      ADFS then executes ":HardDisc4.$.!Boot".
      This does not work if the path contains a special field,
      currently this results in an error as the special filed
      would be lost.
      Unfortunately many programs, including the RISC OS source
      fail because of this.
      Instead if a filing system prefix with special field
      is found switch to the Temporary filing system and
      treat the whole command as a path to execute. For example
      passing "IXFS#W:$.HardDisc4.!Boot" sets the temporary filing
      system to "IXFS" then executes "IXFS#W:$.HardDisc4.!Boot".
      Version 6.30. Tagged as 'Kernel-6_30'
  3. 02 Aug, 2016 1 commit
    • Jeffrey Lee's avatar
      Add support for shareable pages and additional access privileges · 9cd4cbe4
      Jeffrey Lee authored
        This set of changes:
        * Refactors page table entry encoding/decoding so that it's (mostly) performed via functions in the MMU files (s.ARM600, s.VMSAv6) rather than on an ad-hoc basis as was the case previously
        * Page table entry encoding/decoding performed during ROM init is also handled via the MMU functions, which resolves some cases where the wrong cache policy was in use on ARMv6+
        * Adds basic support for shareable pages - on non-uniprocessor systems all pages will be marked as shareable (however, we are currently lacking ARMops which broadcast cache maintenance operations to other cores, so safe sharing of cacheable regions isn't possible yet)
        * Adds support for the VMSA XN flag and the "privileged ROM" access permission. These are exposed via RISC OS access privileges 4 and above, taking advantage of the fact that 4 bits have always been reserved for AP values but only 4 values were defined
        * Adds OS_Memory 17 and 18 to convert RWX-style access flags to and from RISC OS access privelege numbers; this allows us to make arbitrary changes to the mappings of AP values 4+ between different OS/hardware versions, and allows software to more easily cope with cases where the most precise AP isn't available (e.g. no XN on <=ARMv5)
        * Extends OS_Memory 24 (CheckMemoryAccess) to return executability information
        * Adds exported OSMem header containing definitions for OS_Memory and OS_DynamicArea
        File changes:
        - Makefile - export C and assembler versions of hdr/OSMem
        - Resources/UK/Messages - Add more text for OS_Memory errors
        - hdr/KernelWS - Correct comment regarding DCacheCleanAddress. Allocate workspace for MMU_PPLTrans and MMU_PPLAccess.
        - hdr/OSMem - New file containing exported OS_Memory and OS_DynamicArea constants, and public page flags
        - hdr/Options - Reduce scope of ARM6support to only cover builds which require ARMv3 support
        - s/AMBControl/Workspace - Clarify AMBNode_PPL usage
        - s/AMBControl/growp, mapslot, mapsome, memmap - Use AreaFlags_ instead of AP_
        - s/AMBControl/main, memmap - Use GetPTE instead of generating page table entry manually
        - s/ARM600 - Remove old coments relating to lack of stack. Update BangCam to use GetPTE. Update PPL tables, removing PPLTransL1 (L1 entries are now derived from L2 table on demand) and adding a separate table for ARM6. Implement the ARM600 versions of the Get*PTE ('get page table entry') and Decode*Entry functions
        - s/ARMops - Add Init_PCBTrans function to allow relevant MMU_PPLTrans/MMU_PCBTrans pointers to be set up during the pre-MMU stage of ROM init. Update ARM_Analyse to set up the pointers that are used post MMU init.
        - s/ChangeDyn - Move a bunch of flags to hdr/OSMem. Rename the AP_ dynamic area flags to AreaFlags_ to avoid name clashes and confusion with the page table AP_ values exported by Hdr:MEMM.ARM600/Hdr:MEMM.VMSAv6. Also generate the relevant flags for OS_Memory 24 so that it can refer to the fixed areas by their name instead of hardcoding the permissions.
        - s/GetAll - GET Hdr:OSMem
        - s/HAL - Change initial page table setup to use DA/page flags and GetPTE instead of building page table entries manually. Simplify AllocateL2PT by removing the requirement for the user to supply the access perimssions that will be used for the area; instead for ARM6 we just assume that cacheable memory is the norm and set L1_U for any L1 entry we create here.
        - s/Kernel - Add GetPTE macro (for easier integration of Get*PTE functions) and GenPPLAccess macro (for easy generation of OS_Memory 24 flags)
        - s/MemInfo - Fixup OS_Memory 0 to not fail on seeing non-executable pages. Implement OS_Memory 17 & 18. Tidy up some error generation. Make OS_Memory 13 use GetPTE. Extend OS_Memory 24 to return (non-) executability information, to use the named CMA_ constants generated by s/ChangeDyn, and to use the Decode*Entry functions when it's necessary to decode page table entries.
        - s/NewReset - Use AreaFlags_ instead of AP_
        - s/VMSAv6 - Remove old comments relating to lack of stack. Update BangCam to use GetPTE. Update PPL tables, removing PPLTransL1 (L1 entries are now derived from L2 table on demand) and adding a separate table for shareable pages. Implement the VMSAv6 versions of the Get*PTE and Decode*Entry functions.
        Tested on Raspberry Pi 1, Raspberry Pi 3, Iyonix, RPCEmu (ARM6 & ARM7), comparing before and after CAM and page table dumps to check for any unexpected differences
      Version 5.55. Tagged as 'Kernel-5_55'
  4. 05 Apr, 2016 1 commit
    • Jeffrey Lee's avatar
      Add SWI error pointer validation, SeriousErrorV hooks, and OS_ReadSysInfo 15 · b4cf3959
      Jeffrey Lee authored
        Resources/UK/Messages, hdr/KernelWS, s/Kernel - On return from a SWI with V set, do some basic validity checks on the error pointer in order to try and catch buggy SWIs that return bad pointers or invalid error blocks. If a bad pointer is found we'll substitute it with a pointer to a different error block, which has the SWI number in the error message, to allow the user to identify the source of the problem. (There's also a chance we'll crash when investigating a bad pointer, but crashing here in the kernel is preferable to crashing elsewhere because R12 should still contain the SWI number)
        hdr/OSMisc - Define SeriousErrorV reason codes and extended ROM footer entry IDs
        hdr/Options - Remove HangWatch integration flag, obsolete now that SeriousErrorV is available
        s/ArthurSWIs - Keep defaultvectab up to date with vector allocations
        s/Middle - Update serious error handling to call SeriousErrorV at several key points. This allows for accurate crash dumps to be obtained, along with a mechanism to warn low-level components such as RTSupport that the privileged mode stacks are being flattened.
        s/Middle - Add OS_ReadSysInfo 15, for enumerating extended ROM footer entries
        s/PMF/osbyte - Update InitNewFX0Error to use the ROM footer entry ID defined in hdr/OSMisc
        Tested on Pi 1B, 2B, 3B
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_313'
  5. 29 Feb, 2016 1 commit
    • Ben Avison's avatar
      Support for ARMv8 · 66b90f9d
      Ben Avison authored
        * Filled in CPU tables for publicly documented ARMv8 cores (Cortex-A53,57,72).
        * Recent ARM ARMs (e.g. section B1.9.2 of the ARMv7AR ARM) permit the core to
          take an undefined instruction exception upon encountering even not-taken
          conditional undefined instructions. This option is exercised by the
          Cortex-A53, unlike all ARMv7 cores previously supported by RISC OS. This
          unfortunately trips up a lot of kernel code that adapts to different
          architectures at runtime. These have now all been replaced with branches
          over the affected code on the opposite condition.
        * Fixed bug in HAL_InvalidateCache_ARMvF: for the main body of the loop,
          which was written as though to act on the CLIDR register, r8 actually
          contained the CTR register instead.
        Tested on Raspberry Pi 3
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_304'
  6. 21 Dec, 2014 1 commit
    • Robert Sprowson's avatar
      Delegate L2 (and below) cache init at power on/reset to the HAL · 16c00596
      Robert Sprowson authored
      Historically the kernel looked after all aspects of cache control since they were common across all ARMs. However, not all cache controllers are created equal, and sometimes more complex initialisation steps are needed than fit the generic coprocessor ops - for example the PL310 attached to a Cortex-A9 has memory mapped control registers.
      Rather than clutter the kernel with one shot init code for every cache controller invented, we delegate that step to the HAL in HAL_Init. This is only a few hundred instructions later than where it was already being set. The kernel remains responsible for subsequent maintenance, this is just init which is being handed off.
      A quick survey of the Cortex-A TRMs shows:
      A5 - optional, for example ARM's PL310, ref TRM section 8.1.7.
      A7 - optional, C bit of SCTLR, ref TRM section 1.1.
      A8 - L2EN bit of ACTLR, note this bit has been recycled for other uses on other cores, ref TRM section 8.3.
      A9 - not integrated, ARM's PL310 uses bit 0 of control register 1, ref PL310 TRM section 3.1.1.
      A12 - see A17
      A15 - integrated, C bit of SCTLR, ref TRM section 7.2.3.
      A17 - integrated, bit 18 of L2CTLR & C bit of SCTLR, ref TRM section 7.2.
      and while we've got the TRMs open, back fill the CPU id register table.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_250'
  7. 15 Dec, 2013 1 commit
    • Jeffrey Lee's avatar
      Assorted GraphicsV improvements · 694750de
      Jeffrey Lee authored
        This set of changes:
        * Adds basic support for multiple GraphicsV drivers, by way of some new OS_ScreenMode reason codes for registering/deregistering, selecting and enumerating drivers (11, 64-68)
        * Tidies up handling of HAL video calls so that the HAL calls will be transformed into a bona fide GraphicsV driver if they're implemented
        * Changes handling of 16bpp gamma table entries so that they're sent to GraphicsV in a generic form instead of in a VIDC-specific form
        * Adds a new GraphicsV call and defines new VIDC list items to allow GraphicsV drivers to utilise the new pixel formats
        File changes:
        * h/VIDCList, hdr/VIDCList, Makefile - Add new header export containing VIDC list type 3 definitions, to avoid repeated definitions in other components
        * Resources/UK/Messages - Add new GraphicsV/OS_ScreenMode error strings and some missing processor type strings
        * hdr/KernelWS - Clean up some pre-GraphicsV definitions, and add new workspace locations for storing the current GraphicsV driver number and the driver list
        * hdr/Options - Remove obsolete InverseTextTransparency option
        * hdr/VduExt - Add VDU variable 192 for storing GraphicsV driver number (same as ROL's VideoV driver number). Remove old 'Flag_*' mode flag definitions (use new 'ModeFlag_*' defintions instead). Add new OS_ScreenMode reason codes.
        * s/ARM600, s/VMSAv6, s/vdu/vdu23, s/vdu/vdugrafa, s/vdu/vdugrafd, s/vdu/vdupalxx, s/vdu/vdupointer, s/vdu/vduwrch - Strip out pre-GraphicsV code. Update GraphicsV code to use correct driver number.
        * s/ArthurSWIs - Pass the default GraphicsV claimant the VduDriverWorkSpace instead of ZeroPage
        * s/Getall - Add Hdr:VIDCList and s/vdu/VduGrafHAL to list of GETs
        * s/NewIRQs - Remove HAL VSync IRQ initialisation, is now handled by grafvhal. Remove old HAL VsyncIRQ entry point, all VSyncs are now handled by VsyncIRQ_ExtEntry.
        * s/PMF/osbyte - Stop OS_Byte 19 waiting forever if no video driver is active
        * s/PMF/osinit - Remove HAL VSync IRQ initialisation, is now handled by grafvhal
        * s/vdu/vducursoft - Use new workspace variable names and flag names
        * s/vdu/vdudecl - Remove old HALDAG_* definitions, GVDAG_* definitions are used instead. Add definition of the per-driver workspace structure and flags.
        * s/vdu/vdudriver - Remove pre-GraphicsV code. Update InitialiseMode to check for and initialise a HAL driver. Use cached driver features word in a few places instead of calling GraphicsV each time. Update PalIndexTable to disable VIDC mangling of 16bpp gamma tables.
        * s/vdu/vdugrafv, s/vdu/vdugrafhal - HAL<->GraphicsV code split off into its own file (vdugrafhal). Default GraphicsV claimant now only deals with VSync events for the active driver.
        * s/vdu/vdumodes - Get rid of old VIDC List type 3 definiton; now in hdr/VIDCList
        * s/vdu/vduswis - Added OS_ScreenMode reason codes 11 and 64-68 for registering, deregistering, selecting and enumerating GraphicsV drivers. Update mode set code to not bother checking if the driver supports the pixel format; instead we assume that the driver's vet mode call will do the check for us.
        Tested in Tungsten, IOMD, OMAP3 & BCM2835 ROMs
        Requires HdrSrc-2_38 and updated video driver modes
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_203'
  8. 05 Dec, 2012 1 commit
    • Jeffrey Lee's avatar
      Add support for new extended internal key codes, low level key codes, and key handler format · bcb499b5
      Jeffrey Lee authored
        s/Middle - Added OS_ReadSysInfo 13 to allow the kernel to validate a key handler before the owner attempts to install it
        Resources/UK/Messages - Text for new "Bad key handler" error
        s/GetAll, s/PMF/Def - Get rid of now obsolete s/PMF/Def file. It only contained definitions for pre-HAL hardware, and for the key handler layout (now in Hdr:Keyboard)
        hdr/KeyWS - Increased size of KeysDown array so it can hold 768 keys instead of 160. Trim a couple of obsolete variables, and increase CurrKey/OldKey from 1 byte to 4 bytes.
        s/PMF/key, s/PMF/osbyte - Main bulk of the changes for the new key handling. All the important interfaces are now able to deal with extended (i.e. > 8 bit) internal key numbers, and the kernel is able to cope with key handlers which use 16 bit internal/low level key numbers instead of 8 bit.
        Tested on Pandora & BB-xM
        Requires HdrSrc-2_20
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_178'
  9. 01 Jul, 2012 1 commit
    • Robert Sprowson's avatar
      Sort out SetBorder · fe354937
      Robert Sprowson authored
      The one remaining use of SetBorder was to denote the user asked for and got a CMOS reset, which in the HAL case emitted a warning because setting the border is potentially complicated/slow.
      To solve this, the reset is noted and replaces the normal RISC OS banner with a warning message. The behaviour and text for this comes from the BBC Master, though the escape key is used in place of break since a reset isn't actually needed.
      Moved the unused cputable inside its corresponding switch.
      Two occurrences of WriteS_Translated would have executed the message in the V=1 case.
      Flag added to workspace, translation added to messages files.
      Commented out use of SetBorder removed.
      SetBorder macro removed.
      Switched out use of SetBorder removed.
      Conditional WriteS_Translated would try to execute the message in the opposite condition case.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_157'
  10. 27 Nov, 2011 1 commit
    • Robert Sprowson's avatar
      Added 'UnConv' error (see also HdrSrc). · 191ae197
      Robert Sprowson authored
      Implement OS_ConvertVariform, internally the other conversions now just call it.
      Add tester for Variform to 'Dev'.
      Made block copy weirdness for XScale dependent on XScale arch flag.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_126'
  11. 30 Nov, 2002 1 commit
    • Ben Avison's avatar
      Commit of kernel as featured in release 5.00. · 9664c93b
      Ben Avison authored
        Lots of changes since last version, at least the following:
        * Updated OS timestamp, removed alpha status
        * Negative INKEY OS version changed to &AA
        * GraphicsV is now alocated vector number &2A
        * ROM moved up to &FC000000
        * Max application slot increased to 512 Mbytes (for now)
        * Max size of RMA increased to 256 Mbytes
        * RMA is now first-created dynamic area (so it gets lowest address after
          top of application slot)
        * OS_Memory 10 reimplemeted
        * New OS_ReadSysInfo 6 values 18-22 added
        * OS_ReadSysInfo 8 gains flag bit to indicate soft power-off
        * Misc internal top-bit-set-address fixes
        * *ChangeDynamicArea can take sizes in megabytes or gigabytes
        * Magic word "&off" in R0 passed to OS_Reset powers down if possible
        * Added acceleration: block copy; CLS; text window scroll up; rectangle
        * Disabled LED flashing in page mode (liable to crash)
        * Masked sprite plot and VDU 5 text avoids reading the screen if possible
        * Framestore made USR mode accessible
        * Fix for VDU 5,127 bug - now relies on font definitions being in extreme
          quarters of memory, rather than bottom half
        * Allocated 64-bit OS_Convert... SWIs
        * IIC errors use allocated error numbers
        * Looks for Dallas RTC before Philips RTC because we're using a Philips
          NVRAM device with the same ID
        * Fix to bug that meant the oscillator in the Dallas RTC wasn't enabled
        * Default mouse type (USB) changed to allocated number
        * Ram disc max size increased to 128 Mbytes (Ursula merge) and made
          cacheable for StrongARMs (not XScale)
        * Branch through zero handler now works in USR mode, by use of a
          trampoline in the system stack to allow PC-relative register storage
        * Address exception handler changed to not use 0 as workspace
        * OS_Memory 13 extended to allow specification of cacheability and access
        * Added OS_Memory 16 to return important memory addresses
        * RISCOS_MapInIO() takes cacheable flag in bit 3, access permissions in
          bits 10 and 11, doubly-mapped flag in bit 20, and access permissions
          specified flag in bit 21
        * Bug fix in last version for application abort handlers didn't quite
          work; register shuffle required
        * "Module is not 32-bit compatible" error now reports the module name
        * Default configured language changed from 10 to 11 (now Desktop again)
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_51'
  12. 07 Oct, 2002 1 commit
  13. 21 Nov, 2000 1 commit
    • Stewart Brodie's avatar
      32-bit kernels will refuse to initialise non 32-bit modules. · dbc48c98
      Stewart Brodie authored
        The kernel will examine all modules that it is requested to initialise
          and will refuse to initialise any module without a module flags word
          entry in its module header or with bit 0 the first flags word being
          clear (bit 0 being ModuleFlag_32bit)
        Error message added to all the messages files.
        New error block added to message counting block.  The Non-32-bit module
          message is not a cached error message, though.
        Tested in 32-bit Lazarus build.
      Version 5.38. Tagged as 'Kernel-5_38'
  14. 16 Oct, 2000 1 commit
  15. 27 Jun, 2000 2 commits
  16. 04 Apr, 2000 1 commit
    • Kevin Bracey's avatar
      32-bit Kernel. · b4016e9c
      Kevin Bracey authored
        The Kernel will now compile to produce a pure 32-bit system if No26bitCode is
        set to TRUE.
        If No26bitCode is FALSE, then the Kernel will be a standard 26-bit Kernel,
        although some internal changes have taken place to minimise compile
        switches between the two cases. See Docs.32bit for more technical info.
        The hardest part was the flood-fill...
      Other changes:
        Pointer shape changes now take place on the next VSync, rather than actually
        WAITING for the VSync. Turning the Hourglass on shouldn't slow your machine
        down by 5% now :)
        Lots of really crusty pre-IOMD code removed.
        Tested in 32 and 26-bit forms in a limited desktop build. Basically, this
        will need to see a lot of use to iron out difficulties. I'd like anyone who
        has a non-frozen project to at least attempt using this Kernel.
      Version 5.23. Tagged as 'Kernel-5_23'
  17. 01 Oct, 1998 1 commit
    • Kevin Bracey's avatar
      Following changes folded in from the start of the Ursula branch: · 4a34da4f
      Kevin Bracey authored
      CPU type messages internationalised.
      "Unknown OS_PlatformFeatures reason code" internationalised.
      RunningOnEmul flag tweaked.
      MorrisIDString conditional removed.
      New modules added to SWI list at the end of the chain, on grounds that
      the first-registered modules are probably more important.
      *ChangeDynamicArea moved into UtilityModule from TaskManager.
      Version 4.65. Tagged as 'Kernel-4_65'
  18. 30 Sep, 1998 1 commit
    • Kevin Bracey's avatar
      Spinner branch merged. · 5ba3f5db
      Kevin Bracey authored
      Bandwidth limit for 7500FE fixed.
      RO371Timings flag set to :LNOT:STB
      Version 4.64. Tagged as 'Kernel-4_64'
  19. 05 Nov, 1996 1 commit