1. 26 Jan, 2014 1 commit
    • Robert Sprowson's avatar
      Add support for LDRSB to data abort handler · f6c764dd
      Robert Sprowson authored
      ARM600:
      Decode LDRSB, do the sign extend, and fault all the other loads and stores not understood.
      VMSAv6:
      As the loads and stores not understood are now vetted properly, it should be safe to UseProcessTransfer (previously they'd have been disassembled incorrectly).
      Paste in LDRSB code from ARM600.
      Fix dubious looking access of CurrentGraphicsVDriver from WsPtr.
      
      Tested briefly on StrongARM.
      
      Version 5.35, 4.79.2.209. Tagged as 'Kernel-5_35-4_79_2_209'
      f6c764dd
  2. 15 Dec, 2013 1 commit
    • Jeffrey Lee's avatar
      Assorted GraphicsV improvements · 694750de
      Jeffrey Lee authored
      Detail:
        This set of changes:
        * Adds basic support for multiple GraphicsV drivers, by way of some new OS_ScreenMode reason codes for registering/deregistering, selecting and enumerating drivers (11, 64-68)
        * Tidies up handling of HAL video calls so that the HAL calls will be transformed into a bona fide GraphicsV driver if they're implemented
        * Changes handling of 16bpp gamma table entries so that they're sent to GraphicsV in a generic form instead of in a VIDC-specific form
        * Adds a new GraphicsV call and defines new VIDC list items to allow GraphicsV drivers to utilise the new pixel formats
        File changes:
        * h/VIDCList, hdr/VIDCList, Makefile - Add new header export containing VIDC list type 3 definitions, to avoid repeated definitions in other components
        * Resources/UK/Messages - Add new GraphicsV/OS_ScreenMode error strings and some missing processor type strings
        * hdr/KernelWS - Clean up some pre-GraphicsV definitions, and add new workspace locations for storing the current GraphicsV driver number and the driver list
        * hdr/Options - Remove obsolete InverseTextTransparency option
        * hdr/VduExt - Add VDU variable 192 for storing GraphicsV driver number (same as ROL's VideoV driver number). Remove old 'Flag_*' mode flag definitions (use new 'ModeFlag_*' defintions instead). Add new OS_ScreenMode reason codes.
        * s/ARM600, s/VMSAv6, s/vdu/vdu23, s/vdu/vdugrafa, s/vdu/vdugrafd, s/vdu/vdupalxx, s/vdu/vdupointer, s/vdu/vduwrch - Strip out pre-GraphicsV code. Update GraphicsV code to use correct driver number.
        * s/ArthurSWIs - Pass the default GraphicsV claimant the VduDriverWorkSpace instead of ZeroPage
        * s/Getall - Add Hdr:VIDCList and s/vdu/VduGrafHAL to list of GETs
        * s/NewIRQs - Remove HAL VSync IRQ initialisation, is now handled by grafvhal. Remove old HAL VsyncIRQ entry point, all VSyncs are now handled by VsyncIRQ_ExtEntry.
        * s/PMF/osbyte - Stop OS_Byte 19 waiting forever if no video driver is active
        * s/PMF/osinit - Remove HAL VSync IRQ initialisation, is now handled by grafvhal
        * s/vdu/vducursoft - Use new workspace variable names and flag names
        * s/vdu/vdudecl - Remove old HALDAG_* definitions, GVDAG_* definitions are used instead. Add definition of the per-driver workspace structure and flags.
        * s/vdu/vdudriver - Remove pre-GraphicsV code. Update InitialiseMode to check for and initialise a HAL driver. Use cached driver features word in a few places instead of calling GraphicsV each time. Update PalIndexTable to disable VIDC mangling of 16bpp gamma tables.
        * s/vdu/vdugrafv, s/vdu/vdugrafhal - HAL<->GraphicsV code split off into its own file (vdugrafhal). Default GraphicsV claimant now only deals with VSync events for the active driver.
        * s/vdu/vdumodes - Get rid of old VIDC List type 3 definiton; now in hdr/VIDCList
        * s/vdu/vduswis - Added OS_ScreenMode reason codes 11 and 64-68 for registering, deregistering, selecting and enumerating GraphicsV drivers. Update mode set code to not bother checking if the driver supports the pixel format; instead we assume that the driver's vet mode call will do the check for us.
      Admin:
        Tested in Tungsten, IOMD, OMAP3 & BCM2835 ROMs
        Requires HdrSrc-2_38 and updated video driver modes
      
      
      Version 5.35, 4.79.2.203. Tagged as 'Kernel-5_35-4_79_2_203'
      694750de
  3. 28 Mar, 2013 1 commit
    • Jeffrey Lee's avatar
      Teach the kernel about different memory attributes · c40b2dba
      Jeffrey Lee authored
      Detail:
        Briefly, this set of changes:
        * Adjusts PhysRamTable so that it retains the flags passed in by the HAL from OS_AddRAM (by storing them in the lower 12 bits of the size field)
        * Sorts the non-VRAM entries of PhysRamTable by speed and DMA capability, to ensure optimal memory allocation during OS startup.
        * Adjust the initial memory allocation logic to allow the cursor/sound chunk and HAL noncacheable workspace to come from DMA capable memory
        * Extends OS_Memory 12 to accept a 'must be DMA capable' flag in bit 8 of R0. This is the same as available in ROL's OS.
        * Extends OS_DynamicArea 0 to allow the creation of dynamic areas that automatically allocate from DMA capable memory. In ROL's OS this was done by setting bit 12 of R4, but we're using bits 12-14 for specifying the cache policy, so instead bit 15 is used.
        * Fixes OS_ReadSysInfo 6 to return the correct DevicesEnd value now that the IRQ/device limit is computed at runtime
        File changes:
        * hdr/OSEntries - Add definitions of the various flags passed to OS_AddRAM by the HAL. Add a new flag, NoDMA, for memory which can't be used for DMA.
        * hdr/KernelWS - Tidy PhysRamTable definition a bit by removing all the DRAM bank definitions except the first - this makes it easier to search for code which is interacting with the table. Remove VRAMFlags, it's redundant now that the flags are kept in the table. Add DMA allocation info to InitWs.
        * s/AMBControl/memmap - Updated to mask out the flags from PhysRamTable when reading RAM block sizes.
        * s/ARM600 - Strip out a lot of IOMD specific pre-HAL code.
        * s/ChangeDyn - Updated to cope with the flags stored in PhysRamTable. Implement support for DMA-capable dynamic areas. Rewrite InitDynamicAreas to insert pages into the free pool in the right order so that the fastest memory will be taken from it first.
        * s/GetAll, s/Middle - Fix OS_ReadSysInfo 6 to return the correct HAL-specific DevicesEnd value
        * s/HAL - Significant rework of initial RAM allocation code to allow the kernel workspace to come from the fastest DMA incapable RAM, while also allowing allocation of DMA capable memory for HAL NCNB workspace & kernel cursor/sound chunks. ClearPhysRAM rewritten as part of this.
        * s/MemInfo - Updated to cope with the flags stored in PhysRamTable. Add support for the new OS_Memory 12 flag. Update OS_Memory 7 to not assume PhysRamTable entries are sorted in address order, and rip out the old pre-HAL IOMD implementation.
        * s/NewReset - Remove GetPagesFromFreePool option, assume TRUE (as this has been the case for the past 10+ years). Revise a few comments and strip dead code. Update to cope with PhysRamTable flags.
        * s/VMSAv6 - Remove a couple of unused definitions
        * s/vdu/vdudriver - Update to cope with PhysRamTable flags
      Admin:
        Tested in Kinetic RiscPC ROM softload, Iyonix softload, & OMAP3
      
      
      Version 5.35, 4.79.2.186. Tagged as 'Kernel-5_35-4_79_2_186'
      c40b2dba
  4. 28 Oct, 2012 1 commit
    • Robert Sprowson's avatar
      Review of Internation switch · d58ce177
      Robert Sprowson authored
      Variously the call to TranslateError was either followed (outside the switch) by an unnecessary SETV, or missing SETV for the non international case.
      Added DMA controller HAL device for IOMD.
      
      Version 5.35, 4.79.2.174. Tagged as 'Kernel-5_35-4_79_2_174'
      d58ce177
  5. 20 Jul, 2012 1 commit
  6. 04 Jul, 2012 1 commit
    • Robert Sprowson's avatar
      Make GraphicsV_IICOp more consistent · c671badb
      Robert Sprowson authored
      No accepts  r0 = b31-24 set 0
                       b23-16 fully qualified IIC address
                       b15-0  starting offset
                  r1 = buffer pointer
                  r2 = number of bytes to tranfer
                  r4 = b31-24 display number
                       b23-16 head
                       b15-0  reason code (=14)
      Now returns r0 = result codes as per HAL_IICTransfer()
                  r1 = buffer pointer incremented by number of bytes transferred
                  r2 = number of bytes *not* transferred
                  r4 = 0
      Removed '_' after Video in entry numbers to be consistent with other HAL entry naming, and HAL_VideoFlybackDevice.
      Added IICStatus return numbers to Hdr:HALEntries.
      Stop calling HAL_MonitorLeadID as only IOMD implemented it - just guess VGA until the graphics driver says otherwise.
      
      Version 5.35, 4.79.2.159. Tagged as 'Kernel-5_35-4_79_2_159'
      c671badb
  7. 18 Jun, 2012 1 commit
    • Robert Sprowson's avatar
      Make OS_Memory 8 return more correct values · b6cfcbdf
      Robert Sprowson authored
      The only fake result now is the hard ROM amount, which is hardwired to 4MB and might not be correct.
      Unrelated changes
       hdr.HALDevice: Assign a device for VIDC20.
       hdr.KernelWS: Reorder into ascending order, remove legacy addresses.
       s.ARM600: Move PhysSpaceSize inside :LNOT:HAL switch.
       s.Kernel: Move PhysSpaceSize inside :LNOT:HAL switch.
      
      Version 5.35, 4.79.2.153. Tagged as 'Kernel-5_35-4_79_2_153'
      b6cfcbdf
  8. 21 May, 2012 1 commit
    • Robert Sprowson's avatar
      Make Mike's macros permanent. · 2c9aad90
      Robert Sprowson authored
      While the HAL and kernel were being split some temporary macros were used for the bits being worked on, after 12 years of use they're probably safe to adopt.
      mjsCallHAL -> CallHAL; mjsAddressHAL -> AddressHAL; mjsHAL -> HAL.
      OS_VIDCDividerSWI code now always does NoSuchSWI (had been switched out previously).
      File vduhint.s no longer assembled (was empty).
      
      
      Version 5.35, 4.79.2.150. Tagged as 'Kernel-5_35-4_79_2_150'
      2c9aad90
  9. 15 Apr, 2012 1 commit
    • Jeffrey Lee's avatar
      OS_ChangeDynamicArea performance optimisations · 5e11e665
      Jeffrey Lee authored
      Detail:
        s/ChangeDyn:
          - Apply various optimisations to OS_ChangeDynamicArea to reduce the execution time when performing large grows/shrinks.
          - Optimisations can be toggled on/off with FastCDA_* flags for debugging.
          - On a 1GHz 512MB BB-xM, the initial *FreePool call now takes 0.15s instead of 13.46s. On a 512MB Iyonix the time has dropped from 1.18s to 0.23s.
          - Growing screen memory (on BB-xM) has also seen significant gains - between 2x and 4x speedup, depending on what state the source pages are in.
          - Added/updated documentation for a few functions and made more use of ROUTs for safety
        s/ARM600, s/VMSAv6:
          - Update BangCamUpdate, etc. to add support for the PageFlags_Unsafe flag that OS_ChangeDynamicArea uses to bypass cache/TLB maintenance in some situations
          - Avoid BangCamUpdate calling BangL2PT to map out the page if the page isn't mapped in (avoids unnecessary cache/TLB flush)
        s/ArthurSWIs:
          - Add extra ASSERT for safety
        s/AMBcontrol/memory
          - Fix incorrect assumption that the usable size of a heap block is always 8 less than the value stored in the header. Even with the old 8 byte aligned allocations the usable size will always be 4 bytes less than the value in the header. This code would have resulted in some slight memory wasteage, as AMBcontrol will have always tried growing the block four bytes bigger than needed.
      Admin:
        Tested on Iyonix & BB-xM
      
      
      Version 5.35, 4.79.2.146. Tagged as 'Kernel-5_35-4_79_2_146'
      5e11e665
  10. 27 Nov, 2011 1 commit
    • Robert Sprowson's avatar
      Reindent Arthur2. · 2d883d8d
      Robert Sprowson authored
      Expand tabs.
      Swap DCI for instructions now Objasm 4 is out.
      Symbols for FSControl_CAT/RUN/OPT changed to non Arthur definitions.
      Still boots on IOMD class, no other testing.
      
      Version 5.35, 4.79.2.124. Tagged as 'Kernel-5_35-4_79_2_124'
      2d883d8d
  11. 08 Aug, 2011 1 commit
    • Jeffrey Lee's avatar
      Add zero page relocation support · 2247d8e9
      Jeffrey Lee authored
      Detail:
        A whole mass of changes to add high processor vectors + zero page relocation support to the Cortex branch of the kernel
        At the moment the code can only cope with two ZeroPage locations, &0 and &FFFF0000. But with a bit more tweaking those restrictions can probably be lifted, allowing ZeroPage to be hidden at almost any address (assuming it's fixed at compile time). If I've done my job right, these restrictions should all be enforced by asserts.
        There's a new option, HiProcVecs, in hdr/Options to control whether high processor vectors are used. When enabling it and building a ROM, remember:
        * FPEmulator needs to be built with the FPEAnchor=High option specified in the components file (not FPEAnchorType=High as my FPEmulator commit comments suggested)
        * ShareFS needs unplugging/removing since it can't cope with it yet
        * Iyonix users will need to use the latest ROOL boot sequence, to ensure the softloaded modules are compatible (OMAP, etc. don't really softload much so they're OK with older sequences)
        * However VProtect also needs patching to fix a nasty bug there - http://www.riscosopen.org/tracker/tickets/294
        The only other notable thing I can think of is that the ProcessTransfer code in s/ARM600 & s/VMSAv6 is disabled if high processor vectors are in use (it's fairly safe to say that code is obsolete in HAL builds anyway?)
        Fun challenge for my successor: Try setting ZeroPage to &FFFF00FF (or similar) so its value can be loaded with MVN instead of LDR. Then use positive/negative address offsets to access the contents.
        File changes:
        - hdr/ARMops - Modified ARMop macro to take the ZeroPage pointer as a parameter instead of 'zero'
        - hdr/Copro15ops - Corrected $quick handling in myISB macro
        - hdr/Options - Added ideal setting for us to use for HiProcVecs
        - s/AMBControl/allocate, s/AMBControl/growp, s/AMBControl/mapslot, s/AMBControl/memmap, s/AMBControl/service, s/AMBControl/shrinkp, s/Arthur2, s/Arthur3, s/ArthurSWIs, s/ChangeDyn, s/ExtraSWIs, s/HAL, s/HeapMan, s/Kernel, s/MemInfo, s/Middle, s/ModHand, s/MoreSWIs, s/MsgCode, s/NewIRQs, s/NewReset, s/Oscli, s/PMF/buffer, s/PMF/IIC, s/PMF/i2cutils, s/PMF/key, s/PMF/mouse, s/PMF/osbyte, s/PMF/oseven, s/PMF/osinit, s/PMF/osword, s/PMF/oswrch, s/SWINaming, s/Super1, s/SysComms, s/TickEvents, s/Utility, s/vdu/vdu23, s/vdu/vdudriver, s/vdu/vdugrafl, s/vdu/vdugrafv, s/vdu/vdupalxx, s/vdu/vdupointer, s/vdu/vduswis, s/vdu/vduwrch - Lots of updates to deal with zero page relocation
        - s/ARM600 - UseProcessTransfer option. Zero page relocation support. Deleted pre-HAL ClearPhysRAM code to tidy the file up a bit.
        - s/ARMops - Zero page relocation support. Set CPUFlag_HiProcVecs when high vectors are in use.
        - s/KbdResPC - Disable compilation of dead code
        - s/VMSAv6 - UseProcessTransfer option. Zero page relocation support.
      Admin:
        Tested with OMAP & Iyonix ROM softloads, both with high & low zero page.
        High zero page hasn't had extensive testing, but boot sequence + ROM apps seem to work.
      
      
      Version 5.35, 4.79.2.98.2.48. Tagged as 'Kernel-5_35-4_79_2_98_2_48'
      2247d8e9
  12. 06 Nov, 2009 1 commit
    • Jeffrey Lee's avatar
      Fix bug when creating code variables via OS_SetVarVal, remove errant line from... · e1e71002
      Jeffrey Lee authored
      Fix bug when creating code variables via OS_SetVarVal, remove errant line from s.ARM600, automatically enable alignment exceptions if NoUnaligned is TRUE (Cortex branch)
      
      Detail:
        s/ARM600 - Removed an errant line that could have caused problems if the ARM600 MMU model was used with the WB_CR7_Lx cache type
        s/Arthur2 - OS_SetVarVal was failing to call XOS_SynchroniseCodeAreas after copying the code variables code block into the system heap. This has now been fixed.
        s/HAL - Alignment exceptions are now automatically enabled when the kernel is built with the NoUnaligned option turned on.
      Admin:
        Tested on rev C2 beagleboard. OS_SetVarVal fix means the Debugger module now shows the right register names instead of ofla!
      
      
      Version 5.35, 4.79.2.98.2.15. Tagged as 'Kernel-5_35-4_79_2_98_2_15'
      e1e71002
  13. 06 Mar, 2009 1 commit
    • Jeffrey Lee's avatar
      Add VMSAv6 MMU support, fixes to allow booting on beagleboard · 3d1317e7
      Jeffrey Lee authored
      Detail:
        s/ARM600 - fix to SyncCodeAreasRange to correctly read cache line length for WB_CR7_Lx caches
        s/ARMops - Cortex cache handling fixes. Enable L2 cache for Cortex.
        s/ChangeDyn - VMSAv6 support in AllocateBackingLevel2
        s/HAL - Improve RISCOS_InitARM to set/clear correct CP15 flags for ARMv6/v7. VMSAv6 support in code to generate initial page tables.
        s/NewReset - Extra DebugTX calls during OS startup. Disable pre-HAL Processor_Type for HAL builds.
        s/VMSAv6 - Main VMSAv6 MMU code - stripped down version of s/ARM600 with support for basic VMSAv6 features.
        hdr/Options - Use VMSAv6 MMU code, not ARM600. Disable ARM6support since current VMSAv6 code will conflict with it.
      Admin:
        Tested basic OS functionality under qemu-omap3 and revision B6 beagleboard.
      
      
      Version 5.35, 4.79.2.98.2.3. Tagged as 'Kernel-5_35-4_79_2_98_2_3'
      3d1317e7
  14. 06 May, 2004 1 commit
    • Kevin Bracey's avatar
      * HAL can choose to limit amount of screen memory to allocate · 0f6941a8
      Kevin Bracey authored
        [Not fully implemented - for now leaves at least 16MB free if only
        one RAM area; was 1MB].
      * Added HAL_USBControllerInfo, HAL_MonitorLeadID and HAL_Video_Render.
      * Added HAL->OS call OS_IICOpV.
      * OS_MMUControl now allows independent control of I and C bits.
      * Added facility to deactivate keyboard debounce (magic word "NoKd" in
        R2 in KeyV 0).
      * Fixed problem with RAM amounts not a multiple of 4MB.
      * Supremacy bit (in VDU 19) now sets all 8 bits of supremacy.
      * Added PaletteV 14 (reads gamma tables).
      * Added Supremacy transfer functions (like gamma correction, but for
        supremacy). Allows easy global supremacy effects in a mode-independent
        fashion. Controlled with PaletteV 15,16.
      * Added modes 50-53 (320x240, 1,2,4,8bpp). Intended for small LCD.
      * Added 13.5kHz versions of TV modes (selected by Hdr:Machine).
      * Upped desktop version to 5.06.
      
      Version 5.35, 4.79.2.66. Tagged as 'Kernel-5_35-4_79_2_66'
      0f6941a8
  15. 30 Nov, 2002 1 commit
    • Ben Avison's avatar
      Commit of kernel as featured in release 5.00. · 9664c93b
      Ben Avison authored
      Detail:
        Lots of changes since last version, at least the following:
        * Updated OS timestamp, removed alpha status
        * Negative INKEY OS version changed to &AA
        * GraphicsV is now alocated vector number &2A
        * ROM moved up to &FC000000
        * Max application slot increased to 512 Mbytes (for now)
        * Max size of RMA increased to 256 Mbytes
        * RMA is now first-created dynamic area (so it gets lowest address after
          top of application slot)
        * OS_Memory 10 reimplemeted
        * New OS_ReadSysInfo 6 values 18-22 added
        * OS_ReadSysInfo 8 gains flag bit to indicate soft power-off
        * Misc internal top-bit-set-address fixes
        * *ChangeDynamicArea can take sizes in megabytes or gigabytes
        * Magic word "&off" in R0 passed to OS_Reset powers down if possible
        * Added acceleration: block copy; CLS; text window scroll up; rectangle
          fill
        * Disabled LED flashing in page mode (liable to crash)
        * Masked sprite plot and VDU 5 text avoids reading the screen if possible
        * Framestore made USR mode accessible
        * Fix for VDU 5,127 bug - now relies on font definitions being in extreme
          quarters of memory, rather than bottom half
        * Allocated 64-bit OS_Convert... SWIs
        * IIC errors use allocated error numbers
        * Looks for Dallas RTC before Philips RTC because we're using a Philips
          NVRAM device with the same ID
        * Fix to bug that meant the oscillator in the Dallas RTC wasn't enabled
        * Default mouse type (USB) changed to allocated number
        * Ram disc max size increased to 128 Mbytes (Ursula merge) and made
          cacheable for StrongARMs (not XScale)
        * Branch through zero handler now works in USR mode, by use of a
          trampoline in the system stack to allow PC-relative register storage
        * Address exception handler changed to not use 0 as workspace
        * OS_Memory 13 extended to allow specification of cacheability and access
          privileges
        * Added OS_Memory 16 to return important memory addresses
        * RISCOS_MapInIO() takes cacheable flag in bit 3, access permissions in
          bits 10 and 11, doubly-mapped flag in bit 20, and access permissions
          specified flag in bit 21
        * Bug fix in last version for application abort handlers didn't quite
          work; register shuffle required
        * "Module is not 32-bit compatible" error now reports the module name
        * Default configured language changed from 10 to 11 (now Desktop again)
      
      Version 5.35, 4.79.2.51. Tagged as 'Kernel-5_35-4_79_2_51'
      9664c93b
  16. 28 Oct, 2002 1 commit
    • Ben Avison's avatar
      In the No26bitCode case (ie when abort handlers are entered in ABT32 mode), if... · 982426fe
      Ben Avison authored
      In the No26bitCode case (ie when abort handlers are entered in ABT32 mode), if lazy task swapping was enabled and a data abort occurred that was not a page translation fault, then the code in AMB_LazyFixUp to map in the whole application slot was being circumvented, leading to problems for abort handlers in application space because r14_abt was corrupted by any abort due to accessing the abort handler itself. The test of the FSR (to compensate for the FAR being unusable for external aborts) which prompted the circumvention has therefore been moved inside AMB_LazyFixup.
      
      Also now preserves the FSR and FAR across AMB_LazyFixUp, so they are now
      visible from application abort handlers if desired.
      
      Version 5.35, 4.79.2.50. Tagged as 'Kernel-5_35-4_79_2_50'
      982426fe
  17. 07 Oct, 2002 1 commit
  18. 11 Jun, 2001 1 commit
  19. 22 May, 2001 1 commit
    • Mike Stephens's avatar
      Reimplement Lazy task swapping, an amusing idea from Ursula, would have done... · bdc4f843
      Mike Stephens authored
      Reimplement Lazy task swapping, an amusing idea from Ursula, would have done it sooner but couldn't be bothered (humour).
      
      Currently activates for all ARMs flagged as base-restored
      abort model. No handling of eg. StrongARM pre-revT bug, but
      then the kernel no longer runs on StrongARM (progress).
      Still some details to fix: all aborts in current app space
      assumed to be missing pages, but this must be fixed to
      handle abort code in app space, things like debuggers
      marking code read only.
      
      Plus, small fixes:
        OS_Memory 8 returns vaguely useful info for RAM,VRAM
        in HAL build (temporary partial implementation)
        Broken handling of old BBC commands with (fx,tv etc)
        with no spaces fixed (fudgeulike code from Ursula,
        now 32-bit).
      
      Version 5.35, 4.79.2.31. Tagged as 'Kernel-5_35-4_79_2_31'
      bdc4f843
  20. 13 Feb, 2001 1 commit
  21. 23 Jan, 2001 1 commit
    • Mike Stephens's avatar
      fix for IMB_range · 1e16da0c
      Mike Stephens authored
      Detail:
        ARM600.s
      Admin:
        (highlight level of testing that has taken place)
        (bugfix number if appropriate)
      1e16da0c
  22. 12 Jan, 2001 1 commit
    • Mike Stephens's avatar
      kernel now attempts to substitute video mode numbers in face of h/w with... · 6a293f53
      Mike Stephens authored
      kernel now attempts to substitute video mode numbers in face of h/w with limited bits-per-pixel support (not tested yet)
      
      HAL_API document added - early draft only, of interest to those
      writing or modifying HALs for new h/w
      ARMop_API document added - early draft only, of interest only
      to those modifying kernel to support new ARM cores
      *** polite comments on HAL_API welcome ***
      
      Version 5.35, 4.79.2.15. Tagged as 'Kernel-5_35-4_79_2_15'
      6a293f53
  23. 09 Jan, 2001 1 commit
  24. 10 Nov, 2000 1 commit
  25. 23 Oct, 2000 1 commit
  26. 20 Oct, 2000 1 commit
  27. 16 Oct, 2000 1 commit
  28. 09 Oct, 2000 1 commit
  29. 06 Oct, 2000 1 commit
  30. 05 Oct, 2000 3 commits
  31. 03 Oct, 2000 1 commit
  32. 02 Oct, 2000 1 commit
  33. 15 Sep, 2000 1 commit
    • Kevin Bracey's avatar
      * Converted to building with ObjAsm (but still a single object file using ORG). · 49836a59
      Kevin Bracey authored
      * Added ARM_IMB and ARM_IMBRange SWIs as recommended by ARMv5.
      * Some early prototype HAL bits popped in - a lot of source restructuring still
        to come.
      * New debug target creates an AIF image with debug information, and translates
        this into an ASCII object file for the 16702B logic analyser.
      
      Version 5.35, 4.79.2.1. Tagged as 'Kernel-5_35-4_79_2_1'
      49836a59
  34. 13 Apr, 2000 1 commit
    • Kevin Bracey's avatar
      * Run-time emulator detection added (no need for separate images). Needs an · 36ba4cb5
      Kevin Bracey authored
        RPCEm update.
      * Register allocation in default ErrorV handler fixed - problems occured when
        callbacks were triggered on way out.
      * OS_Byte 19 didn't manipulate interrupt disable flag correctly in 26-bit
        builds.
      * Stray bit of debugging left in sprite code many years ago removed.
      
      Version 5.23. Not tagged
      36ba4cb5
  35. 04 Apr, 2000 1 commit
    • Kevin Bracey's avatar
      32-bit Kernel. · b4016e9c
      Kevin Bracey authored
      Details:
        The Kernel will now compile to produce a pure 32-bit system if No26bitCode is
        set to TRUE.
        If No26bitCode is FALSE, then the Kernel will be a standard 26-bit Kernel,
        although some internal changes have taken place to minimise compile
        switches between the two cases. See Docs.32bit for more technical info.
      
        The hardest part was the flood-fill...
      
      Other changes:
        Pointer shape changes now take place on the next VSync, rather than actually
        WAITING for the VSync. Turning the Hourglass on shouldn't slow your machine
        down by 5% now :)
      
        Lots of really crusty pre-IOMD code removed.
      
      Admin:
        Tested in 32 and 26-bit forms in a limited desktop build. Basically, this
        will need to see a lot of use to iron out difficulties. I'd like anyone who
        has a non-frozen project to at least attempt using this Kernel.
      
      Version 5.23. Tagged as 'Kernel-5_23'
      b4016e9c
  36. 02 Feb, 2000 1 commit
    • Stewart Brodie's avatar
      Added OS_ReadSysInfo 6, 7 and 8 from Ursula branch. · b85d7d81
      Stewart Brodie authored
        Ensured that M_Phoebe builds set UtilityModule version to 4.00
      Detail:
        The softload utility relies on the existence of the extra reason codes
          to OS_ReadSysInfo introduced in Ursula.  The main kernel now supports
          these too (they are simply interfaces to read kernel capabilities and
          configuration - eg. addresses and sizes of UND and SVC mode stacks)
        Avoid OS_ReadSysInfo 9 - ROL have used it for reading the ROM personality
          information (and it's not in our kernel)
        Added some of the new macros into Copro15ops required by the ABT dump
          area code (returned by OS_ReadSysInfo 7) and added the code into ARM600
          to store abort information there.
      Admin:
        Required by softload utility for Ursula builds.
        Tested on Risc PC.
      
      Version 5.15. Tagged as 'Kernel-5_15'
      b85d7d81
  37. 29 Sep, 1999 1 commit
    • Kevin Bracey's avatar
      * Meaning of FEIOSpeedHalf was accidentally inverted. · fb297c9b
      Kevin Bracey authored
      * Wasn't allowing writes to most of EEPROM.
      * Old prototype OS_SetTime SWI code removed.
      * MPEGPoduleNTSCNotPALMask option support removed to simplify things a bit.
      * Now can cope with a system with a PAL/NTSC link, but no monitor detect line.
      * Default PAL & NTSC modes now always 12 & 46 respectively.
      * Kernel now knows about monitor type 8 (NTSC) - modes 44-46 (640x200) are
        available.
      * STB/NC CMOS test removed from POST pending further investigation.
      
      Version 4.90. Tagged as 'Kernel-4_90'
      fb297c9b
  38. 23 Sep, 1999 1 commit