1. 31 Jul, 2011 1 commit
    • Jeffrey Lee's avatar
      Update the method the HAL kernel uses to determine the UtilityModule & ROM dates · e249f5da
      Jeffrey Lee authored
        Three main changes:
        * On odd-numbered (i.e. development) versions of the module, the UtilityModule will now take its date from the VersionNum file instead of using a hard-coded date
        * All build versions now look for the new "extended ROM footer" (as created by romlinker 0.04+) at the end of the ROM image and use it to determine the ROM build date for return by OS_ReadSysInfo 9,2. Failing to find the build date in the footer will cause OS_ReadSysInfo 9,2 to return 0.
        * On odd-numbered versions, OS_Byte 0 will now use the ROM build date (as found in the extended footer) to generate the error block that's returned to the user. This seems OK as the PRM describes OS_Byte 0 as returning the "creation date of the operating system". Plus it's a convenient way of getting the ROM build date into the Switcher, since the switcher uses OS_Byte 0. If the extended footer can't be found (or if the string isn't initialised yet, e.g. before Service_PostInit) the code falls back to a hard-coded string containing the date from the VersionNum file.
        File changes:
        Makefile - Updated to not create the obsolete Time+Date file (previously used for the ROM build date)
        Version - Use date from VersionNum file for development builds
        hdr/Options - New UseNewFX0Error variable/option to make it easy to check which OS_Byte 0 variant should be enabled
        hdr/KernelWS - Added new string buffers & extended ROM footer pointer to workspace
        s/Middle - Updated OS_ReadSysInfo 9 code, and added utility functions for searching the extended ROM footer for certain tags
        s/NewReset - Added a couple of calls to initialise the new string buffers just prior to Service_PostInit. This is required since OS_Byte/OS_ReadSysInfo shouldn't enable interrupts, but date conversion relies on the Territory module, which may enable interrupts.
        s/PMF/osbyte - Updated OS_Byte 0 code
        Tested in Tungsten ROM, with and without the extended footer present.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_115'
  2. 18 Jul, 2011 1 commit
    • Jeffrey Lee's avatar
      Update list of OS_Memory 9 controllers · e339bdd5
      Jeffrey Lee authored
        s/MemInfo - List of OS_Memory 9 controllers now updated to include details of the ones that ROL are using, along with which numbers should/shouldn't be safe for us to expand into in the future.
        Tested in ROM softload on RiscPC
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_114'
  3. 04 Jun, 2011 1 commit
    • Jeffrey Lee's avatar
      Add hdr.Variables to C header export · 819b8458
      Jeffrey Lee authored
        Makefile - Added hdr.Variables to the C header export list
        Fixes build errors with the latest Draw module
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_113'
  4. 22 May, 2011 1 commit
  5. 20 Mar, 2010 1 commit
    • Jeffrey Lee's avatar
      Bring HAL branch of hdr/HALDevice, h/HALDevice in line with Cortex branch · ff0710fa
      Jeffrey Lee authored
        A fair number of bus/device types and IDs have been added to the Cortex branch since the branch was created.
        Now that the ClearIRQ entry has also been added, it's about time that the HAL branch was brought up to date.
        Untested, but should be fine.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_111'
  6. 20 Feb, 2010 1 commit
    • Jeffrey Lee's avatar
      Fix detection of Philips RTC/NVRAM when MaybeIIC is in use · a6492b14
      Jeffrey Lee authored
        s/PMF/i2cutils - Although the code will detect the Philips RTC correctly, it was failing to set the device size in R4, causing CMOS RAM to be misread. This change fixes that.
        Tested in IOMD HAL build on development version of RPCEmu.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_110'
  7. 02 Feb, 2010 1 commit
    • Jeffrey Lee's avatar
      Fix bug in InitCMOSCache that could cause CMOS to be errouneously reset if... · ed3cc555
      Jeffrey Lee authored
      Fix bug in InitCMOSCache that could cause CMOS to be errouneously reset if NVRAM is of type 'MaybeIIC'
        s/PMF/i2cutils - Kernel was checking if the full IIC flags word was equal to MaybeIIC instead of just checking if the Provision bits equalled MaybeIIC. Thus if any of the additional flags were set along with MaybeIIC the kernel would have skipped the probing code, skipped the IIC code, and fallen through to using the (likely unimplemented) HAL interface for initialising the NVRAM cache.
        Tested in IOMD build under RPCemu; kernel now takes the correct path for MaybeIIC + ProtectAtEnd.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_109'
  8. 19 Jan, 2010 1 commit
  9. 18 Jan, 2010 1 commit
    • John Ballance's avatar
      modified s.PMF.osword to cope with the iyonix RTC operating in BCD · 23e2c1e0
      John Ballance authored
      Also upissued to RISC OS 5.16 to release this in ROM
        (list files and functions that have changed)
      tested at Castle (JB)
        (highlight level of testing that has taken place)
        (bugfix number if appropriate)
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_107'
  10. 06 Nov, 2009 1 commit
    • Jeffrey Lee's avatar
      Fix bug when creating code variables via OS_SetVarVal (HAL branch) · 9fe47897
      Jeffrey Lee authored
        OS_SetVarVal was failing to call XOS_SynchroniseCodeAreas after copying the code variables code block into the system heap. This has now been fixed.
        Fix tested in Cortex branch on rev C2 beagleboard. Debugger module now shows the right register names instead of ofla!
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_106'
  11. 28 Oct, 2009 1 commit
    • Ben Avison's avatar
      Build fix · 62fb1997
      Ben Avison authored
        Hdr:Macros has just been changed on the trunk in such a way that you now
        need to include Hdr:CPU.Arch as well. Previously this include file was only
        referenced by the Cortex branch kernel - now mirrored on the HAL branch
        kernel too.
        Verified that IOMD ROM now builds again - should fix Tungsten ROM build too.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_105'
  12. 22 Oct, 2009 1 commit
    • Jeffrey Lee's avatar
      Fix error handling for sparse dynamic area resize operations (for main HAL branch) · d0ddc243
      Jeffrey Lee authored
        s/ChangeDyn - Swap CMP with TEQ to avoid accidental clobbering of V flag before its state is checked on return from a SWI. Errors encounterd during sparse dynamic area resize operations (OS_DynamicArea 9 & 10) should now be reported properly.
        Not tested, but the same fix has been proven to work on the Cortex branch.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_104'
  13. 07 Jun, 2009 2 commits
    • Ben Avison's avatar
      Added comment · 9e7233fb
      Ben Avison authored
        Noted reservation of IO controller type  passed to OS_Memory 9 used when
        system is running as a coprocessor. Not used by current code but we need to
        make sure that any future reservations use different numbers.
        No functional change. Brought to our attention by Rob Sprowson.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_103'
    • Ben Avison's avatar
      Build fix · 0538bbba
      Ben Avison authored
        Some users reported problems building the sources if they had other
        installations of perl on their build machine. The build system was using a
        mixture of "perl" and "<Perl$Dir>.perl" to invoke the interpreter, and
        sometimes but not always using "do" to expand system variables on the
        command line. This has now been standardised to use "do <Perl$Dir>.perl in
        all cases, and where possible, to use the makefile macro ${PERL}.
        Checked that a Tungsten build still works on a build machine with no other
        perl installation. "perl" was aliased to an error to ensure it wasn't used.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_102'
  14. 23 Apr, 2009 1 commit
    • Ben Avison's avatar
      Increased Kernel version number to 5.15. · 40949773
      Ben Avison authored
        Castle seems to have settled on an official 5.14 build, so changed our
        version to distinguish our test builds from the official one.
        No testing required
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_101'
  15. 21 Apr, 2009 1 commit
  16. 15 Apr, 2009 1 commit
  17. 22 Dec, 2008 1 commit
    • Ben Avison's avatar
      Minor kernel updates · ab08ee91
      Ben Avison authored
        * Added some documentation on previously undocumented HAL calls
        * Corrected NVMemoryFlag_Provision bitmask to match documentation
        * Bugfix: NVMemoryFlag_ProtectAtEnd flag was being ignored
        Not tested
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_98'
  18. 03 Dec, 2008 1 commit
  19. 04 Oct, 2008 1 commit
    • Ben Avison's avatar
      Merged in changes from Castle · ffe4d1b4
      Ben Avison authored
        Updated GraphicsV documentation
        Upped ROM version number - currently matches latest Castle release (5.13)
        No code change
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_96'
  20. 22 Feb, 2006 1 commit
  21. 16 Feb, 2006 1 commit
  22. 07 Oct, 2005 1 commit
  23. 24 Sep, 2005 1 commit
  24. 23 Sep, 2005 1 commit
  25. 16 Sep, 2005 1 commit
  26. 15 Sep, 2005 1 commit
    • Ben Avison's avatar
      Bugfix to *Help. · 82d4de44
      Ben Avison authored
        Internationalisation of *Help code (ie probably dating back to RISC OS 3.1)
        broke the Escape condition checking. This is particularly nasty if you
        do *Help . on a machine with slow hardware scrolling!
        Not tested.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_89'
  27. 12 Sep, 2005 1 commit
  28. 09 Jun, 2005 1 commit
  29. 18 May, 2005 1 commit
  30. 04 May, 2005 1 commit
  31. 21 Mar, 2005 1 commit
  32. 12 Nov, 2004 1 commit
    • Ben Avison's avatar
      BBE tidying. · ec70a1a4
      Ben Avison authored
        Tightened up BBE resources export, to exclude in appropriate files (this
        component has a non-standard resources directory structure).
        Tested in a Tungsten BBE build.
      Retagged, since this won't affect any existing builds.
  33. 04 Nov, 2004 2 commits
  34. 02 Nov, 2004 1 commit
    • John Ballance's avatar
      several mode: · 208da9fd
      John Ballance authored
           1: default ticker based vsync generated whenever no device present to do so
           2: graphicsv handling and spec updated to use the hi 8 bits in the
              reason code (R4) to define the display number. Kernel only knows
              of display 0
           tested castle  castle added ip
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_81'
  35. 29 Oct, 2004 2 commits
  36. 13 Oct, 2004 1 commit
    • Ben Avison's avatar
      Bugfix and header change. · 9a6346d8
      Ben Avison authored
        * I noticed in passing that the default exception handlers were broken for
          non-IOMD machines if the exception was raised in FIQ mode - unless you
          had a very large application slot, then the machine would lock up. Now
          properly HAL-ised.
        * Added a new event number, allocated for PRISM use back in June.
        Not tested. However, it can't make the situation any worse!
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_78'
  37. 06 Oct, 2004 1 commit
    • Ben Avison's avatar
      Change to calling conditions of UnthreadV. · 5e89ff87
      Ben Avison authored
        Previously, UnthreadV was only called when the IRQsema chain was empty, the
        link for the just-completed interrupt having just been removed. However,
        the information in the link is necessary to allow OS_Heap to be called from
        UnthreadV context, and patching up IRQsema within the UnthreadV handler
        prevents the implementation of a prioritised threading scheme. As a result,
        we must call UnthreadV every time the interrupt dispatch unthreads, and
        leave it up to the UnthreadV handler to distinguish between return to
        thread context and return from a nested interrupt handler.
        Will require some sort of patch to enable heap-safe prioritised threading
        on RISC OS-STB 5.0.0 or RISC OS 5.07, the only two released OSes with the
        previous UnthreadV behaviour.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_77'