1. 10 May, 2009 1 commit
    • Jeffrey Lee's avatar
      Assorted kernel fixes for ARMv6/ARMv7 · ca8f36f5
      Jeffrey Lee authored
        s/ARMops - Fix IMB_Range_WB_CR7_Lx to clean the correct number of cache lines
        s/HAL - Change CP15 control register flags so unaligned loads are enabled on ARMv6 (to simplify support for ARMv7 where unaligned loads are always enabled, and to match the behaviour expected by the example code in Hdr:CPU.Arch)
        s/AMBControl/memmap - Make AMB_LazyFixUp use the correct L2PT protection flags depending on ARM600/VMSAv6 MMU model. Also guard against problems caused by future L2PT flag changes.
        s/vdu/vdugrafj - Fix previously undiscovered 32bit incompatability in GetSprite (OS_SpriteOp 14/16)
        Tested on rev C2 beagleboard
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_98_2_5'
  2. 23 Apr, 2009 1 commit
    • Jeffrey Lee's avatar
      Fix kernel cache clean/invalidate operations for Cortex CPUs · d28235ea
      Jeffrey Lee authored
        s/ARMops - Fix set/way-based cache ops for cache type WB_CR7_Lx to iterate sets/ways/cache levels properly
        s/HAL - Fix HAL_InvalidateCache_ARMvF to iterate sets/ways/cache levels properly
        Tested on rev C2 beagleboard
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_98_2_4'
  3. 06 Mar, 2009 1 commit
    • Jeffrey Lee's avatar
      Add VMSAv6 MMU support, fixes to allow booting on beagleboard · 3d1317e7
      Jeffrey Lee authored
        s/ARM600 - fix to SyncCodeAreasRange to correctly read cache line length for WB_CR7_Lx caches
        s/ARMops - Cortex cache handling fixes. Enable L2 cache for Cortex.
        s/ChangeDyn - VMSAv6 support in AllocateBackingLevel2
        s/HAL - Improve RISCOS_InitARM to set/clear correct CP15 flags for ARMv6/v7. VMSAv6 support in code to generate initial page tables.
        s/NewReset - Extra DebugTX calls during OS startup. Disable pre-HAL Processor_Type for HAL builds.
        s/VMSAv6 - Main VMSAv6 MMU code - stripped down version of s/ARM600 with support for basic VMSAv6 features.
        hdr/Options - Use VMSAv6 MMU code, not ARM600. Disable ARM6support since current VMSAv6 code will conflict with it.
        Tested basic OS functionality under qemu-omap3 and revision B6 beagleboard.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_98_2_3'
  4. 21 Feb, 2009 1 commit
    • Jeffrey Lee's avatar
      Add support for Cortex cache type. Extend ARM_Analyse to, where appropriate,... · ad9cdf41
      Jeffrey Lee authored
      Add support for Cortex cache type. Extend ARM_Analyse to, where appropriate, use CPU feature registers to identify CPU capabilities.
        s/ARMops - Support for Cortex multi-level cache (CT_ctype_WB_CR7_Lx). New ARM_Analyse_Fancy to identify CPU capabilities using feature registers.
        s/HAL - Modify pre-ARMop cache code to handle Cortex-syle caches.
        s/MemInfo - Replace ARM_flush_TLB macro call with appropriate ARMop to provide Cortex compatability
        hdr/ARMops - Update list of ARM architectures
        hdr/CoPro15ops - Deprecate ARM_flush_* macros for HAL kernels, as they are no longer capable of flushing all cache types. ARMops should be used instead.
        hdr/KernelWS - Add storage space for multi-level cache properties required for new cache cleaning code.
        Tested under qemu-omap3. Still unable to verify on real hardware due to lack of appropriate MMU code. However new OMAP3 HAL code that uses similar cache management functions appears to work fine on real hardware.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_98_2_2'
  5. 01 Feb, 2009 1 commit
    • Jeffrey Lee's avatar
      Initial kernel support for Cortex-A8 processors. · e2262380
      Jeffrey Lee authored
        hdr/ARMops - Added Cortex_A8 processor type, new ARM architecture number
        hdr/Options - Enabled various kernel debug options
        s/ARMops - Added Cortex-A8/OMAP3530 to known CPUs list. Ignore cache type register for ARM architecture &F.
        s/NewIRQs - Increase MaxInterrupts to 96
        Brief testing under qemu-omap3.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_98_2_1'
  6. 22 Dec, 2008 1 commit
    • Ben Avison's avatar
      Minor kernel updates · ab08ee91
      Ben Avison authored
        * Added some documentation on previously undocumented HAL calls
        * Corrected NVMemoryFlag_Provision bitmask to match documentation
        * Bugfix: NVMemoryFlag_ProtectAtEnd flag was being ignored
        Not tested
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_98'
  7. 03 Dec, 2008 1 commit
  8. 04 Oct, 2008 1 commit
    • Ben Avison's avatar
      Merged in changes from Castle · ffe4d1b4
      Ben Avison authored
        Updated GraphicsV documentation
        Upped ROM version number - currently matches latest Castle release (5.13)
        No code change
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_96'
  9. 22 Feb, 2006 1 commit
  10. 16 Feb, 2006 1 commit
  11. 07 Oct, 2005 1 commit
  12. 24 Sep, 2005 1 commit
  13. 23 Sep, 2005 1 commit
  14. 16 Sep, 2005 1 commit
  15. 15 Sep, 2005 1 commit
    • Ben Avison's avatar
      Bugfix to *Help. · 82d4de44
      Ben Avison authored
        Internationalisation of *Help code (ie probably dating back to RISC OS 3.1)
        broke the Escape condition checking. This is particularly nasty if you
        do *Help . on a machine with slow hardware scrolling!
        Not tested.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_89'
  16. 12 Sep, 2005 1 commit
  17. 09 Jun, 2005 1 commit
  18. 18 May, 2005 1 commit
  19. 04 May, 2005 1 commit
  20. 21 Mar, 2005 1 commit
  21. 12 Nov, 2004 1 commit
    • Ben Avison's avatar
      BBE tidying. · ec70a1a4
      Ben Avison authored
        Tightened up BBE resources export, to exclude in appropriate files (this
        component has a non-standard resources directory structure).
        Tested in a Tungsten BBE build.
      Retagged, since this won't affect any existing builds.
  22. 04 Nov, 2004 2 commits
  23. 02 Nov, 2004 1 commit
    • John Ballance's avatar
      several mode: · 208da9fd
      John Ballance authored
           1: default ticker based vsync generated whenever no device present to do so
           2: graphicsv handling and spec updated to use the hi 8 bits in the
              reason code (R4) to define the display number. Kernel only knows
              of display 0
           tested castle  castle added ip
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_81'
  24. 29 Oct, 2004 2 commits
  25. 13 Oct, 2004 1 commit
    • Ben Avison's avatar
      Bugfix and header change. · 9a6346d8
      Ben Avison authored
        * I noticed in passing that the default exception handlers were broken for
          non-IOMD machines if the exception was raised in FIQ mode - unless you
          had a very large application slot, then the machine would lock up. Now
          properly HAL-ised.
        * Added a new event number, allocated for PRISM use back in June.
        Not tested. However, it can't make the situation any worse!
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_78'
  26. 06 Oct, 2004 1 commit
    • Ben Avison's avatar
      Change to calling conditions of UnthreadV. · 5e89ff87
      Ben Avison authored
        Previously, UnthreadV was only called when the IRQsema chain was empty, the
        link for the just-completed interrupt having just been removed. However,
        the information in the link is necessary to allow OS_Heap to be called from
        UnthreadV context, and patching up IRQsema within the UnthreadV handler
        prevents the implementation of a prioritised threading scheme. As a result,
        we must call UnthreadV every time the interrupt dispatch unthreads, and
        leave it up to the UnthreadV handler to distinguish between return to
        thread context and return from a nested interrupt handler.
        Will require some sort of patch to enable heap-safe prioritised threading
        on RISC OS-STB 5.0.0 or RISC OS 5.07, the only two released OSes with the
        previous UnthreadV behaviour.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_77'
  27. 08 Sep, 2004 2 commits
  28. 06 Sep, 2004 1 commit
    • John Ballance's avatar
      fix for invalid cmos checksum computation on iyonix new version date for 5.07 · 83827e89
      John Ballance authored
         CheckSumBlock called IIC_OpV to checksum byte 0 of CMOS, but read back the
         resultant checksum from the wrong offset (#20.. new R1 value)..  now
         corrected to #24 as the correct offset (approx line 997).
         tested at castle in iyonix
         castle added IP
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_74'
  29. 12 Aug, 2004 1 commit
  30. 05 Jul, 2004 1 commit
  31. 25 Jun, 2004 1 commit
    • Kevin Bracey's avatar
      * Changed some STB switches to Embedded_UI · 0731377c
      Kevin Bracey authored
      * Added use of CDVPoduleIRQs (from Hdr:Machine)
      * Fixed checksum corruption in OS_NVMemory block writes ending just below
        the checksum byte.
      * Fixed R4 corruption by OS_Byte 162 with certain HALs.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_71'
  32. 21 Jun, 2004 2 commits
    • Ben Avison's avatar
      Bugfixes to OS_Bytes 13 and 14. · 799120d5
      Ben Avison authored
        Event numbers greater than 31 are possible, it's just that OS_GenerateEvent
        doesn't bother cheking the event semaphores for them. However, the value
        returned in R1 from these OS_Bytes always indicated that such events were
        disabled. This suggests that OS_GenerateEvent was not always so, but the
        initials in comments there suggest the change was about RISC OS 3.0.
        The OS_Bytes now correctly reflect OS_GenerateEvent behaviour.
        Another bug fix is that once the event semaphores had saturated at 255,
        OS_Byte 13 was still happy to decrement the semaphore, so for example 256
        enables followed by 255 disables would have disabled the event.
        Not tested.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_70'
    • Ben Avison's avatar
      Added UnthreadV (vector &2B). Called near the end of despatch of the outermost... · 297a95c2
      Ben Avison authored
      Added UnthreadV (vector &2B). Called near the end of despatch of the outermost interrupt, in IRQ32/26 mode with IRQs disabled, just before transient and non-transient callback checking is performed. Suitable for implementing a CBAI replacement.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_69'
  33. 18 Jun, 2004 1 commit
    • Ben Avison's avatar
      Added four new VDU variables. · f0e2e714
      Ben Avison authored
        174: left border size
        175: bottom border size
        176: right border size
        177: top border size
        Not tested.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_68'
  34. 07 May, 2004 1 commit
  35. 06 May, 2004 1 commit
    • Kevin Bracey's avatar
      * HAL can choose to limit amount of screen memory to allocate · 0f6941a8
      Kevin Bracey authored
        [Not fully implemented - for now leaves at least 16MB free if only
        one RAM area; was 1MB].
      * Added HAL_USBControllerInfo, HAL_MonitorLeadID and HAL_Video_Render.
      * Added HAL->OS call OS_IICOpV.
      * OS_MMUControl now allows independent control of I and C bits.
      * Added facility to deactivate keyboard debounce (magic word "NoKd" in
        R2 in KeyV 0).
      * Fixed problem with RAM amounts not a multiple of 4MB.
      * Supremacy bit (in VDU 19) now sets all 8 bits of supremacy.
      * Added PaletteV 14 (reads gamma tables).
      * Added Supremacy transfer functions (like gamma correction, but for
        supremacy). Allows easy global supremacy effects in a mode-independent
        fashion. Controlled with PaletteV 15,16.
      * Added modes 50-53 (320x240, 1,2,4,8bpp). Intended for small LCD.
      * Added 13.5kHz versions of TV modes (selected by Hdr:Machine).
      * Upped desktop version to 5.06.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_66'
  36. 04 Mar, 2004 1 commit