1. 14 Aug, 2015 1 commit
    • Jeffrey Lee's avatar
      Replace WriteBuffer_Drain ARMop with a suite of memory barrier ARMops · afc3b390
      Jeffrey Lee authored
        - Docs/HAL/ARMop_API - Updated with documentation for the new ARMops.
        - s/ARMops - Set up pointers for the new memory barrier ARMops. Add full implementations for ARMv6 & ARMv7; older architectures should be able to get by with a mix of null ops & write buffer drain ops. Update ARMopPtrTable to validate structure against the list in hdr/OSMisc
        - hdr/KernelWS - Reserve workspace for new ARMops. Free up a bit of space by limiting ourselves to 2 cache levels with ARMv7. Remove some unused definitions.
        - hdr/OSMisc - New header defining OS_PlatformFeatures & OS_MMUControl reason codes, OS_PlatformFeatures 0 flags, and OS_MMUControl 2 ARMop indices
        - Makefile - Add export rules for OSMisc header
        - hdr/ARMops, s/ARM600, s/VMSAv6 - Remove CPUFlag_* and MMUCReason_* definitions. Update OS_MMUControl write buffer drain to use DSB_ReadWrite ARMop (which is what most existing write buffer drain implementations have been renamed to).
        - s/GetAll - Get Hdr:OSMisc
        - s/Kernel - Use OS_PlatformFeatures reason code symbols
        - s/vdu/vdudecl - Remove unused definition
        Tested on ARM11, Cortex-A8, Cortex-A9
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_279'
  2. 05 Aug, 2015 1 commit
    • Jeffrey Lee's avatar
      Improve support for VMSAv6 cache policies & memory types. Expose raw ARMops... · afb010f2
      Jeffrey Lee authored
      Improve support for VMSAv6 cache policies & memory types. Expose raw ARMops via OS_MMUControl & cache information via OS_PlatformFeatures.
        Docs/HAL/ARMop_API - Document two new ARMops: Cache_Examine and IMB_List
        hdr/KernelWS - Shuffle workspace round a bit to allow space for the two new ARMops. IOSystemType now deleted (has been deprecated and fixed at 0 for some time)
        s/ARM600 - Cosmetic changes to BangCam to make it clearer what's going on. Add OS_MMUControl 2 (get ARMop) implementation.
        s/ARMops - Switch out different ARMop implementations and XCB tables depending on MMU model - helps reduce assembler warnings and make it clearer what code paths are and aren't possible. Add implementations of the two new ARMops. Simplify ARM_Analyse_Fancy by removing some tests which we know will have certain results. Use CCSIDR constants in ARMv7 ARMops instead of magic numbers. Update XCB table comments, and add a new table for VMSAv6
        s/ChangeDyn - Define constant for the new NCB 'idempotent' cache policy (VMSAv6 normal, non-cacheable memory)
        s/HAL - Use CCSIDR constants instead of magic numbers. Extend RISCOS_MapInIO to allow the TEX bits to be specified.
        s/Kernel - OS_PlatformFeatures 33 (read cache information) implementation (actually, just calls through to an ARMop)
        s/MemInfo - Modify VMSAv6 OS_Memory 0 cache/uncache implementation to use the XCB table instead of modifying L2_C directly. This allows the cacheability to be changed without affecting the memory type - important for e.g. unaligned accesses to work correctly. Implement cache policy support for OS_Memory 13.
        s/Middle - Remove IOSystemType from OS_ReadSysInfo 6.
        s/VMSAv6 - Make sure BangCam uses the XCB table for working out the attributes of temp-uncacheable pages instead of manipulating L2_C directly. Add OS_MMUControl 2 implementation.
        s/AMBControl/memmap - Update VMSAv6 page table pokeing to use XCB table
        s/PMF/osinit - Remove IOSystemType reference, and switch out some pre-HAL code that was trying to use IOSystemType.
        Tested on Iyonix, ARM11, Cortex-A7, -A8, -A9, -A15
        Note that contrary to the comments in the source the default NCB policy currently maps to VMSAv6 Device memory type (as per previous kernel versions). This is just a temporary measure, and it will be switched over to Normal, non-cacheable once appropriate memory barriers have been added to the affected IO code.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_273'
  3. 13 Apr, 2015 1 commit
    • Jeffrey Lee's avatar
      Fix aborts on Cortex-A15 when using lazy task swapping · 99b3f14a
      Jeffrey Lee authored
        s/VMSAv6 - After AMB_LazyFixUp has modified the page tables, perform a DSB + ISB to ensure the page table write has completed before we return from the abort handler.
        Tested on IGEPv5
        Fixes aborts seen in desktop, e.g. when !CloseUp is rebuilding its sprite (heavy RAM write activity delaying pagetable write?)
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_262'
  4. 20 Jan, 2015 1 commit
    • Jeffrey Lee's avatar
      Perform extra TLB maintenance on ARMv6+. Other cache/TLB maintenance tweaks. · aca7f939
      Jeffrey Lee authored
        s/ARMops - Implement Cache_RangeThreshold for PL310 (helps AMBControl to decide what type of TLB maintenance is best). Fix MMU_ChangingEntry_PL310 doing more work than is necessary; was attempting to flush all ways for a given address tag, when really it should have only been flushing all the lines within a page and letting the cache worry about the tags/indices they correspond to.
        s/ChangeDyn, s/VMSAv6, s/AMBControl/memmap - Do extra TLB maintenance following writes to the page tables, as mandated by the ARMv6+ memory order model. Fixes frequent crashes on Cortex-A9 when running with lazy task swapping disabled (and presumably fixes other crashes too)
        s/MemInfo - Fix OS_Memory cache/uncache so that it does cache/TLB maintenance on a per-page basis instead of a global basis. Vastly improves performance when you have a large cache, but may need tweaking again in future to do a global op if large numbers of pages are being modified.
        Tested on Pandaboard
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_255'
  5. 17 Jan, 2015 1 commit
    • Jeffrey Lee's avatar
      Enable/disable HAL cache controller when enabling/disabling ARM caches · 9c55b854
      Jeffrey Lee authored
        s/VMSAv6 - Modify OS_MMUControl to ensure any HAL-based cache is disabled when either the ARM I or D cache is disabled. This emulates the behaviour of an integrated L2 cache controller.
        Tested on Pandaboard
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_254'
  6. 20 Apr, 2014 1 commit
    • Jeffrey Lee's avatar
      Disable ProcessTransfer code indefinitely · fa2003c1
      Jeffrey Lee authored
        s/ARM600, s/VMSAv6 - Disable ProcessTransfer code for all kernel configurations.
        For VMSAv6 it was definitely broken (needs to be taught about VMSAv6 page tables and ARMv6+ unaligned loads).
        For ARM600 it seems to work OK, but is of no real use as (a) we're always running in 32bit mode and so don't need to worry about processor vector writes and (b) OS_AbortTrap isn't implemented so there's no way for anyone to register an abort handling routine.
        Code is being kept around instead of deleting it straight away just in case there are some hidden knock-ons to disabling it, or we decide to implement our own OS_AbortTrap some day.
        Tested on Iyonix, BB-xM
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_223'
  7. 23 Mar, 2014 2 commits
    • Robert Sprowson's avatar
      Missing hash · 89f30451
      Robert Sprowson authored
      One less warning in each of ARM600/VMSAv6.
    • Jeffrey Lee's avatar
      Fix ProcessTransfer bug with LDM · dd9c5400
      Jeffrey Lee authored
        s/ARM600, s/VMSAv6 - When processing an LDM which wasn't the "user mode registers" form, the initialisation of lr was being skipped, resulting in the registers being loaded from garbage addresses. Shuffle things around slightly so that the branch to label 34 works as intended.
        Issue spotted by Willi Theiss
        Builds, but untested
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_211'
  8. 26 Jan, 2014 1 commit
    • Robert Sprowson's avatar
      Add support for LDRSB to data abort handler · f6c764dd
      Robert Sprowson authored
      Decode LDRSB, do the sign extend, and fault all the other loads and stores not understood.
      As the loads and stores not understood are now vetted properly, it should be safe to UseProcessTransfer (previously they'd have been disassembled incorrectly).
      Paste in LDRSB code from ARM600.
      Fix dubious looking access of CurrentGraphicsVDriver from WsPtr.
      Tested briefly on StrongARM.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_209'
  9. 15 Dec, 2013 1 commit
    • Jeffrey Lee's avatar
      Assorted GraphicsV improvements · 694750de
      Jeffrey Lee authored
        This set of changes:
        * Adds basic support for multiple GraphicsV drivers, by way of some new OS_ScreenMode reason codes for registering/deregistering, selecting and enumerating drivers (11, 64-68)
        * Tidies up handling of HAL video calls so that the HAL calls will be transformed into a bona fide GraphicsV driver if they're implemented
        * Changes handling of 16bpp gamma table entries so that they're sent to GraphicsV in a generic form instead of in a VIDC-specific form
        * Adds a new GraphicsV call and defines new VIDC list items to allow GraphicsV drivers to utilise the new pixel formats
        File changes:
        * h/VIDCList, hdr/VIDCList, Makefile - Add new header export containing VIDC list type 3 definitions, to avoid repeated definitions in other components
        * Resources/UK/Messages - Add new GraphicsV/OS_ScreenMode error strings and some missing processor type strings
        * hdr/KernelWS - Clean up some pre-GraphicsV definitions, and add new workspace locations for storing the current GraphicsV driver number and the driver list
        * hdr/Options - Remove obsolete InverseTextTransparency option
        * hdr/VduExt - Add VDU variable 192 for storing GraphicsV driver number (same as ROL's VideoV driver number). Remove old 'Flag_*' mode flag definitions (use new 'ModeFlag_*' defintions instead). Add new OS_ScreenMode reason codes.
        * s/ARM600, s/VMSAv6, s/vdu/vdu23, s/vdu/vdugrafa, s/vdu/vdugrafd, s/vdu/vdupalxx, s/vdu/vdupointer, s/vdu/vduwrch - Strip out pre-GraphicsV code. Update GraphicsV code to use correct driver number.
        * s/ArthurSWIs - Pass the default GraphicsV claimant the VduDriverWorkSpace instead of ZeroPage
        * s/Getall - Add Hdr:VIDCList and s/vdu/VduGrafHAL to list of GETs
        * s/NewIRQs - Remove HAL VSync IRQ initialisation, is now handled by grafvhal. Remove old HAL VsyncIRQ entry point, all VSyncs are now handled by VsyncIRQ_ExtEntry.
        * s/PMF/osbyte - Stop OS_Byte 19 waiting forever if no video driver is active
        * s/PMF/osinit - Remove HAL VSync IRQ initialisation, is now handled by grafvhal
        * s/vdu/vducursoft - Use new workspace variable names and flag names
        * s/vdu/vdudecl - Remove old HALDAG_* definitions, GVDAG_* definitions are used instead. Add definition of the per-driver workspace structure and flags.
        * s/vdu/vdudriver - Remove pre-GraphicsV code. Update InitialiseMode to check for and initialise a HAL driver. Use cached driver features word in a few places instead of calling GraphicsV each time. Update PalIndexTable to disable VIDC mangling of 16bpp gamma tables.
        * s/vdu/vdugrafv, s/vdu/vdugrafhal - HAL<->GraphicsV code split off into its own file (vdugrafhal). Default GraphicsV claimant now only deals with VSync events for the active driver.
        * s/vdu/vdumodes - Get rid of old VIDC List type 3 definiton; now in hdr/VIDCList
        * s/vdu/vduswis - Added OS_ScreenMode reason codes 11 and 64-68 for registering, deregistering, selecting and enumerating GraphicsV drivers. Update mode set code to not bother checking if the driver supports the pixel format; instead we assume that the driver's vet mode call will do the check for us.
        Tested in Tungsten, IOMD, OMAP3 & BCM2835 ROMs
        Requires HdrSrc-2_38 and updated video driver modes
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_203'
  10. 28 Mar, 2013 1 commit
    • Jeffrey Lee's avatar
      Teach the kernel about different memory attributes · c40b2dba
      Jeffrey Lee authored
        Briefly, this set of changes:
        * Adjusts PhysRamTable so that it retains the flags passed in by the HAL from OS_AddRAM (by storing them in the lower 12 bits of the size field)
        * Sorts the non-VRAM entries of PhysRamTable by speed and DMA capability, to ensure optimal memory allocation during OS startup.
        * Adjust the initial memory allocation logic to allow the cursor/sound chunk and HAL noncacheable workspace to come from DMA capable memory
        * Extends OS_Memory 12 to accept a 'must be DMA capable' flag in bit 8 of R0. This is the same as available in ROL's OS.
        * Extends OS_DynamicArea 0 to allow the creation of dynamic areas that automatically allocate from DMA capable memory. In ROL's OS this was done by setting bit 12 of R4, but we're using bits 12-14 for specifying the cache policy, so instead bit 15 is used.
        * Fixes OS_ReadSysInfo 6 to return the correct DevicesEnd value now that the IRQ/device limit is computed at runtime
        File changes:
        * hdr/OSEntries - Add definitions of the various flags passed to OS_AddRAM by the HAL. Add a new flag, NoDMA, for memory which can't be used for DMA.
        * hdr/KernelWS - Tidy PhysRamTable definition a bit by removing all the DRAM bank definitions except the first - this makes it easier to search for code which is interacting with the table. Remove VRAMFlags, it's redundant now that the flags are kept in the table. Add DMA allocation info to InitWs.
        * s/AMBControl/memmap - Updated to mask out the flags from PhysRamTable when reading RAM block sizes.
        * s/ARM600 - Strip out a lot of IOMD specific pre-HAL code.
        * s/ChangeDyn - Updated to cope with the flags stored in PhysRamTable. Implement support for DMA-capable dynamic areas. Rewrite InitDynamicAreas to insert pages into the free pool in the right order so that the fastest memory will be taken from it first.
        * s/GetAll, s/Middle - Fix OS_ReadSysInfo 6 to return the correct HAL-specific DevicesEnd value
        * s/HAL - Significant rework of initial RAM allocation code to allow the kernel workspace to come from the fastest DMA incapable RAM, while also allowing allocation of DMA capable memory for HAL NCNB workspace & kernel cursor/sound chunks. ClearPhysRAM rewritten as part of this.
        * s/MemInfo - Updated to cope with the flags stored in PhysRamTable. Add support for the new OS_Memory 12 flag. Update OS_Memory 7 to not assume PhysRamTable entries are sorted in address order, and rip out the old pre-HAL IOMD implementation.
        * s/NewReset - Remove GetPagesFromFreePool option, assume TRUE (as this has been the case for the past 10+ years). Revise a few comments and strip dead code. Update to cope with PhysRamTable flags.
        * s/VMSAv6 - Remove a couple of unused definitions
        * s/vdu/vdudriver - Update to cope with PhysRamTable flags
        Tested in Kinetic RiscPC ROM softload, Iyonix softload, & OMAP3
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_186'
  11. 28 Oct, 2012 1 commit
    • Robert Sprowson's avatar
      Review of Internation switch · d58ce177
      Robert Sprowson authored
      Variously the call to TranslateError was either followed (outside the switch) by an unnecessary SETV, or missing SETV for the non international case.
      Added DMA controller HAL device for IOMD.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_174'
  12. 04 Jul, 2012 1 commit
    • Robert Sprowson's avatar
      Make GraphicsV_IICOp more consistent · c671badb
      Robert Sprowson authored
      No accepts  r0 = b31-24 set 0
                       b23-16 fully qualified IIC address
                       b15-0  starting offset
                  r1 = buffer pointer
                  r2 = number of bytes to tranfer
                  r4 = b31-24 display number
                       b23-16 head
                       b15-0  reason code (=14)
      Now returns r0 = result codes as per HAL_IICTransfer()
                  r1 = buffer pointer incremented by number of bytes transferred
                  r2 = number of bytes *not* transferred
                  r4 = 0
      Removed '_' after Video in entry numbers to be consistent with other HAL entry naming, and HAL_VideoFlybackDevice.
      Added IICStatus return numbers to Hdr:HALEntries.
      Stop calling HAL_MonitorLeadID as only IOMD implemented it - just guess VGA until the graphics driver says otherwise.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_159'
  13. 26 Jun, 2012 3 commits
  14. 21 May, 2012 1 commit
    • Robert Sprowson's avatar
      Make Mike's macros permanent. · 2c9aad90
      Robert Sprowson authored
      While the HAL and kernel were being split some temporary macros were used for the bits being worked on, after 12 years of use they're probably safe to adopt.
      mjsCallHAL -> CallHAL; mjsAddressHAL -> AddressHAL; mjsHAL -> HAL.
      OS_VIDCDividerSWI code now always does NoSuchSWI (had been switched out previously).
      File vduhint.s no longer assembled (was empty).
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_150'
  15. 15 Apr, 2012 1 commit
    • Jeffrey Lee's avatar
      OS_ChangeDynamicArea performance optimisations · 5e11e665
      Jeffrey Lee authored
          - Apply various optimisations to OS_ChangeDynamicArea to reduce the execution time when performing large grows/shrinks.
          - Optimisations can be toggled on/off with FastCDA_* flags for debugging.
          - On a 1GHz 512MB BB-xM, the initial *FreePool call now takes 0.15s instead of 13.46s. On a 512MB Iyonix the time has dropped from 1.18s to 0.23s.
          - Growing screen memory (on BB-xM) has also seen significant gains - between 2x and 4x speedup, depending on what state the source pages are in.
          - Added/updated documentation for a few functions and made more use of ROUTs for safety
        s/ARM600, s/VMSAv6:
          - Update BangCamUpdate, etc. to add support for the PageFlags_Unsafe flag that OS_ChangeDynamicArea uses to bypass cache/TLB maintenance in some situations
          - Avoid BangCamUpdate calling BangL2PT to map out the page if the page isn't mapped in (avoids unnecessary cache/TLB flush)
          - Add extra ASSERT for safety
          - Fix incorrect assumption that the usable size of a heap block is always 8 less than the value stored in the header. Even with the old 8 byte aligned allocations the usable size will always be 4 bytes less than the value in the header. This code would have resulted in some slight memory wasteage, as AMBcontrol will have always tried growing the block four bytes bigger than needed.
        Tested on Iyonix & BB-xM
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_146'
  16. 24 Sep, 2011 1 commit
    • Jeffrey Lee's avatar
      Fix objasm 4 warnings · 6d052230
      Jeffrey Lee authored
        s/Arthur3, s/ChangeDyn, s/HAL, s/HeapMan, s/Middle, s/MoreSWIs, s/NewIRQs, s/Utility, s/VMSAv6, s/PMF/key, s/PMF/osbyte, s/PMF/osword, s/vdu/vdudecl, s/vdu/vdudriver, s/vdu/vduplot, s/vdu/vduwrch - Tweaked lots of LDM/STM instructions in order to get rid of the depracation/performance warnings
        Tested on rev A2 BB-xM
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_98_2_53'
  17. 08 Aug, 2011 1 commit
    • Jeffrey Lee's avatar
      Add zero page relocation support · 2247d8e9
      Jeffrey Lee authored
        A whole mass of changes to add high processor vectors + zero page relocation support to the Cortex branch of the kernel
        At the moment the code can only cope with two ZeroPage locations, &0 and &FFFF0000. But with a bit more tweaking those restrictions can probably be lifted, allowing ZeroPage to be hidden at almost any address (assuming it's fixed at compile time). If I've done my job right, these restrictions should all be enforced by asserts.
        There's a new option, HiProcVecs, in hdr/Options to control whether high processor vectors are used. When enabling it and building a ROM, remember:
        * FPEmulator needs to be built with the FPEAnchor=High option specified in the components file (not FPEAnchorType=High as my FPEmulator commit comments suggested)
        * ShareFS needs unplugging/removing since it can't cope with it yet
        * Iyonix users will need to use the latest ROOL boot sequence, to ensure the softloaded modules are compatible (OMAP, etc. don't really softload much so they're OK with older sequences)
        * However VProtect also needs patching to fix a nasty bug there - http://www.riscosopen.org/tracker/tickets/294
        The only other notable thing I can think of is that the ProcessTransfer code in s/ARM600 & s/VMSAv6 is disabled if high processor vectors are in use (it's fairly safe to say that code is obsolete in HAL builds anyway?)
        Fun challenge for my successor: Try setting ZeroPage to &FFFF00FF (or similar) so its value can be loaded with MVN instead of LDR. Then use positive/negative address offsets to access the contents.
        File changes:
        - hdr/ARMops - Modified ARMop macro to take the ZeroPage pointer as a parameter instead of 'zero'
        - hdr/Copro15ops - Corrected $quick handling in myISB macro
        - hdr/Options - Added ideal setting for us to use for HiProcVecs
        - s/AMBControl/allocate, s/AMBControl/growp, s/AMBControl/mapslot, s/AMBControl/memmap, s/AMBControl/service, s/AMBControl/shrinkp, s/Arthur2, s/Arthur3, s/ArthurSWIs, s/ChangeDyn, s/ExtraSWIs, s/HAL, s/HeapMan, s/Kernel, s/MemInfo, s/Middle, s/ModHand, s/MoreSWIs, s/MsgCode, s/NewIRQs, s/NewReset, s/Oscli, s/PMF/buffer, s/PMF/IIC, s/PMF/i2cutils, s/PMF/key, s/PMF/mouse, s/PMF/osbyte, s/PMF/oseven, s/PMF/osinit, s/PMF/osword, s/PMF/oswrch, s/SWINaming, s/Super1, s/SysComms, s/TickEvents, s/Utility, s/vdu/vdu23, s/vdu/vdudriver, s/vdu/vdugrafl, s/vdu/vdugrafv, s/vdu/vdupalxx, s/vdu/vdupointer, s/vdu/vduswis, s/vdu/vduwrch - Lots of updates to deal with zero page relocation
        - s/ARM600 - UseProcessTransfer option. Zero page relocation support. Deleted pre-HAL ClearPhysRAM code to tidy the file up a bit.
        - s/ARMops - Zero page relocation support. Set CPUFlag_HiProcVecs when high vectors are in use.
        - s/KbdResPC - Disable compilation of dead code
        - s/VMSAv6 - UseProcessTransfer option. Zero page relocation support.
        Tested with OMAP & Iyonix ROM softloads, both with high & low zero page.
        High zero page hasn't had extensive testing, but boot sequence + ROM apps seem to work.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_98_2_48'
  18. 24 Jul, 2011 1 commit
    • Jeffrey Lee's avatar
      Tweak data abort handler to try and avoid recusrive aborts confusing AMBControl · 8df5d3f5
      Jeffrey Lee authored
        s/VMSAv6 - The code to detect aborting MVA ops now only runs if the aborting instruction wasn't located in application space.
        This is a workaround for an issue where:
        (a) The aborting instruction is in application space
        (b) The aborting instruction is attempting to access memory located in the same page as itself
        (c) That page is not mapped in (despite the fact that code is being executed from it)
        Originally attempting to load the aborting the instruction would have triggered another abort, causing AMBControl to map in the page and resume the first abort handler. The first abort handler would then have determined that it wasn't an MVA op and called AMBControl, only to be told by AMBControl that it wasn't a lazy fixup abort (even though it really was), thus triggering the abort environment handler.
        By ignoring instructions located in application space the second abort is avoided, allowing AMBControl to correctly process the abort.
        Tested on rev A2 BB-xM.
        Fixes issue with DPScan crashing - http://www.freelists.org/post/davidpilling/DPScan-ARMini-crash
        Still need to determine how the ICache is able to become so out of sync with the DCache & page tables.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_98_2_40'
  19. 04 Jun, 2011 1 commit
    • Jeffrey Lee's avatar
      Add hdr.Variables to the C header export, fix ARMv6 issues · b8267d5d
      Jeffrey Lee authored
        Makefile - Added hdr.Variables to the C header export list
        hdr/ARMops, s/ARMops - Added ARM1176JZF-S to the list of known CPUs
        s/ARMops - Fix unaligned memory access in ARM_PrintProcessorType
        hdr/Copro15ops, s/ARMops, s/HAL, s/VMSAv6, s/AMBControl/memmap - Fixed all myDSB/myISB/etc. macro instances to specify a temp register, so that they work properly when building an ARMv6 version of the kernel
        Fixes build errors with the latest Draw module.
        Should also allow the kernel to work properly with the new S3C6410 port.
        ARMv6 version builds OK, but no other builds or runtime tests have been made.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_98_2_38'
  20. 22 May, 2011 1 commit
    • Jeffrey Lee's avatar
      Update Cortex branch of kernel to support HALSize env variable. Export C version of hdr.OSEntries. · 1bd9c9e0
      Jeffrey Lee authored
        Makefile - Now exports a C version of hdr.OSEntries, for use by the new HAL USB drivers
        s/GetAll, s/Kernel - The HALSize env variable is now used in place of hard-coded values for the HAL size
        s/HAL - Reset_IRQ_Handler now switches to SVC mode before calling HAL_KbdScanInterrupt, to allow the HAL USB drivers to re-enable interrupts if they wish.
        s/VMSAv6 - Deleted some obsolete definitions
        Tested on rev C2 BB, A2 BB-xM, C1 TouchBook
        Needs latest BuildSys, Env, HdrSrc
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_98_2_37'
  21. 02 Sep, 2010 1 commit
    • Jeffrey Lee's avatar
      Fix ARMv7 MVA-based cache/TLB op abort handler to be re-entrant · 9aa05feb
      Jeffrey Lee authored
        s/VMSAv6 - The code in DAbPreVeneer that checks for aborting MVA-based cache/TLB ops is now re-entrant.
        This is to cope with the "strange but true" case where a data abort was being triggered by a load/store
        instruction that itself was in an unmapped page.
        Tested on rev C2 beagleboard. Fixes issue with StrongED crashing on load (see http://www.riscosopen.org/forum/forums/5/topics/453)
        Still need to work out why CPU was able to execute code from the unmapped page without triggering a prefetch abort (stale cache entries?)
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_98_2_31'
  22. 03 Jul, 2010 1 commit
    • Jeffrey Lee's avatar
      Fix more issues caused by aborting MVA cache/TLB ops on ARMv7 · 9e6b9350
      Jeffrey Lee authored
        s/ARMops - Fixed an instance of 'invalidate branch predictor entry' that should have been 'invalidate all branch predictors'
        s/ChangeDyn - Avoid cleaning the Nowhere page when reallocating memory, to avoid incurring the performance hit of the abort handler, and to avoid AMBControl screwing things up by mapping in pages that we're trying to modify
        s/VMSAv6 - Move MVA cache/TLB abort handler to before ChocolateAMB code, to ensure AMBControl doesn't try mapping in pages for harmless cache/TLB op aborts. Also tweaked code to be a little bit faster.
        Tested on rev C2 beagleboard. No more lockups when moving screen memory around, for now at least.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_98_2_30'
  23. 23 Jun, 2010 1 commit
    • Jeffrey Lee's avatar
      Update Cortex kernel to use correct instruction/memory barriers and to perform... · de8e610e
      Jeffrey Lee authored
      Update Cortex kernel to use correct instruction/memory barriers and to perform branch target predictor maintenance. Plus tweak default CMOS settings.
        hdr/Copro15ops - Added myISB, myDSB, myDMB macros to provide barrier functionality on ARMv6+
        s/ARMops, s/HAL, s/VMSAv6, s/AMBControl/memmap - Correct barrier operations are now performed on ARMv6+ following CP15 writes. Branch predictors are now also maintained properly.
        s/NewReset - Change default CMOS settings so number of CDFS drives is 0 in Cortex builds. Fixes rogue CDFS icon on iconbar.
        Tested on rev C2 beagleboard
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_98_2_27'
  24. 28 Feb, 2010 1 commit
    • Jeffrey Lee's avatar
      Update VDU HAL device for new OMAPVideo driver, fix MVA-based cache/TLB... · b213fdd5
      Jeffrey Lee authored
      Update VDU HAL device for new OMAPVideo driver, fix MVA-based cache/TLB maintenance ops aborting on ARMv7, add warning to VDU driver about inconsistent state variables during screen mode changes
        hdr/VideoDevice - removed Address2 and Device2 fields as it makes more sense for them to be in the device specific field (which for OMAP3 is a pointer to an OMAP3-specific struct)
        s/VMSAv6 - Modify data abort handler to ignore aborts that are generated by MVA-based cache/TLB maintenance ops. Unlike earlier ARM architectures, MVA-based ops can abort under ARMv7 if the page has no mapping to a physical address.
        s/vdu/vdudriver - Add a warning about VDU driver state variables (particularly CursorAddr) being left in invalid states during the execution of mode changes. This can cause problems if any attempt is made to output to the screen during the mode change (e.g. as a result of an abort)
        Tested on rev C2 beagleboard. Video device changes mean that OMAP3 HAL 0.23 will be needed for ROM compilation to succeed.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_98_2_24'
  25. 17 May, 2009 1 commit
    • Ben Avison's avatar
      Miscellaneous v6-related updates · 9d9aa41b
      Ben Avison authored
       * Stopped calling the broken abort fixup code when running under VMSAv6.
         Might be desirable to update it, possibly farmed out to a separate module -
         still need to think about this.
       * Unaligned load optimisations can now be disabled by the global NoUnaligned
         flag for testing purposes.
       * Extended OS_ReadUnsigned to permit reading of 64-bit unsigned integers.
         See Docs.ReadUnsigned for more details. Also sped it up by using MLA
         (or UMLAL) for most digits rather than repeated addition.
       * Bugfix is OS_GSRead: an uninitialised r0 was being passed to
         OS_ReadUnsigned, causing undesirable effects on rare occasions.
        Tested on a rev B7 beagleboard.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_98_2_8'
  26. 06 Mar, 2009 1 commit
    • Jeffrey Lee's avatar
      Add VMSAv6 MMU support, fixes to allow booting on beagleboard · 3d1317e7
      Jeffrey Lee authored
        s/ARM600 - fix to SyncCodeAreasRange to correctly read cache line length for WB_CR7_Lx caches
        s/ARMops - Cortex cache handling fixes. Enable L2 cache for Cortex.
        s/ChangeDyn - VMSAv6 support in AllocateBackingLevel2
        s/HAL - Improve RISCOS_InitARM to set/clear correct CP15 flags for ARMv6/v7. VMSAv6 support in code to generate initial page tables.
        s/NewReset - Extra DebugTX calls during OS startup. Disable pre-HAL Processor_Type for HAL builds.
        s/VMSAv6 - Main VMSAv6 MMU code - stripped down version of s/ARM600 with support for basic VMSAv6 features.
        hdr/Options - Use VMSAv6 MMU code, not ARM600. Disable ARM6support since current VMSAv6 code will conflict with it.
        Tested basic OS functionality under qemu-omap3 and revision B6 beagleboard.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_98_2_3'