1. 31 Aug, 2015 1 commit
    • Jeffrey Lee's avatar
      Add initial support for "physical memory pools" · 54872d8c
      Jeffrey Lee authored
        This set of changes adds support for "physical memory pools" (aka PMPs), a new type of dynamic area which allow physical pages to be claimed/allocated without mapping them in to the logical address space. PMPs have full control over which physical pages they use (similar to DAs which request specific physical pages), and also have full control over the logical mapping of their pages (which pages go where, and per-page access/cacheability control).
        Currently the OS makes use of two PMPs: one for the free pool (which now has a logical size of zero - freeing up gigabytes of logical space), and one for the RAM disc (logical size of 1MB, allowing for a physical size limited only by the amount of free memory)
        Implementing these changes has required a number of other changes to be made:
        * The CAM has been expanded from 8 bytes per entry to 16 bytes per entry, in order to allow each RAM page to store information about its PMP association
        * The system heap has been expanded to 32MB in size (from just under 4MB), in order to allow it to be used to store PMP page lists (1 word needed per page, but PMP pages may not always have physical pages assigned to them - so to allow multiple large PMPs to exist we need more than just 1 word per RAM page)
        * The &FA000000-&FBFFFFFF area of fixed kernel workspace has been shuffled around to accomodate the larger CAM, and the system heap is now located just above the RMA.
        * SoftResets code stripped out (unlikely we'll ever want to fix and re-enable it)
        * A couple of FastCDA options are now permanently on
        * Internal page flags shuffled around a bit. PageFlags_Unavailable now publicly exposed so that PMP clients can lock/unlock pages at will.
        * When OS_ChangeDynamicArea is asked to grow or shrink the free pool, it now implicitly converts it into a shrink or grow of application space (which is what would happen anyway). This simplifies the implementation; during a grow, pages (or replacement pages) are always sourced from the free pool, and during a shrink pages are always sent to the free pool.
        File changes:
        - hdr/KernelWS - Extend DANode structure. Describe CAM format. Adjust kernel workspace.
        - hdr/OSRSI6, s/Middle - Add new item to expose the CAM format
        - hdr/Options - Remove SoftResets switch. Add some PMP switches.
        - s/ARM600, s/VMSAv6 - Updated for new CAM format. Note that although the CAM stores PMP information, BangCamUpdate currently doesn't deal with updating that data - it's the caller's responsibility to do so where appropriate.
        - s/ChangeDyn - Lots of changes to implement PMP support, and to cope with the new CAM format.
        - s/HAL - Updated to cope with new CAM format, and lack of logical mapping of free pool.
        - s/MemInfo - Updated to cope with new CAM format. OS_Memory 0 updated to cope with converting PPN to PA for pages which are mapped out. OS_Memory 24 updated to decode the access permissions on a per-page basis for PMPs, and fixed its HWM usage for sparse DAs.
        - s/NewReset - Soft reset code and unused AddCamEntries function removed. Updated to cope with new CAM format, PMP free pool, PMP RAMFS
        - s/AMBControl/allocate - Update comment (RMA hasn't been used for AMBControl nodes for a long time)
        - s/AMBControl/growp, s/AMBControl/memmap, s/AMBControl/shrinkp - Update for new CAM format + PMP free pool
        - s/vdu/vdudriver - Strip out soft reset code.
        Tested on Pandaboard
        This is just a first iteration of the PMP feature, with any luck future changes will improve functionality. This means APIs are subject to change as well.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_284'
  2. 20 Aug, 2015 1 commit
    • John Ballance's avatar
      Corrected makefile omissions. · da41d3a5
      John Ballance authored
        Removed errant tab characters from EtherDevice header
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_283'
  3. 19 Aug, 2015 1 commit
  4. 17 Aug, 2015 1 commit
    • Jeffrey Lee's avatar
      Fix examination of L2 cache · ace0a205
      Jeffrey Lee authored
        s/ARMops - In Analyse_WB_CR7_Lx, we need to check against Cache_Lx_MaxLevel*2, because the cache size selection register counts I + D caches separately
        Tested on IGEPv5
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_281'
  5. 15 Aug, 2015 1 commit
    • Jeffrey Lee's avatar
      Switch default NCB cache policy to MergingIdempotent (i.e. Normal, non-cacheable) · 4dff21b8
      Jeffrey Lee authored
        s/ARMops - Change VMSAv6 cache policy mapping so that default NCB policy maps to Normal, non-cacheable memory rather than Device memory. This allows unaligned accesses to work, and also delivers some major performance improvements for some activities (write performance seems about 2x better than Device)
        Docs/HAL/ARMop_API - Wrap the new barrier ARMop description text to match the rest of the file
        Tested on ARM11, Cortex-A7, -A8, -A9
        Note - relaxed memory consistency rules for Normal vs. Device mean that now more than ever, developers authoring device drivers for ARMv6+ need to be careful to use memory barriers in all the right places (preferably the new ARMop barriers exposed by OS_MMUControl 2 to ensure compatibility with all machines)
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_280'
  6. 14 Aug, 2015 1 commit
    • Jeffrey Lee's avatar
      Replace WriteBuffer_Drain ARMop with a suite of memory barrier ARMops · afc3b390
      Jeffrey Lee authored
        - Docs/HAL/ARMop_API - Updated with documentation for the new ARMops.
        - s/ARMops - Set up pointers for the new memory barrier ARMops. Add full implementations for ARMv6 & ARMv7; older architectures should be able to get by with a mix of null ops & write buffer drain ops. Update ARMopPtrTable to validate structure against the list in hdr/OSMisc
        - hdr/KernelWS - Reserve workspace for new ARMops. Free up a bit of space by limiting ourselves to 2 cache levels with ARMv7. Remove some unused definitions.
        - hdr/OSMisc - New header defining OS_PlatformFeatures & OS_MMUControl reason codes, OS_PlatformFeatures 0 flags, and OS_MMUControl 2 ARMop indices
        - Makefile - Add export rules for OSMisc header
        - hdr/ARMops, s/ARM600, s/VMSAv6 - Remove CPUFlag_* and MMUCReason_* definitions. Update OS_MMUControl write buffer drain to use DSB_ReadWrite ARMop (which is what most existing write buffer drain implementations have been renamed to).
        - s/GetAll - Get Hdr:OSMisc
        - s/Kernel - Use OS_PlatformFeatures reason code symbols
        - s/vdu/vdudecl - Remove unused definition
        Tested on ARM11, Cortex-A8, Cortex-A9
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_279'
  7. 11 Aug, 2015 1 commit
    • Jeffrey Lee's avatar
      Fix some re-entrancy issues. Minor optimisations. · cbfc4ff1
      Jeffrey Lee authored
        - Change initial TickNodeLeft check in ProcessTickEventChain to exit on HI rather than NE. This fixes a case where the ticker event chain can become corrupted if ProcessTickEventChain is re-entered while in the middle of processing multiple nodes which are due to fire at the same time (after initial node is removed from the list, head node will be left with a TickNodeLeft value of 0)
        - Move "IRQ's off again" PSR write to be after the 10 label, to ensure that IRQs are off before we examine/process the next node (naughty CallEvery may have exited with IRQs enabled)
        - Stop using crusty old WritePSRc macro (currently generates 4 instructions for something that should be 1)
        - Also get rid of ARM2-era NOPs
        - Optimise CallEvery check to be MOVS rather than LDR + CMP
        Tested on Pandaboard
        Should fix problem reported on forums with apparent wrap-around of TickNodeLeft value of first node: https://www.riscosopen.org/forum/forums/5/topics/3544
        May also fix other ticker corruption problems: https://www.riscosopen.org/forum/forums/4/topics/2708
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_278'
  8. 10 Aug, 2015 3 commits
  9. 06 Aug, 2015 1 commit
    • Jeffrey Lee's avatar
      Fix DebuggerSpace page to be cacheable · 5db5ffa3
      Jeffrey Lee authored
        s/HAL - A typo seems to have resulted in the HiProcVecs DebuggerSpace page being mapped in as NCB instead of CB. Fix it.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_274'
  10. 05 Aug, 2015 1 commit
    • Jeffrey Lee's avatar
      Improve support for VMSAv6 cache policies & memory types. Expose raw ARMops... · afb010f2
      Jeffrey Lee authored
      Improve support for VMSAv6 cache policies & memory types. Expose raw ARMops via OS_MMUControl & cache information via OS_PlatformFeatures.
        Docs/HAL/ARMop_API - Document two new ARMops: Cache_Examine and IMB_List
        hdr/KernelWS - Shuffle workspace round a bit to allow space for the two new ARMops. IOSystemType now deleted (has been deprecated and fixed at 0 for some time)
        s/ARM600 - Cosmetic changes to BangCam to make it clearer what's going on. Add OS_MMUControl 2 (get ARMop) implementation.
        s/ARMops - Switch out different ARMop implementations and XCB tables depending on MMU model - helps reduce assembler warnings and make it clearer what code paths are and aren't possible. Add implementations of the two new ARMops. Simplify ARM_Analyse_Fancy by removing some tests which we know will have certain results. Use CCSIDR constants in ARMv7 ARMops instead of magic numbers. Update XCB table comments, and add a new table for VMSAv6
        s/ChangeDyn - Define constant for the new NCB 'idempotent' cache policy (VMSAv6 normal, non-cacheable memory)
        s/HAL - Use CCSIDR constants instead of magic numbers. Extend RISCOS_MapInIO to allow the TEX bits to be specified.
        s/Kernel - OS_PlatformFeatures 33 (read cache information) implementation (actually, just calls through to an ARMop)
        s/MemInfo - Modify VMSAv6 OS_Memory 0 cache/uncache implementation to use the XCB table instead of modifying L2_C directly. This allows the cacheability to be changed without affecting the memory type - important for e.g. unaligned accesses to work correctly. Implement cache policy support for OS_Memory 13.
        s/Middle - Remove IOSystemType from OS_ReadSysInfo 6.
        s/VMSAv6 - Make sure BangCam uses the XCB table for working out the attributes of temp-uncacheable pages instead of manipulating L2_C directly. Add OS_MMUControl 2 implementation.
        s/AMBControl/memmap - Update VMSAv6 page table pokeing to use XCB table
        s/PMF/osinit - Remove IOSystemType reference, and switch out some pre-HAL code that was trying to use IOSystemType.
        Tested on Iyonix, ARM11, Cortex-A7, -A8, -A9, -A15
        Note that contrary to the comments in the source the default NCB policy currently maps to VMSAv6 Device memory type (as per previous kernel versions). This is just a temporary measure, and it will be switched over to Normal, non-cacheable once appropriate memory barriers have been added to the affected IO code.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_273'
  11. 26 Jul, 2015 1 commit
    • Jeffrey Lee's avatar
      Add HAL device numbers for Raspberry Pi SPI controllers · fc4cbde0
      Jeffrey Lee authored
        hdr/HALDevice - Add a new device type for SPI controllers, and allocate two device numbers for use on the Pi (to differentiate between the main and aux controllers)
        Tested on Raspberry Pi B & 2 B
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_272'
  12. 17 Jul, 2015 1 commit
    • Jeffrey Lee's avatar
      Expose more areas via OS_ReadSysInfo 6 & OS_Memory 16. Expose processor... · 5e6fd146
      Jeffrey Lee authored
      Expose more areas via OS_ReadSysInfo 6 & OS_Memory 16. Expose processor vectors base + size via OS_PlatformFeatures.
        hdr/KernelWS - Define processor vectors address. Currently same as ZeroPage, but in the future will differ for some machines.
        hdr/OSRSI6, s/Middle - Expose VecPtrTab & NVECTORS via OS_ReadSysInfo items 85 & 86
        s/Kernel - Add OS_PlatformFeatures 32, for returning the base + size of the processor vectors
        s/MemInfo - Add areas 12 thru 15 to OS_Memory 16, for reporting ZeroPage, ProcVecs, DebuggerSpace and ScratchSpace. The task manager can now use these for calculating memory usage instead of assuming 32K workspace from &0-&8000.
        Tested on Raspberry Pi
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_271'
  13. 13 Jul, 2015 1 commit
    • Jeffrey Lee's avatar
      Fix software pointer being enabled when it isn't needed. Improve HangWatch support. · 0da882fd
      Jeffrey Lee authored
        s/vdu/vdupointer - For any mode where the software pointer is usable, RestorePointer was restoring the software pointer regardless of whether it was in use at the time RemovePointer was called. This would cause both the software & hardware pointers to be briefly enabled at the same time, potentially causing flickering or other glitches. Fix the issue by making sure RestorePointer only restores if the software pointer was actually in use at the time RemovePointer was called. Also, attempt to deal with the situation where the pointer might have moved to a location where the software pointer is no longer required.
        s/Middle - Improve integration of HangWatch with the abort handler - avoid overwriting the top of the SVC stack so that it can be preserved for the HangWatch dump.
        Tested on Raspberry Pi
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_270'
  14. 10 Jul, 2015 1 commit
    • Jeffrey Lee's avatar
      Add builtin software pointer support · d1af0ed0
      Jeffrey Lee authored
        This set of changes adds support for rendering software mouse pointers directly in the kernel, rather than requiring graphics drivers to render them themselves as was the case previously.
        If a driver returns from GraphicsV_Features with the 'hardware pointer' bit clear, and a call to GraphicsV_UpdatePointer is returned unclaimed, then the kernel will step in and render a software pointer. This allows selective control over which areas of the screen the software pointer is used (e.g. if hardware only supports its use in some areas)
        hdr/KernelWS - Shrink PointerXEigFactor to 1 byte to free up some space for tracking the display log2bpp. Use 8 words of space for tracking software pointer state.
        s/vdu/vducursoft - Adjust existing the existing calls to the software pointer RemovePointer/RestorePointer functions so that they're called with IRQs enabled
        s/vdu/vdudriver - Keep track of display log2bpp. Claim/release memory needed for restoring pixels under software pointer.
        s/vdu/vdugrafhal - Update HAL_VideoUpdatePointer handling so that 0 can be returned in a1 to indicate the GraphicsV call should be left unclaimed.
        s/vdu/vdupalxx - Trigger updates of the cached software pointer palette whenever it's likely to become invalidated.
        s/vdu/vdupointer - Add software pointer implementation. Relying on a SpriteExtend OS_SpriteOp would be nice, but we're in the background so have to do plotting & unplotting manually. ColourTrans is used to cache the pointer palette colours for the current mode, although we're limited to calling it from a callback.
        Tested on Raspberry Pi & BB-xM
        Pointer is very flickery under some circumstances (e.g. running !CloseUp) due to needing to plot/unplot around any VDU driver screen access (as per text cursor). So code may need revising in future once we can trap reads/writes from specific screen memory pages.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_269'
  15. 04 Jul, 2015 2 commits
    • Jeffrey Lee's avatar
      Enable high processor vectors/zero page relocation. OS_DynamicArea 20 fixes. · f5644f74
      Jeffrey Lee authored
        Makefile, hdr/Options - By default enable high processor vectors/zero page relocation for compatible machines, but also allow the components file to override the setting if required
        s/ChangeDyn - Fix OS_DynamicArea 20 to check the correct range for doubly mapped areas, and to correctly localise its error message
        Tested on Iyonix
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_268'
    • Robert Sprowson's avatar
      Add extra OS_DynamicArea subreason · c8f15bd6
      Robert Sprowson authored
      Subreason 20 takes a logical address and tells you which area it lies in, including system areas (ie. those returned by OS_Memory 16.
      This allows areas to change type in future without the caller needing to care where the kernel put it.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_267'
  16. 19 Jun, 2015 1 commit
    • Jeffrey Lee's avatar
      Fix HiProcVecs build. Remove old-style PublicWS definitions. · 1aa4be26
      Jeffrey Lee authored
        s/ARMops - Added extra LTORG to fix HiProcVecs build error for some platforms
        hdr/PublicWS - Remove the old (non-Legacy_) workspace exports, and add a comment explaining how the newer Legacy_ exports should be used.
        HiProcVecs ROMs for various platforms now appear to build OK
        Untested at runtime
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_266'
  17. 14 Jun, 2015 1 commit
    • Jeffrey Lee's avatar
      Ensure IO memory is marked as non-executable · e5bd59a6
      Jeffrey Lee authored
        s/HAL - The VMSAv6/v7 memory model allows speculative instruction fetches from any memory (including device/strongly-ordered), unless the memory is marked as non-executable. So to prevent interference with read-sensitive devices we must make sure all appropriate IO memory is marked as non-executable.
        Tested on IGEPv5
        Fixes data corruption seen when reading from SD card
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_265'
  18. 19 Apr, 2015 2 commits
  19. 13 Apr, 2015 1 commit
    • Jeffrey Lee's avatar
      Fix aborts on Cortex-A15 when using lazy task swapping · 99b3f14a
      Jeffrey Lee authored
        s/VMSAv6 - After AMB_LazyFixUp has modified the page tables, perform a DSB + ISB to ensure the page table write has completed before we return from the abort handler.
        Tested on IGEPv5
        Fixes aborts seen in desktop, e.g. when !CloseUp is rebuilding its sprite (heavy RAM write activity delaying pagetable write?)
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_262'
  20. 29 Mar, 2015 1 commit
    • Jeffrey Lee's avatar
      Fix OS_Byte 19 getting stuck if it's called just before the screen blanker... · f17af1cf
      Jeffrey Lee authored
      Fix OS_Byte 19 getting stuck if it's called just before the screen blanker activates. Add new OS_ReadSysInfo reason code for determining IIC bus count.
        s/PMF/osbyte - For OS_Byte 19, move screen blanker check (and current GraphicsV driver check) inside the WFI loop so that the loop will terminate if the screen should blank (or current GraphicsV driver should die) before the next VSync occurs. Also move the Portable_Idle call to before the interrupt trigger - the old location meant that if the screen blanked we'd continue on to the Portable_Idle call and end up pointlessly stalling the system
        s/Middle - Add OS_ReadSysInfo 14, as a legitimate way of finding the number of IIC buses present on the system
        Tested on Pandaboard
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_261'
  21. 16 Mar, 2015 1 commit
  22. 12 Mar, 2015 1 commit
    • Robert Sprowson's avatar
      Ensure HAL cache device is initialised · abcadc7c
      Robert Sprowson authored
      The Cache_HALDevice is in the RAM clear skip table, so when there's no controller found and the kernel is doing the RAM clear it's unset, leading to probable aborts when typing *CACHE Om|Off.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_259'
  23. 26 Feb, 2015 1 commit
    • Jeffrey Lee's avatar
      Add TouchBook to hdr:GPIODevice · 06396b24
      Jeffrey Lee authored
        hdr/GPIODevice - Added the TouchBook as an OMAP3 machine type. We don't actually create a GPIO HAL device for it, but having it defined here is useful for SDIO support in the HAL.
        Tested on TouchBook
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_258'
  24. 16 Feb, 2015 1 commit
  25. 07 Feb, 2015 1 commit
    • Jeffrey Lee's avatar
      Add workaround for Cortex-A7 errata 814220 · 94c601f8
      Jeffrey Lee authored
        s/ARMops, s/HAL - Errata 814220 states that the Cortex-A7 set/way cache maintenance operations violate the usual operation ordering rules, such that an L2 maintenance operation which is started after an L1 operation may actually complete before it, causing data corruption if the L1 data was to be evicted to the L2 entry. Implement the suggested workaround of performing a DSB when switching cache levels, rather than just at the end of the combined L1+L2 group of operations.
        Tested on Raspberry Pi 2
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_257'
  26. 02 Feb, 2015 1 commit
    • Ben Avison's avatar
      Add Raspberry Pi 2 support · d6806495
      Ben Avison authored
        The Raspberry Pi ROM now joins the IOMD ROM in supporting multiple
        architectures, in this case ARMv6 and ARMv7. This has been achieved by
        creating a new machine type specific for Raspberry Pi. The old ARM11ZF
        machine type remains for builds that are ARM11-only.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_256'
  27. 20 Jan, 2015 1 commit
    • Jeffrey Lee's avatar
      Perform extra TLB maintenance on ARMv6+. Other cache/TLB maintenance tweaks. · aca7f939
      Jeffrey Lee authored
        s/ARMops - Implement Cache_RangeThreshold for PL310 (helps AMBControl to decide what type of TLB maintenance is best). Fix MMU_ChangingEntry_PL310 doing more work than is necessary; was attempting to flush all ways for a given address tag, when really it should have only been flushing all the lines within a page and letting the cache worry about the tags/indices they correspond to.
        s/ChangeDyn, s/VMSAv6, s/AMBControl/memmap - Do extra TLB maintenance following writes to the page tables, as mandated by the ARMv6+ memory order model. Fixes frequent crashes on Cortex-A9 when running with lazy task swapping disabled (and presumably fixes other crashes too)
        s/MemInfo - Fix OS_Memory cache/uncache so that it does cache/TLB maintenance on a per-page basis instead of a global basis. Vastly improves performance when you have a large cache, but may need tweaking again in future to do a global op if large numbers of pages are being modified.
        Tested on Pandaboard
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_255'
  28. 17 Jan, 2015 1 commit
    • Jeffrey Lee's avatar
      Enable/disable HAL cache controller when enabling/disabling ARM caches · 9c55b854
      Jeffrey Lee authored
        s/VMSAv6 - Modify OS_MMUControl to ensure any HAL-based cache is disabled when either the ARM I or D cache is disabled. This emulates the behaviour of an integrated L2 cache controller.
        Tested on Pandaboard
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_254'
  29. 16 Jan, 2015 1 commit
    • Jeffrey Lee's avatar
      Escape some dollars · ece80d58
      Jeffrey Lee authored
        s/NewReset, s/Super1 - Escape some dollars contained in strings to avoid warnings from objasm
        Resulting binary unchanged
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_253'
  30. 11 Jan, 2015 1 commit
    • Jeffrey Lee's avatar
      Add ARMops for PL310 L2 cache controller · 6eb6ee2a
      Jeffrey Lee authored
        Unlike on the Cortex-A8 or Cortex-A15, the L2 cache that's used with the Cortex-A9 isn't hooked up to the standard ARMv7 CP15 cache maintenance ops. Instead, memory-mapped registers must be used to program and maintain the cache.
        Since the PL310 can't be detected automatically, this change adds support for a 'cache controller' HAL device which the HAL can use to advertise the presence of any external caches. If a cache device is registered during HAL_InitDevices the kernel will then check it against a list of known cache types and replace the appropriate ARMop routines with the alternatives for that controller.
        File changes:
        - hdr/PL310 - New header containing PL310 register listing
        - Makefile - Add export for PL310 header. Reorder exports to be alphabetical
        - hdr/HALDevice - Add cache controller device type, PL310 device
        - hdr/KernelWS - Allocate some workspace for storing a pointer to the current cache HAL device
        - s/ARMops - Add code for searching for known cache types, and implementation of PL310-specific ARMops
        - s/GetAll - Get Hdr:PL310
        - s/NewReset - Look for a cache controller after calling HAL_InitDevices
        Tested on Pandaboard
        Fixes various assorted instability issues
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_252'
  31. 09 Jan, 2015 1 commit
    • Jeffrey Lee's avatar
      Fix detection of ARMv7 minimum cache line lengths · 4843ce7e
      Jeffrey Lee authored
        s/ARMops - Replace the code to calculate the minimum cache line lengths with something much simpler which reads the values directly from the cache type register.
        The old code was buggy in two ways:
        (a) the cache size identification register stores the line length as log2(num words)-2, whereas the code throughout the kernel was expecting it to be log2(num bytes)-2
        (b) the loop is structured so that it will try and read the details of a non-existent cache level. although it doesn't read anything from CP15, it does result in the minimum cache line length values getting clobbered
        The net result of the above two bugs being that the OS would treat the CPU as if the minimum line length was just 4 bytes (although other than slowing down cache maintenance ops, this shouldn't have had any bad side-effects)
        The cache type register directly contains the minimum line lengths as log2(num bytes)-2, so by switching over to use that everything is now fine.
        Tested on BB-xM, Pandaboard
        Fixes issue spotted by Willi Theiss
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_251'
  32. 21 Dec, 2014 2 commits
    • Robert Sprowson's avatar
      Delegate L2 (and below) cache init at power on/reset to the HAL · 16c00596
      Robert Sprowson authored
      Historically the kernel looked after all aspects of cache control since they were common across all ARMs. However, not all cache controllers are created equal, and sometimes more complex initialisation steps are needed than fit the generic coprocessor ops - for example the PL310 attached to a Cortex-A9 has memory mapped control registers.
      Rather than clutter the kernel with one shot init code for every cache controller invented, we delegate that step to the HAL in HAL_Init. This is only a few hundred instructions later than where it was already being set. The kernel remains responsible for subsequent maintenance, this is just init which is being handed off.
      A quick survey of the Cortex-A TRMs shows:
      A5 - optional, for example ARM's PL310, ref TRM section 8.1.7.
      A7 - optional, C bit of SCTLR, ref TRM section 1.1.
      A8 - L2EN bit of ACTLR, note this bit has been recycled for other uses on other cores, ref TRM section 8.3.
      A9 - not integrated, ARM's PL310 uses bit 0 of control register 1, ref PL310 TRM section 3.1.1.
      A12 - see A17
      A15 - integrated, C bit of SCTLR, ref TRM section 7.2.3.
      A17 - integrated, bit 18 of L2CTLR & C bit of SCTLR, ref TRM section 7.2.
      and while we've got the TRMs open, back fill the CPU id register table.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_250'
    • Robert Sprowson's avatar
      Use symbol for GraphicsV op · 13123813
      Robert Sprowson authored
  33. 06 Dec, 2014 2 commits
    • Robert Sprowson's avatar
      Untangle some buses · aaddca77
      Robert Sprowson authored
       More clearly describe the intent of the different bus types.
       Reclassify the OMAP interconnect as either a system bus or peripheral bus, noting their names from the datasheet.
       Reclassify the GPMC as an expansion bus.
       Add AMBA 3's AXI bus, which (along with the existing AHB/APB) is what iMx6 uses. Delete redundant iMx6 interconnect type.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_249'
    • Robert Sprowson's avatar
      Fixes to HAL memory info calls and docs · 75de3830
      Robert Sprowson authored
       Several places in this code called the HAL or other ATPCS defined functions like memset() and hoped that the overall result was V clear. If any of them accidentally set V (for example a CMP that straddles 0x80000000) you ended up trying to look up an international error at the address of the reason code to OS_Memory.
       Now, explicitly clear V in the non error cases where an ATPCS function was called.
       Change the HAL_PhysInfo call to expect a physical ROM size back as an inclusive range, to match the RAM range subreason code. Add 1 to correct for this. A value of 0 & 0 is taken to mean "no physical ROM" as before.
       Document that 255 means "no IOMD" or "no VIDC", that's what the HALs have been using since year dot.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_248'
  34. 13 Nov, 2014 1 commit
    • Robert Sprowson's avatar
      Add a means to write NetStnCMOS in a HAL world · 10a86092
      Robert Sprowson authored
      With ProtectStationID turned on there are no routes to writing the Econet station (or bottom octect of the IP address), a function previously fulfilled by the SetStation utility which pokes the hardware directly and doesn't fit into a HAL model.
      Add a new subreason to OS_NVMemory to perform this role. This SWI appeared for RISC OS 5.00, and errors unsupported subreasons, so there's a means of run tim selecting its use by checking the platform class and trying the SWI. All RISC OS 5 based platforms can always be upgraded to this version, since they're all still being maintained.
      hdr/Options: move the switch with the other options from osinit.s
      i2cutils.c: new subreason
      Ditch the 'ObsoleteNC1CMOS' switch, if it was obsolete for NC1, it's certainly obsolete now.
      Ditch unmaintained messages files for Morris4/Omega/Ursula projects.
      Tested on a Risc PC.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_247'