1. 30 Sep, 2019 1 commit
    • Jeffrey Lee's avatar
      Allow runtime adjustment of AplWorkMaxSize · 0aeea07f
      Jeffrey Lee authored
      Detail:
      This adds a new OS_DynamicArea reason code, 26, for adjusting
      AplWorkMaxSize at runtime. This allows compatibility tools such as
      Aemulor to adjust the limit without resorting to patching the kernel.
      Any adjustment made to the value will affect the upper limit of
      application space, and the lower limit of dynamic area placement.
      Attempting to adjust beyond the compile-time upper/default limit, or
      such that it will interfere with existing dynamic areas / wimpslots,
      will result in an error.
      
      Relevant forum thread:
      https://www.riscosopen.org/forum/forums/11/topics/14734
      
      Admin:
      Tested on BB-xM, desktop active & inactive
      
      Version 6.24. Tagged as 'Kernel-6_24'
      0aeea07f
  2. 13 Dec, 2016 3 commits
    • Jeffrey Lee's avatar
      Implement support for cacheable pagetables · 65fa6a28
      Jeffrey Lee authored
      Detail:
        Modern ARMs (ARMv6+) introduce the possibility for the page table walk hardware to make use of the data cache(s) when performing memory accesses. This can significantly reduce the cost of a TLB miss on the system, and since the accesses are cache-coherent with the CPU it allows us to make the page tables cacheable for CPU (program) accesses also, improving the performance of page table manipulation by the OS.
        Even on ARMs where the page table walk can't use the data cache, it's been measured that page table manipulation operations can still benefit from placing the page tables in write-through or bufferable memory.
        So with that in mind, this set of changes updates the OS to allow cacheable/bufferable page tables to be used by the OS + MMU, using a system-appropriate cache policy.
        File changes:
        - hdr/KernelWS - Allocate workspace for storing the page flags that are to be used by the page tables
        - hdr/OSMem - Re-specify CP_CB_AlternativeDCache as having a different behaviour on ARMv6+ (inner write-through, outer write-back)
        - hdr/Options - Add CacheablePageTables option to allow switching back to non-cacheable page tables if necessary. Add SyncPageTables var which will be set {TRUE} if either the OS or the architecture requires a DSB after writing to a faulting page table entry.
        - s/ARM600, s/VMSAv6 - Add new SetTTBR & GetPageFlagsForCacheablePageTables functions. Update VMSAv6 for wider XCBTable (now 2 bytes per element)
        - s/ARMops - Update pre-ARMv7 MMU_Changing ARMops to drain the write buffer on entry if cacheable pagetables are in use (ARMv7+ already has this behaviour due to architectural requirements). For VMSAv6 Normal memory, change the way that the OS encodes the cache policy in the page table entries so that it's more compatible with the encoding used in the TTBR.
        - s/ChangeDyn - Update page table page flag handling to use PageTable_PageFlags. Make use of new PageTableSync macro.
        - s/Exceptions, s/AMBControl/memmap - Make use of new PageTableSync macro.
        - s/HAL - Update MMU initialisation sequence to make use of PageTable_PageFlags + SetTTBR
        - s/Kernel - Add PageTableSync macro, to be used after any write to a faulting page table entry
        - s/MemInfo - Update OS_Memory 0 page flag conversion. Update OS_Memory 24 to use new symbol for page table access permissions.
        - s/MemMap2 - Use PageTableSync. Add routines to enable/disable cacheable pagetables
        - s/NewReset - Enable cacheable pagetables once we're fully clear of the MMU initialision sequence (doing earlier would be trickier due to potential double-mapping)
      Admin:
        Tested on pretty much everything currently supported
        Delivers moderate performance benefits to page table ops on old systems (e.g. 10% faster), astronomical benefits on some new systems (up to 8x faster)
        Stats: https://www.riscosopen.org/forum/forums/3/topics/2728?page=2#posts-58015
      
      
      Version 5.71. Tagged as 'Kernel-5_71'
      65fa6a28
    • Jeffrey Lee's avatar
      Make MMU_Changing ARMops perform the sub-operations in a sensible order · 9a96263a
      Jeffrey Lee authored
      Detail:
        For a while we've known that the correct way of doing cache maintenance on ARMv6+ (e.g. when converting a page from cacheable to non-cacheable) is as follows:
        1. Write new page table entry
        2. Flush old entry from TLB
        3. Clean cache + drain write buffer
        The MMU_Changing ARMops (e.g. MMU_ChangingEntry) implement the last two items, but in the wrong order. This has caused the operations to fall out of favour and cease to be used, even in pre-ARMv6 code paths where the effects of improper cache/TLB management perhaps weren't as readily visible.
        This change re-specifies the relevant ARMops so that they perform their sub-operations in the correct order to make them useful on modern ARMs, updates the implementations, and updates the kernel to make use of the ops whereever relevant.
        File changes:
        - Docs/HAL/ARMop_API - Re-specify all the MMU_Changing ARMops to state that they are for use just after a page table entry has been changed (as opposed to before - e.g. 5.00 kernel behaviour). Re-specify the cacheable ones to state that the TLB invalidatation comes first.
        - s/ARM600, s/ChangeDyn, s/HAL, s/MemInfo, s/VMSAv6, s/AMBControl/memmap - Replace MMU_ChangingUncached + Cache_CleanInvalidate pairs with equivalent MMU_Changing op
        - s/ARMops - Update ARMop implementations to do everything in the correct order
        - s/MemMap2 - Update ARMop usage, and get rid of some lingering sledgehammer logic from ShuffleDoublyMappedRegionForGrow
      Admin:
        Tested on pretty much everything currently supported
      
      
      Version 5.70. Tagged as 'Kernel-5_70'
      9a96263a
    • Jeffrey Lee's avatar
      Reimplement AMBControl ontop of the PMP system · cefb4815
      Jeffrey Lee authored
      Detail:
        With this set of changes, each AMB node is now the owner of a fake DANode which is linked to a PMP.
        From a user's perspective the behaviour of AMBControl is the same as before, but rewriting it to use PMPs internally offers the following (potential) benefits:
        * Reduction in the amount of code which messes with the CAM & page tables, simplifying future work/maintenance. Some of the AMB ops (grow, shrink) now just call through to OS_ChangeDynamicArea. However all of the old AMB routines were well-optimised, so to avoid a big performance hit for common operations not all of them have been removed (e.g. mapslot / mapsome). Maybe one day these optimal routines will be made available for use by regular PMP DAs.
        * Removal of the slow Service_MemoryMoved / Service_PagesSafe handlers that had to do page list fixup after the core kernel had reclaimed/moved pages. Since everything is a PMP, the kernel will now deal with this on behalf of AMB.
        * Removal of a couple of other slow code paths (e.g. Do_AMB_MakeUnsparse calls from OS_ChangeDynamicArea)
        * Potential for more flexible mapping of application space in future, e.g. sparse allocation of memory to the wimp slot
        * Simpler transition to an ASID-based task swapping scheme on ARMv6+?
        Other changes of note:
        * AMB_LazyMapIn switch has been fixed up to work correctly (i.e. turning it off now disables lazy task swapping and all associated code instead of producing a build error)
        * The DANode for the current app should be accessed via the GetAppSpaceDANode macro. This will either return the current AMB DANode, or AppSpaceDANode (if e.g. pre-Wimp). However be aware that AppSpaceDANode retains the legacy behaviour of having a base + size relative to &0, while the AMB DANodes (identifiable via the PMP flag) are sane and have their base + size relative to &8000.
        * Mostly-useless DebugAborts switch removed
        * AMBPhysBin (page number -> phys addr lookup table) removed. Didn't seem to give any tangible performance benefit, and was imposing hidden restrictions on memory usage (all phys RAM fragments in PhysRamTable must be multiple of 512k). And if it really was a good optimisation, surely it should have been applied to all areas of the kernel, not just AMB!
        Other potential future improvements:
        * Turn the fake DANodes into real dynamic areas, reducing the amount of special code needed in some places, but allow the DAs to be hidden from OS_DynamicArea 3 so that apps/users won't get too confused
        * Add a generic abort trapping system to PMPs/DAs (lazy task swapping abort handler is still a special case)
        File changes:
        - s/ARM600, s/VMSAv6, s/ExtraSWIs - Remove DebugAborts
        - s/ArthurSWIs - Remove AMB service call handler dispatch
        - s/ChangeDyn - AMB_LazyMapIn switch fixes. Add alternate internal entry points for some PMP ops to allow the DANode to be specified (used by AMB)
        - s/Exceptions - Remove DebugAborts, AMB_LazyMapIn switch fixes
        - s/Kernel - Define GetAppSpaceDANode macro, AMB_LazyMapIn switch fix
        - s/MemInfo - AMB_LazyMapIn switch fixes
        - s/AMBControl/AMB - Update GETs
        - s/AMBControl/Memory - Remove block size quantisation, AMB_BlockResize (page list blocks are now allocated by PMP code)
        - s/AMBControl/Options - Remove PhysBin definitions, AMBMIRegWords (moved to Workspace file), AMB_LimpidFreePool switch. Add AMB_Debug switch.
        - s/AMBControl/Workspace - Update AMBNode to contain an embedded DANode. Move AMBMIRegWords here from Options file.
        - s/AMBControl/allocate - Fake DA node initialisation
        - s/AMBControl/deallocate - Add debug output
        - s/AMBControl/growp, growshrink, mapslot, mapsome, shrinkp - Rewrite to use PMP ops where possible, add debug output
        - s/AMBControl/main - Remove PhysBin initialisation. Update the enumerate/mjs_info call.
        - s/AMBControl/memmap - Low-level memory mapping routines updated or rewritten as appropriate.
        - s/AMBControl/readinfo - Update to cope with DANode
        - s/AMBControl/service - Remove old service call handlers
        - s/AMBControl/handler - DA handler for responding to PMP calls from OS_ChangeDynamicArea; just calls through to growpages/shrinkpages as appropriate.
      Admin:
        Tested on pretty much everything currently supported
      
      
      Version 5.66. Tagged as 'Kernel-5_66'
      cefb4815
  3. 02 Aug, 2016 1 commit
    • Jeffrey Lee's avatar
      Add support for shareable pages and additional access privileges · 9cd4cbe4
      Jeffrey Lee authored
      Detail:
        This set of changes:
        * Refactors page table entry encoding/decoding so that it's (mostly) performed via functions in the MMU files (s.ARM600, s.VMSAv6) rather than on an ad-hoc basis as was the case previously
        * Page table entry encoding/decoding performed during ROM init is also handled via the MMU functions, which resolves some cases where the wrong cache policy was in use on ARMv6+
        * Adds basic support for shareable pages - on non-uniprocessor systems all pages will be marked as shareable (however, we are currently lacking ARMops which broadcast cache maintenance operations to other cores, so safe sharing of cacheable regions isn't possible yet)
        * Adds support for the VMSA XN flag and the "privileged ROM" access permission. These are exposed via RISC OS access privileges 4 and above, taking advantage of the fact that 4 bits have always been reserved for AP values but only 4 values were defined
        * Adds OS_Memory 17 and 18 to convert RWX-style access flags to and from RISC OS access privelege numbers; this allows us to make arbitrary changes to the mappings of AP values 4+ between different OS/hardware versions, and allows software to more easily cope with cases where the most precise AP isn't available (e.g. no XN on <=ARMv5)
        * Extends OS_Memory 24 (CheckMemoryAccess) to return executability information
        * Adds exported OSMem header containing definitions for OS_Memory and OS_DynamicArea
        File changes:
        - Makefile - export C and assembler versions of hdr/OSMem
        - Resources/UK/Messages - Add more text for OS_Memory errors
        - hdr/KernelWS - Correct comment regarding DCacheCleanAddress. Allocate workspace for MMU_PPLTrans and MMU_PPLAccess.
        - hdr/OSMem - New file containing exported OS_Memory and OS_DynamicArea constants, and public page flags
        - hdr/Options - Reduce scope of ARM6support to only cover builds which require ARMv3 support
        - s/AMBControl/Workspace - Clarify AMBNode_PPL usage
        - s/AMBControl/growp, mapslot, mapsome, memmap - Use AreaFlags_ instead of AP_
        - s/AMBControl/main, memmap - Use GetPTE instead of generating page table entry manually
        - s/ARM600 - Remove old coments relating to lack of stack. Update BangCam to use GetPTE. Update PPL tables, removing PPLTransL1 (L1 entries are now derived from L2 table on demand) and adding a separate table for ARM6. Implement the ARM600 versions of the Get*PTE ('get page table entry') and Decode*Entry functions
        - s/ARMops - Add Init_PCBTrans function to allow relevant MMU_PPLTrans/MMU_PCBTrans pointers to be set up during the pre-MMU stage of ROM init. Update ARM_Analyse to set up the pointers that are used post MMU init.
        - s/ChangeDyn - Move a bunch of flags to hdr/OSMem. Rename the AP_ dynamic area flags to AreaFlags_ to avoid name clashes and confusion with the page table AP_ values exported by Hdr:MEMM.ARM600/Hdr:MEMM.VMSAv6. Also generate the relevant flags for OS_Memory 24 so that it can refer to the fixed areas by their name instead of hardcoding the permissions.
        - s/GetAll - GET Hdr:OSMem
        - s/HAL - Change initial page table setup to use DA/page flags and GetPTE instead of building page table entries manually. Simplify AllocateL2PT by removing the requirement for the user to supply the access perimssions that will be used for the area; instead for ARM6 we just assume that cacheable memory is the norm and set L1_U for any L1 entry we create here.
        - s/Kernel - Add GetPTE macro (for easier integration of Get*PTE functions) and GenPPLAccess macro (for easy generation of OS_Memory 24 flags)
        - s/MemInfo - Fixup OS_Memory 0 to not fail on seeing non-executable pages. Implement OS_Memory 17 & 18. Tidy up some error generation. Make OS_Memory 13 use GetPTE. Extend OS_Memory 24 to return (non-) executability information, to use the named CMA_ constants generated by s/ChangeDyn, and to use the Decode*Entry functions when it's necessary to decode page table entries.
        - s/NewReset - Use AreaFlags_ instead of AP_
        - s/VMSAv6 - Remove old comments relating to lack of stack. Update BangCam to use GetPTE. Update PPL tables, removing PPLTransL1 (L1 entries are now derived from L2 table on demand) and adding a separate table for shareable pages. Implement the VMSAv6 versions of the Get*PTE and Decode*Entry functions.
      Admin:
        Tested on Raspberry Pi 1, Raspberry Pi 3, Iyonix, RPCEmu (ARM6 & ARM7), comparing before and after CAM and page table dumps to check for any unexpected differences
      
      
      Version 5.55. Tagged as 'Kernel-5_55'
      9cd4cbe4
  4. 30 Jun, 2016 1 commit
    • Jeffrey Lee's avatar
      Delete pre-HAL and 26bit code · 7d5bfc66
      Jeffrey Lee authored
      Detail:
        This change gets rid of the following switches from the source (picking appropriate code paths for a 32bit HAL build):
        * HAL
        * HAL26
        * HAL32
        * No26bitCode
        * No32bitCode
        * IncludeTestSrc
        * FixR9CorruptionInExtensionSWI
        Various old files have also been removed (POST code, Arc/STB keyboard drivers, etc.)
      Admin:
        Identical binary to previous revision for IOMD & Raspberry Pi builds
      
      
      Version 5.49. Tagged as 'Kernel-5_49'
      7d5bfc66
  5. 10 Mar, 2016 1 commit
    • Jeffrey Lee's avatar
      Cache maintenance fixes · b0682acb
      Jeffrey Lee authored
      Detail:
        This set of changes tackles two main issues:
        * Before mapping out a cacheable page or making it uncacheable, the OS performs a cache clean+invalidate op. However this leaves a small window where data may be fetched back into the cache, either accidentally (dodgy interrupt handler) or via agressive prefetch (as allowed for by the architecture). This rogue data can then result in coherency issues once the pages are mapped out or made uncacheable a short time later.
          The fix for this is to make the page uncacheable before performing the cache maintenance (although this isn't ideal, as prior to ARMv7 it's implementation defined whether address-based cache maintenance ops affect uncacheable pages or not - and on ARM11 it seems that they don't, so for that CPU we currently force a full cache clean instead)
        * Modern ARMs generally ignore unexpected cache hits, so there's an interrupt hole in the current OS_Memory 0 "make temporarily uncacheable" implementation where the cache is being flushed after the page has been made uncacheable (consider the case of a page that's being used by an interrupt handler, but the page is being made uncacheable so it can also be used by DMA). As well as affecting ARMv7+ devices this was found to affect XScale (and ARM11, although untested for this issue, would have presumably suffered from the "can't clean uncacheable pages" limitation)
          The fix for this is to disable IRQs around the uncache sequence - however FIQs are currently not being dealt with, so there's still a potential issue there.
        File changes:
        - Docs/HAL/ARMop_API, hdr/KernelWS, hdr/OSMisc - Add new Cache_CleanInvalidateRange ARMop
        - s/ARM600, s/VMSAv6 - BangCam updated to make the page uncacheable prior to flushing the cache. Add GetTempUncache macro to help with calculating the page flags required for making pages uncacheable. Fix abort in OS_MMUControl on Raspberry Pi - MCR-based ISB was resetting ZeroPage pointer to 0
        - s/ARMops - Cache_CleanInvalidateRange implementations. PL310 MMU_ChangingEntry/MMU_ChangingEntries refactored to rely on Cache_CleanInvalidateRange_PL310, which should be a more optimal implementation of the cache cleaning code that was previously in MMU_ChangingEntry_PL310.
        - s/ChangeDyn - Rename FastCDA_UpFront to FastCDA_Bulk, since the cache maintenance is no longer performed upfront. CheckCacheabilityR0ByMinusR2 now becomes RemoveCacheabilityR0ByMinusR2. PMP LogOp implementation refactored quite a bit to perform cache/TLB maintenance after making page table changes instead of before. One flaw with this new implementation is that mapping out large areas of cacheable pages will result in multiple full cache cleans while the old implementation would have (generally) only performed one - a two-pass approach over the page list would be needed to solve this.
        - s/GetAll - Change file ordering so GetTempUncache macro is available earlier
        - s/HAL - ROM decompression changed to do full MMU_Changing instead of MMU_ChangingEntries, to make sure earlier cached data is truly gone from the cache. ClearPhysRAM changed to make page uncacheable before flushing cache.
        - s/MemInfo - OS_Memory 0 interrupt hole fix
        - s/AMBControl/memmap - AMB_movepagesout_L2PT now split into cacheable+non-cacheable variants. Sparse map out operation now does two passes through the page list so that they can all be made uncacheable prior to the cache flush + map out.
      Admin:
        Tested on StrongARM, XScale, ARM11, Cortex-A7, Cortex-A9, Cortex-A15, Cortex-A53
        Appears to fix the major issues plaguing SATA on IGEPv5
      
      
      Version 5.35, 4.79.2.306. Tagged as 'Kernel-5_35-4_79_2_306'
      b0682acb
  6. 06 Sep, 2015 1 commit
    • Jeffrey Lee's avatar
      Misc memory management tweaks & fixes · 943c4964
      Jeffrey Lee authored
      Detail:
        s/ChangeDyn - Fix OS_DynamicArea 20 to work properly with sparse & PMP DAs. It now checks against the max extent of the area rather than the current size; this matches the logic used for checking fixed system workspace areas. The call only determines the ownership of a logical address, and it's considered the caller's responsibility to check if there's actually a page at the given address.
        s/ChangeDyn - Revise OS_DynamicArea 25 to remove the redundant 'PMP page flags' entry, and to allow pages to be looked up by either PMP page index, phys page number, or DA page index
        s/ChangeDyn - Tidy up InitDynamicAreas by adding the NextFreePage routine to help determine the next page to be added to the free pool.
        s/AMBControl/Workspace, s/AMBControl/main, s/AMBControl/memmap - Fix lazy mapping in of pages to use the correct L2PT flags for the default CB cache policy
        s/AMBControl/allocate - Get rid of magic constant when extracting page flags from DA flags, and make note of the fact that assorted bits of code ignore the flags
        s/AMBControl/growp, s/AMBControl/shrinkp - Reverse the page order when growing/shrinking areas, to match OS_ChangeDynamicArea. This helps both DAs and application space to have pages allocated to them in contiguous physical order - which in turn helps produce shorter, more optimal scatter lists for DMA
      Admin:
        Tested on Pandaboard
      
      
      Version 5.35, 4.79.2.287. Tagged as 'Kernel-5_35-4_79_2_287'
      943c4964
  7. 31 Aug, 2015 1 commit
    • Jeffrey Lee's avatar
      Add initial support for "physical memory pools" · 54872d8c
      Jeffrey Lee authored
      Detail:
        This set of changes adds support for "physical memory pools" (aka PMPs), a new type of dynamic area which allow physical pages to be claimed/allocated without mapping them in to the logical address space. PMPs have full control over which physical pages they use (similar to DAs which request specific physical pages), and also have full control over the logical mapping of their pages (which pages go where, and per-page access/cacheability control).
        Currently the OS makes use of two PMPs: one for the free pool (which now has a logical size of zero - freeing up gigabytes of logical space), and one for the RAM disc (logical size of 1MB, allowing for a physical size limited only by the amount of free memory)
        Implementing these changes has required a number of other changes to be made:
        * The CAM has been expanded from 8 bytes per entry to 16 bytes per entry, in order to allow each RAM page to store information about its PMP association
        * The system heap has been expanded to 32MB in size (from just under 4MB), in order to allow it to be used to store PMP page lists (1 word needed per page, but PMP pages may not always have physical pages assigned to them - so to allow multiple large PMPs to exist we need more than just 1 word per RAM page)
        * The &FA000000-&FBFFFFFF area of fixed kernel workspace has been shuffled around to accomodate the larger CAM, and the system heap is now located just above the RMA.
        * SoftResets code stripped out (unlikely we'll ever want to fix and re-enable it)
        * A couple of FastCDA options are now permanently on
        * Internal page flags shuffled around a bit. PageFlags_Unavailable now publicly exposed so that PMP clients can lock/unlock pages at will.
        * When OS_ChangeDynamicArea is asked to grow or shrink the free pool, it now implicitly converts it into a shrink or grow of application space (which is what would happen anyway). This simplifies the implementation; during a grow, pages (or replacement pages) are always sourced from the free pool, and during a shrink pages are always sent to the free pool.
        File changes:
        - hdr/KernelWS - Extend DANode structure. Describe CAM format. Adjust kernel workspace.
        - hdr/OSRSI6, s/Middle - Add new item to expose the CAM format
        - hdr/Options - Remove SoftResets switch. Add some PMP switches.
        - s/ARM600, s/VMSAv6 - Updated for new CAM format. Note that although the CAM stores PMP information, BangCamUpdate currently doesn't deal with updating that data - it's the caller's responsibility to do so where appropriate.
        - s/ChangeDyn - Lots of changes to implement PMP support, and to cope with the new CAM format.
        - s/HAL - Updated to cope with new CAM format, and lack of logical mapping of free pool.
        - s/MemInfo - Updated to cope with new CAM format. OS_Memory 0 updated to cope with converting PPN to PA for pages which are mapped out. OS_Memory 24 updated to decode the access permissions on a per-page basis for PMPs, and fixed its HWM usage for sparse DAs.
        - s/NewReset - Soft reset code and unused AddCamEntries function removed. Updated to cope with new CAM format, PMP free pool, PMP RAMFS
        - s/AMBControl/allocate - Update comment (RMA hasn't been used for AMBControl nodes for a long time)
        - s/AMBControl/growp, s/AMBControl/memmap, s/AMBControl/shrinkp - Update for new CAM format + PMP free pool
        - s/vdu/vdudriver - Strip out soft reset code.
      Admin:
        Tested on Pandaboard
        This is just a first iteration of the PMP feature, with any luck future changes will improve functionality. This means APIs are subject to change as well.
      
      
      Version 5.35, 4.79.2.284. Tagged as 'Kernel-5_35-4_79_2_284'
      54872d8c
  8. 05 Aug, 2015 1 commit
    • Jeffrey Lee's avatar
      Improve support for VMSAv6 cache policies & memory types. Expose raw ARMops... · afb010f2
      Jeffrey Lee authored
      Improve support for VMSAv6 cache policies & memory types. Expose raw ARMops via OS_MMUControl & cache information via OS_PlatformFeatures.
      
      Detail:
        Docs/HAL/ARMop_API - Document two new ARMops: Cache_Examine and IMB_List
        hdr/KernelWS - Shuffle workspace round a bit to allow space for the two new ARMops. IOSystemType now deleted (has been deprecated and fixed at 0 for some time)
        s/ARM600 - Cosmetic changes to BangCam to make it clearer what's going on. Add OS_MMUControl 2 (get ARMop) implementation.
        s/ARMops - Switch out different ARMop implementations and XCB tables depending on MMU model - helps reduce assembler warnings and make it clearer what code paths are and aren't possible. Add implementations of the two new ARMops. Simplify ARM_Analyse_Fancy by removing some tests which we know will have certain results. Use CCSIDR constants in ARMv7 ARMops instead of magic numbers. Update XCB table comments, and add a new table for VMSAv6
        s/ChangeDyn - Define constant for the new NCB 'idempotent' cache policy (VMSAv6 normal, non-cacheable memory)
        s/HAL - Use CCSIDR constants instead of magic numbers. Extend RISCOS_MapInIO to allow the TEX bits to be specified.
        s/Kernel - OS_PlatformFeatures 33 (read cache information) implementation (actually, just calls through to an ARMop)
        s/MemInfo - Modify VMSAv6 OS_Memory 0 cache/uncache implementation to use the XCB table instead of modifying L2_C directly. This allows the cacheability to be changed without affecting the memory type - important for e.g. unaligned accesses to work correctly. Implement cache policy support for OS_Memory 13.
        s/Middle - Remove IOSystemType from OS_ReadSysInfo 6.
        s/VMSAv6 - Make sure BangCam uses the XCB table for working out the attributes of temp-uncacheable pages instead of manipulating L2_C directly. Add OS_MMUControl 2 implementation.
        s/AMBControl/memmap - Update VMSAv6 page table pokeing to use XCB table
        s/PMF/osinit - Remove IOSystemType reference, and switch out some pre-HAL code that was trying to use IOSystemType.
      Admin:
        Tested on Iyonix, ARM11, Cortex-A7, -A8, -A9, -A15
        Note that contrary to the comments in the source the default NCB policy currently maps to VMSAv6 Device memory type (as per previous kernel versions). This is just a temporary measure, and it will be switched over to Normal, non-cacheable once appropriate memory barriers have been added to the affected IO code.
      
      
      Version 5.35, 4.79.2.273. Tagged as 'Kernel-5_35-4_79_2_273'
      afb010f2
  9. 20 Jan, 2015 1 commit
    • Jeffrey Lee's avatar
      Perform extra TLB maintenance on ARMv6+. Other cache/TLB maintenance tweaks. · aca7f939
      Jeffrey Lee authored
      Detail:
        s/ARMops - Implement Cache_RangeThreshold for PL310 (helps AMBControl to decide what type of TLB maintenance is best). Fix MMU_ChangingEntry_PL310 doing more work than is necessary; was attempting to flush all ways for a given address tag, when really it should have only been flushing all the lines within a page and letting the cache worry about the tags/indices they correspond to.
        s/ChangeDyn, s/VMSAv6, s/AMBControl/memmap - Do extra TLB maintenance following writes to the page tables, as mandated by the ARMv6+ memory order model. Fixes frequent crashes on Cortex-A9 when running with lazy task swapping disabled (and presumably fixes other crashes too)
        s/MemInfo - Fix OS_Memory cache/uncache so that it does cache/TLB maintenance on a per-page basis instead of a global basis. Vastly improves performance when you have a large cache, but may need tweaking again in future to do a global op if large numbers of pages are being modified.
      Admin:
        Tested on Pandaboard
      
      
      Version 5.35, 4.79.2.255. Tagged as 'Kernel-5_35-4_79_2_255'
      aca7f939
  10. 15 Oct, 2014 1 commit
    • John Ballance's avatar
      Re enable compile with kernel built from current tree. · 0564d81c
      John Ballance authored
      Detail:
      Recent kernal changes appear to have enabled lazy task swapping, which brought
      up a data alignment abort whilst compiling the source tree using a rom compiled
      from this tree. Simple change added
      to AMB_MakeHonestLA and PN routines to avoid this.
      
      Admin:
        (highlight level of testing that has taken place)
        (bugfix number if appropriate)
      
      
      Version 5.35, 4.79.2.240. Tagged as 'Kernel-5_35-4_79_2_240'
      0564d81c
  11. 28 Mar, 2013 1 commit
    • Jeffrey Lee's avatar
      Teach the kernel about different memory attributes · c40b2dba
      Jeffrey Lee authored
      Detail:
        Briefly, this set of changes:
        * Adjusts PhysRamTable so that it retains the flags passed in by the HAL from OS_AddRAM (by storing them in the lower 12 bits of the size field)
        * Sorts the non-VRAM entries of PhysRamTable by speed and DMA capability, to ensure optimal memory allocation during OS startup.
        * Adjust the initial memory allocation logic to allow the cursor/sound chunk and HAL noncacheable workspace to come from DMA capable memory
        * Extends OS_Memory 12 to accept a 'must be DMA capable' flag in bit 8 of R0. This is the same as available in ROL's OS.
        * Extends OS_DynamicArea 0 to allow the creation of dynamic areas that automatically allocate from DMA capable memory. In ROL's OS this was done by setting bit 12 of R4, but we're using bits 12-14 for specifying the cache policy, so instead bit 15 is used.
        * Fixes OS_ReadSysInfo 6 to return the correct DevicesEnd value now that the IRQ/device limit is computed at runtime
        File changes:
        * hdr/OSEntries - Add definitions of the various flags passed to OS_AddRAM by the HAL. Add a new flag, NoDMA, for memory which can't be used for DMA.
        * hdr/KernelWS - Tidy PhysRamTable definition a bit by removing all the DRAM bank definitions except the first - this makes it easier to search for code which is interacting with the table. Remove VRAMFlags, it's redundant now that the flags are kept in the table. Add DMA allocation info to InitWs.
        * s/AMBControl/memmap - Updated to mask out the flags from PhysRamTable when reading RAM block sizes.
        * s/ARM600 - Strip out a lot of IOMD specific pre-HAL code.
        * s/ChangeDyn - Updated to cope with the flags stored in PhysRamTable. Implement support for DMA-capable dynamic areas. Rewrite InitDynamicAreas to insert pages into the free pool in the right order so that the fastest memory will be taken from it first.
        * s/GetAll, s/Middle - Fix OS_ReadSysInfo 6 to return the correct HAL-specific DevicesEnd value
        * s/HAL - Significant rework of initial RAM allocation code to allow the kernel workspace to come from the fastest DMA incapable RAM, while also allowing allocation of DMA capable memory for HAL NCNB workspace & kernel cursor/sound chunks. ClearPhysRAM rewritten as part of this.
        * s/MemInfo - Updated to cope with the flags stored in PhysRamTable. Add support for the new OS_Memory 12 flag. Update OS_Memory 7 to not assume PhysRamTable entries are sorted in address order, and rip out the old pre-HAL IOMD implementation.
        * s/NewReset - Remove GetPagesFromFreePool option, assume TRUE (as this has been the case for the past 10+ years). Revise a few comments and strip dead code. Update to cope with PhysRamTable flags.
        * s/VMSAv6 - Remove a couple of unused definitions
        * s/vdu/vdudriver - Update to cope with PhysRamTable flags
      Admin:
        Tested in Kinetic RiscPC ROM softload, Iyonix softload, & OMAP3
      
      
      Version 5.35, 4.79.2.186. Tagged as 'Kernel-5_35-4_79_2_186'
      c40b2dba
  12. 08 Aug, 2011 1 commit
    • Jeffrey Lee's avatar
      Add zero page relocation support · 2247d8e9
      Jeffrey Lee authored
      Detail:
        A whole mass of changes to add high processor vectors + zero page relocation support to the Cortex branch of the kernel
        At the moment the code can only cope with two ZeroPage locations, &0 and &FFFF0000. But with a bit more tweaking those restrictions can probably be lifted, allowing ZeroPage to be hidden at almost any address (assuming it's fixed at compile time). If I've done my job right, these restrictions should all be enforced by asserts.
        There's a new option, HiProcVecs, in hdr/Options to control whether high processor vectors are used. When enabling it and building a ROM, remember:
        * FPEmulator needs to be built with the FPEAnchor=High option specified in the components file (not FPEAnchorType=High as my FPEmulator commit comments suggested)
        * ShareFS needs unplugging/removing since it can't cope with it yet
        * Iyonix users will need to use the latest ROOL boot sequence, to ensure the softloaded modules are compatible (OMAP, etc. don't really softload much so they're OK with older sequences)
        * However VProtect also needs patching to fix a nasty bug there - http://www.riscosopen.org/tracker/tickets/294
        The only other notable thing I can think of is that the ProcessTransfer code in s/ARM600 & s/VMSAv6 is disabled if high processor vectors are in use (it's fairly safe to say that code is obsolete in HAL builds anyway?)
        Fun challenge for my successor: Try setting ZeroPage to &FFFF00FF (or similar) so its value can be loaded with MVN instead of LDR. Then use positive/negative address offsets to access the contents.
        File changes:
        - hdr/ARMops - Modified ARMop macro to take the ZeroPage pointer as a parameter instead of 'zero'
        - hdr/Copro15ops - Corrected $quick handling in myISB macro
        - hdr/Options - Added ideal setting for us to use for HiProcVecs
        - s/AMBControl/allocate, s/AMBControl/growp, s/AMBControl/mapslot, s/AMBControl/memmap, s/AMBControl/service, s/AMBControl/shrinkp, s/Arthur2, s/Arthur3, s/ArthurSWIs, s/ChangeDyn, s/ExtraSWIs, s/HAL, s/HeapMan, s/Kernel, s/MemInfo, s/Middle, s/ModHand, s/MoreSWIs, s/MsgCode, s/NewIRQs, s/NewReset, s/Oscli, s/PMF/buffer, s/PMF/IIC, s/PMF/i2cutils, s/PMF/key, s/PMF/mouse, s/PMF/osbyte, s/PMF/oseven, s/PMF/osinit, s/PMF/osword, s/PMF/oswrch, s/SWINaming, s/Super1, s/SysComms, s/TickEvents, s/Utility, s/vdu/vdu23, s/vdu/vdudriver, s/vdu/vdugrafl, s/vdu/vdugrafv, s/vdu/vdupalxx, s/vdu/vdupointer, s/vdu/vduswis, s/vdu/vduwrch - Lots of updates to deal with zero page relocation
        - s/ARM600 - UseProcessTransfer option. Zero page relocation support. Deleted pre-HAL ClearPhysRAM code to tidy the file up a bit.
        - s/ARMops - Zero page relocation support. Set CPUFlag_HiProcVecs when high vectors are in use.
        - s/KbdResPC - Disable compilation of dead code
        - s/VMSAv6 - UseProcessTransfer option. Zero page relocation support.
      Admin:
        Tested with OMAP & Iyonix ROM softloads, both with high & low zero page.
        High zero page hasn't had extensive testing, but boot sequence + ROM apps seem to work.
      
      
      Version 5.35, 4.79.2.98.2.48. Tagged as 'Kernel-5_35-4_79_2_98_2_48'
      2247d8e9
  13. 04 Jun, 2011 1 commit
    • Jeffrey Lee's avatar
      Add hdr.Variables to the C header export, fix ARMv6 issues · b8267d5d
      Jeffrey Lee authored
      Detail:
        Makefile - Added hdr.Variables to the C header export list
        hdr/ARMops, s/ARMops - Added ARM1176JZF-S to the list of known CPUs
        s/ARMops - Fix unaligned memory access in ARM_PrintProcessorType
        hdr/Copro15ops, s/ARMops, s/HAL, s/VMSAv6, s/AMBControl/memmap - Fixed all myDSB/myISB/etc. macro instances to specify a temp register, so that they work properly when building an ARMv6 version of the kernel
      Admin:
        Fixes build errors with the latest Draw module.
        Should also allow the kernel to work properly with the new S3C6410 port.
        ARMv6 version builds OK, but no other builds or runtime tests have been made.
      
      
      Version 5.35, 4.79.2.98.2.38. Tagged as 'Kernel-5_35-4_79_2_98_2_38'
      b8267d5d
  14. 04 Oct, 2010 1 commit
    • Jeffrey Lee's avatar
      Fix some issues preventing the Cortex kernel from being used on non-Cortex machines · e718080c
      Jeffrey Lee authored
      Detail:
        hdr/Options - ARM6support and GetKernelMEMC values are now derived from the value of MEMM_Type
        s/ARMops, s/HAL - Code to detect and handle ARMv7 CPUs is now only enabled when using VMSAv6 MMU model. Saves us from having to deal with lack of myIMB, myDSB, etc. implementations on pre-ARMv6.
        s/HAL - Removed some debug code
        s/NewReset - Fix bug spotted by Tom Walker where R12 wasn't being restored by LookForHALRTC if a non-HAL RTC had already been found
        s/AMBControl/memmap - correct the assert clause that was checking that &FFE are the correct L2PT protection bits for non-VMSAv6 machines
      Admin:
        Tested this kernel on a rev C2 beagleboard & Iyonix softload. Also compiled it into an IOMD ROM, but didn't try running it.
      
      
      Version 5.35, 4.79.2.98.2.32. Tagged as 'Kernel-5_35-4_79_2_98_2_32'
      e718080c
  15. 23 Jun, 2010 1 commit
    • Jeffrey Lee's avatar
      Update Cortex kernel to use correct instruction/memory barriers and to perform... · de8e610e
      Jeffrey Lee authored
      Update Cortex kernel to use correct instruction/memory barriers and to perform branch target predictor maintenance. Plus tweak default CMOS settings.
      
      Detail:
        hdr/Copro15ops - Added myISB, myDSB, myDMB macros to provide barrier functionality on ARMv6+
        s/ARMops, s/HAL, s/VMSAv6, s/AMBControl/memmap - Correct barrier operations are now performed on ARMv6+ following CP15 writes. Branch predictors are now also maintained properly.
        s/NewReset - Change default CMOS settings so number of CDFS drives is 0 in Cortex builds. Fixes rogue CDFS icon on iconbar.
      Admin:
        Tested on rev C2 beagleboard
      
      
      Version 5.35, 4.79.2.98.2.27. Tagged as 'Kernel-5_35-4_79_2_98_2_27'
      de8e610e
  16. 10 May, 2009 1 commit
    • Jeffrey Lee's avatar
      Assorted kernel fixes for ARMv6/ARMv7 · ca8f36f5
      Jeffrey Lee authored
      Detail:
        s/ARMops - Fix IMB_Range_WB_CR7_Lx to clean the correct number of cache lines
        s/HAL - Change CP15 control register flags so unaligned loads are enabled on ARMv6 (to simplify support for ARMv7 where unaligned loads are always enabled, and to match the behaviour expected by the example code in Hdr:CPU.Arch)
        s/AMBControl/memmap - Make AMB_LazyFixUp use the correct L2PT protection flags depending on ARM600/VMSAv6 MMU model. Also guard against problems caused by future L2PT flag changes.
        s/vdu/vdugrafj - Fix previously undiscovered 32bit incompatability in GetSprite (OS_SpriteOp 14/16)
      Admin:
        Tested on rev C2 beagleboard
      
      
      Version 5.35, 4.79.2.98.2.5. Tagged as 'Kernel-5_35-4_79_2_98_2_5'
      ca8f36f5
  17. 30 Nov, 2002 1 commit
    • Ben Avison's avatar
      Commit of kernel as featured in release 5.00. · 9664c93b
      Ben Avison authored
      Detail:
        Lots of changes since last version, at least the following:
        * Updated OS timestamp, removed alpha status
        * Negative INKEY OS version changed to &AA
        * GraphicsV is now alocated vector number &2A
        * ROM moved up to &FC000000
        * Max application slot increased to 512 Mbytes (for now)
        * Max size of RMA increased to 256 Mbytes
        * RMA is now first-created dynamic area (so it gets lowest address after
          top of application slot)
        * OS_Memory 10 reimplemeted
        * New OS_ReadSysInfo 6 values 18-22 added
        * OS_ReadSysInfo 8 gains flag bit to indicate soft power-off
        * Misc internal top-bit-set-address fixes
        * *ChangeDynamicArea can take sizes in megabytes or gigabytes
        * Magic word "&off" in R0 passed to OS_Reset powers down if possible
        * Added acceleration: block copy; CLS; text window scroll up; rectangle
          fill
        * Disabled LED flashing in page mode (liable to crash)
        * Masked sprite plot and VDU 5 text avoids reading the screen if possible
        * Framestore made USR mode accessible
        * Fix for VDU 5,127 bug - now relies on font definitions being in extreme
          quarters of memory, rather than bottom half
        * Allocated 64-bit OS_Convert... SWIs
        * IIC errors use allocated error numbers
        * Looks for Dallas RTC before Philips RTC because we're using a Philips
          NVRAM device with the same ID
        * Fix to bug that meant the oscillator in the Dallas RTC wasn't enabled
        * Default mouse type (USB) changed to allocated number
        * Ram disc max size increased to 128 Mbytes (Ursula merge) and made
          cacheable for StrongARMs (not XScale)
        * Branch through zero handler now works in USR mode, by use of a
          trampoline in the system stack to allow PC-relative register storage
        * Address exception handler changed to not use 0 as workspace
        * OS_Memory 13 extended to allow specification of cacheability and access
          privileges
        * Added OS_Memory 16 to return important memory addresses
        * RISCOS_MapInIO() takes cacheable flag in bit 3, access permissions in
          bits 10 and 11, doubly-mapped flag in bit 20, and access permissions
          specified flag in bit 21
        * Bug fix in last version for application abort handlers didn't quite
          work; register shuffle required
        * "Module is not 32-bit compatible" error now reports the module name
        * Default configured language changed from 10 to 11 (now Desktop again)
      
      Version 5.35, 4.79.2.51. Tagged as 'Kernel-5_35-4_79_2_51'
      9664c93b
  18. 28 Oct, 2002 1 commit
    • Ben Avison's avatar
      In the No26bitCode case (ie when abort handlers are entered in ABT32 mode), if... · 982426fe
      Ben Avison authored
      In the No26bitCode case (ie when abort handlers are entered in ABT32 mode), if lazy task swapping was enabled and a data abort occurred that was not a page translation fault, then the code in AMB_LazyFixUp to map in the whole application slot was being circumvented, leading to problems for abort handlers in application space because r14_abt was corrupted by any abort due to accessing the abort handler itself. The test of the FSR (to compensate for the FAR being unusable for external aborts) which prompted the circumvention has therefore been moved inside AMB_LazyFixup.
      
      Also now preserves the FSR and FAR across AMB_LazyFixUp, so they are now
      visible from application abort handlers if desired.
      
      Version 5.35, 4.79.2.50. Tagged as 'Kernel-5_35-4_79_2_50'
      982426fe
  19. 18 Jun, 2001 1 commit
    • Mike Stephens's avatar
      Reimplement enhancements to kernel Dynamic Area support from · 3f877936
      Mike Stephens authored
      Ursula. Quite a hairy code merge really, so let's hope it is
      worth it to someone. What you get (back after 2 or 3 years):
      - much more efficient for largish numbers of DAs (relevance
        to current build = approx 0)
      - fancy reason codes to support fast update of
        Switcher bar display (relevance = 0)
      - support for clamped maximum area sizes, to avoid address
        space exhaustion with big memory (relevance = 0)
      - better implementation of shrinkable DAs, performance
        wise (if lots of DAs, relevance = approx 0)
      - support for 'Sparse' DAs. Holey dynamic areas, Batman!
        (relevance, go on someone use the darned things)
      Moderately development tested on HAL/32bit ARM9 desktop.
      Note the Switcher should be compiled to use the new
      reason codes 6&7, for fabled desktop builds.
      
      Also, during this work, so I could see the wood for the
      trees, redid some source code clean up, removing pre-Medusa
      stuff (like I did about 3 years ago on Ursula, sigh). That's
      why loads of source files have changed. The new DA stuff
      is confined pretty much to hdr.KernelWS and s.ChangeDyn.
      
      Ta.
      
      Version 5.35, 4.79.2.38. Tagged as 'Kernel-5_35-4_79_2_38'
      3f877936
  20. 13 Jun, 2001 1 commit
    • Mike Stephens's avatar
      Changes to Lazy task swapping to support abort handler in abort mode (now that we can count to 32). · a0f4966c
      Mike Stephens authored
      LazyFixup now ensures all app pages are mapped in before handing
      on a real (no-lazy) abort. This allows an abort handler in app
      space itself, without scrambling the details of the original
      abort (via a lazy abort in abort mode).
      Many a happy minute spent coding and testing for recursive
      aborts and fixups, but lets just pretend it doesn't happen
      shall we.
      Tested with simple popbang code on ARM9 desktop build.
      
      Version 5.35, 4.79.2.36. Tagged as 'Kernel-5_35-4_79_2_36'
      a0f4966c
  21. 06 Jun, 2001 1 commit
    • Mike Stephens's avatar
      Further work on Lazy task swapping: · ae287104
      Mike Stephens authored
        hooks to give correct mapping info for OS_Memory 0
        same for OS_ReadMemMapEntries
        same for OS_FindMemMapEntries
        Lazy fixup routine no longer assumes an abort in current
        app space must be a truant page. However, work in this
        area not complete (no support yet for abort handler code
        in app space itself, eg. for C trampoline)
      Good to know this will be a big performance boost when
      our products use one monolithic application (sarcasm).
      Ta
      
      Version 5.35, 4.79.2.32. Tagged as 'Kernel-5_35-4_79_2_32'
      ae287104
  22. 22 May, 2001 1 commit
    • Mike Stephens's avatar
      Reimplement Lazy task swapping, an amusing idea from Ursula, would have done... · bdc4f843
      Mike Stephens authored
      Reimplement Lazy task swapping, an amusing idea from Ursula, would have done it sooner but couldn't be bothered (humour).
      
      Currently activates for all ARMs flagged as base-restored
      abort model. No handling of eg. StrongARM pre-revT bug, but
      then the kernel no longer runs on StrongARM (progress).
      Still some details to fix: all aborts in current app space
      assumed to be missing pages, but this must be fixed to
      handle abort code in app space, things like debuggers
      marking code read only.
      
      Plus, small fixes:
        OS_Memory 8 returns vaguely useful info for RAM,VRAM
        in HAL build (temporary partial implementation)
        Broken handling of old BBC commands with (fx,tv etc)
        with no spaces fixed (fudgeulike code from Ursula,
        now 32-bit).
      
      Version 5.35, 4.79.2.31. Tagged as 'Kernel-5_35-4_79_2_31'
      bdc4f843
  23. 23 Jan, 2001 1 commit
  24. 10 Nov, 2000 1 commit
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  26. 16 Oct, 2000 1 commit
  27. 07 May, 1997 1 commit
  28. 01 May, 1997 1 commit
  29. 06 Nov, 1996 1 commit