Update Cortex kernel to use correct instruction/memory barriers and to perform...
Update Cortex kernel to use correct instruction/memory barriers and to perform branch target predictor maintenance. Plus tweak default CMOS settings. Detail: hdr/Copro15ops - Added myISB, myDSB, myDMB macros to provide barrier functionality on ARMv6+ s/ARMops, s/HAL, s/VMSAv6, s/AMBControl/memmap - Correct barrier operations are now performed on ARMv6+ following CP15 writes. Branch predictors are now also maintained properly. s/NewReset - Change default CMOS settings so number of CDFS drives is 0 in Cortex builds. Fixes rogue CDFS icon on iconbar. Admin: Tested on rev C2 beagleboard Version 5.35, 22.214.171.124.2.27. Tagged as 'Kernel-5_35-4_79_2_98_2_27'
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