Commit dd9c5400 authored by Jeffrey Lee's avatar Jeffrey Lee
Browse files

Fix ProcessTransfer bug with LDM

Detail:
  s/ARM600, s/VMSAv6 - When processing an LDM which wasn't the "user mode registers" form, the initialisation of lr was being skipped, resulting in the registers being loaded from garbage addresses. Shuffle things around slightly so that the branch to label 34 works as intended.
Admin:
  Issue spotted by Willi Theiss
  Builds, but untested


Version 5.35, 4.79.2.211. Tagged as 'Kernel-5_35-4_79_2_211'
parent 7fbbad3d
......@@ -13,11 +13,11 @@
GBLS Module_ComponentPath
Module_MajorVersion SETS "5.35"
Module_Version SETA 535
Module_MinorVersion SETS "4.79.2.210"
Module_Date SETS "09 Mar 2014"
Module_ApplicationDate SETS "09-Mar-14"
Module_MinorVersion SETS "4.79.2.211"
Module_Date SETS "23 Mar 2014"
Module_ApplicationDate SETS "23-Mar-14"
Module_ComponentName SETS "Kernel"
Module_ComponentPath SETS "castle/RiscOS/Sources/Kernel"
Module_FullVersion SETS "5.35 (4.79.2.210)"
Module_HelpVersion SETS "5.35 (09 Mar 2014) 4.79.2.210"
Module_FullVersion SETS "5.35 (4.79.2.211)"
Module_HelpVersion SETS "5.35 (23 Mar 2014) 4.79.2.211"
END
......@@ -5,19 +5,19 @@
*
*/
#define Module_MajorVersion_CMHG 5.35
#define Module_MinorVersion_CMHG 4.79.2.210
#define Module_Date_CMHG 09 Mar 2014
#define Module_MinorVersion_CMHG 4.79.2.211
#define Module_Date_CMHG 23 Mar 2014
#define Module_MajorVersion "5.35"
#define Module_Version 535
#define Module_MinorVersion "4.79.2.210"
#define Module_Date "09 Mar 2014"
#define Module_MinorVersion "4.79.2.211"
#define Module_Date "23 Mar 2014"
#define Module_ApplicationDate "09-Mar-14"
#define Module_ApplicationDate "23-Mar-14"
#define Module_ComponentName "Kernel"
#define Module_ComponentPath "castle/RiscOS/Sources/Kernel"
#define Module_FullVersion "5.35 (4.79.2.210)"
#define Module_HelpVersion "5.35 (09 Mar 2014) 4.79.2.210"
#define Module_FullVersion "5.35 (4.79.2.211)"
#define Module_HelpVersion "5.35 (23 Mar 2014) 4.79.2.211"
#define Module_LibraryVersionInfo "5:35"
......@@ -838,8 +838,9 @@ DAbPreVeneer ROUT
LDRNE lr, =&6000 ; else put r13,r14 in user bank
AND r0, r4, lr ; r0 = mask of registers to put into user bank
BIC r4, r4, lr ; r4 = mask of registers to put into main bank
MOV lr, #0
34
MOV lr, #0
35
MOVS r4, r4, LSR #1 ; shift bit into carry
LDRCS r2, [r5], #4 ; if set bit then transfer word from stack frame
STRCS r2, [r11, lr, LSL #2] ; into main register bank
......@@ -848,7 +849,7 @@ DAbPreVeneer ROUT
STRCS r2, [r3, lr, LSL #2] ; into user register bank
ADD lr, lr, #1
ORRS r6, r0, r4 ; have we finished both banks?
BNE %BT34 ; no, then loop
BNE %BT35 ; no, then loop
; If LDM with PC in list, then add 4 to it, so the exit procedure is the same as if PC not loaded
; Also, if it was an LDM with PC and ^, then we have to update the stacked SPSR
......
......@@ -687,8 +687,9 @@ DAbPreVeneer ROUT
LDRNE lr, =&6000 ; else put r13,r14 in user bank
AND r0, r4, lr ; r0 = mask of registers to put into user bank
BIC r4, r4, lr ; r4 = mask of registers to put into main bank
MOV lr, #0
34
MOV lr, #0
35
MOVS r4, r4, LSR #1 ; shift bit into carry
LDRCS r2, [r5], #4 ; if set bit then transfer word from stack frame
STRCS r2, [r11, lr, LSL #2] ; into main register bank
......@@ -697,7 +698,7 @@ DAbPreVeneer ROUT
STRCS r2, [r3, lr, LSL #2] ; into user register bank
ADD lr, lr, #1
ORRS r6, r0, r4 ; have we finished both banks?
BNE %BT34 ; no, then loop
BNE %BT35 ; no, then loop
; If LDM with PC in list, then add 4 to it, so the exit procedure is the same as if PC not loaded
; Also, if it was an LDM with PC and ^, then we have to update the stacked SPSR
......
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