Commit ad796332 authored by Mike Stephens's avatar Mike Stephens
Browse files

1) Fixes and tidy ups:

   - mapping of Cur/Sys/Sound area done more elegantly, and soft CAM info
     is now consistent with it
   - cached screen cleaning on VSync performed *after* VSync events
   - comments at top of ARM600 modernised
   - Pages_Unsafe/Safe code fixed to work properly on StrongARM with
     pages that are involved in interrupts (there is no fix for ARM8,
     since that is unlikely to be needed - an ASSERT checks use of ARM8
   - OS_DynamicArea code souped up, to be much more efficient for large
     numbers of dynamic areas (see comments near top of ChangeDyn)
   - cached screen is now suspended on h/w scroll (avoids possible cache
     incoherency)
2) API changes:
   - new OS_Memory reason code (10) allows Wimp to inform kernel of
     Wimp_ClaimFreeMemory, and can control VRAM rescue (see below)
   - new OS_ReadSysInfo reason code (6) allows reading of kernel values
     (reserved for Acorn use, eg. for SoftLoad, ROMPatch)
   - new OS_DynamicArea reason codes (6 and 7) allow for more efficient
     monitoring of dynamic areas by TaskManager (reserved for Acorn use)
3) Changes for Phoebe:
   - kernel runs a VRAM rescue process, which ensures that any VRAM not
     used for the screen is reclaimed if necessary and sinks to the bottom
     of the Free Pool. This is important for Phoebe, where VRAM is slower
     than SDRAM, but does no harm on other platforms.
   - logical copy of physical RAM is removed from memory map. This frees
     up 256M of address space that will later be used for PCI on Phoebe,
     but should do no harm on other platforms (this space is marked
     private in PRMs, so 3rd parties should not use it).
parent 112a81d2
......@@ -13,7 +13,7 @@ OSVersionID SETA &A6
|
Version SETA 380
VString SETS "3.80"
Date SETS "05 Sep 1997" ; version for RISC OS on desktop computers
Date SETS "16 Oct 1997" ; version for RISC OS on desktop computers
OSVersionID SETA &A8 ; was &A7 for 3.70,3.71
]
......
......@@ -953,7 +953,7 @@ Export_ResetType # 1 ; &174 ; bit 0 => 1 = por, 0 = not por ;
ASSERT ?Export_ResetType = ?ResetType
AlignSpace 4
AMBControl_ws # 4 ; workspace anchor word for AMBControl
AMBControl_ws # 4 ; workspace anchor word for AMBControl
;
; next two words are for StrongARM data cache cleaning control - they should *never* be poked directly by non-kernel code
;
......@@ -964,25 +964,56 @@ ARMA_Cleaner_status # 4 ; status for cleans - Allows vsync screen c
; status. SC's and common NSC's should, with interrupts disabled.
; bit fields of ARMA_Cleaner_status (ACS_...) defined as follows:
;
ACS_SCdisable * &80000000 ; bit 31 SC disable flag - VSC and foreground SC disabled at all times if set (must be set if not StrongARM)
ACS_SCsuspend * &40000000 ; bit 30 SC suspend flag - VSC and foreground SC suspended if set
ACS_NSCsemaphore * &20000000 ; bit 29 NSC semaphore - NSC in progress if set
ACS_SCsemaphore * &10000000 ; bit 28 SC semaphore - SC in progress if set (may be VSC or foreground SC)
ACS_VSClazy_MASK * &0C000000 ; bits 26..27 VSC lazy - vsyncs before each triggered VSC will be executed (1..3, 0 is undefined)
ACS_VSClazy_SHIFT * 26
ACS_VSClazy_DEFAULT * 2:SHL:26
ACS_VSCcountdown_MASK * &03000000 ; bits 24..25 VSC countdown - vsyncs before next VSC will execute (0..3, 0=none pending, 1=at next vsync)
ACS_VSCcountdown_SHIFT * 24
ACS_SCflipflop * &00800000 ; bit 23 SC flipflip - controls flipflop between two 16k cleaner areas for SC's
ACS_SCflipflop_SHIFT * 23
ACS_SynchCAsemaphore * &00400000 ; bit 22 SychCA semaphore - set during SynchroniseCodeAreas (re-entrancy guard)
ACS_Scacheflag * &00200000 ; bit 21 Scache flag - set if screen currently cacheable (mainly for info to OS_ScreenMode)
ACS_SCdisable * &80000000 ; bit 31 SC disable flag - VSC and foreground SC disabled at all times if set (must be set if not StrongARM)
ACS_SCsuspend * &40000000 ; bit 30 SC suspend flag - VSC and foreground SC suspended if set
ACS_NSCsemaphore * &20000000 ; bit 29 NSC semaphore - NSC in progress if set
ACS_SCsemaphore * &10000000 ; bit 28 SC semaphore - SC in progress if set (may be VSC or foreground SC)
ACS_VSClazy_MASK * &0C000000 ; bits 26..27 VSC lazy - vsyncs before each triggered VSC will be executed (1..3, 0 is undefined)
ACS_VSClazy_SHIFT * 26
ACS_VSClazy_DEFAULT * 2:SHL:26
ACS_VSCcountdown_MASK * &03000000 ; bits 24..25 VSC countdown - vsyncs before next VSC will execute (0..3, 0=none pending, 1=at next vsync)
ACS_VSCcountdown_SHIFT * 24
ACS_SCflipflop * &00800000 ; bit 23 SC flipflop - controls flipflop between two 16k cleaner areas for SC's
ACS_SCflipflop_SHIFT * 23
ACS_SynchCAsemaphore * &00400000 ; bit 22 SychCA semaphore - set during SynchroniseCodeAreas (re-entrancy guard)
ACS_Scacheflag * &00200000 ; bit 21 Scache flag - set if screen currently cacheable (mainly for info to OS_ScreenMode)
; bit 0..20 reserved - 0
! 0, "AMBControl_ws at ":CC::STR:(AMBControl_ws)
! 0, "ARMA_Cleaner_flipflop at ":CC::STR:(ARMA_Cleaner_flipflop)
! 0, "ARMA_Cleaner_status at ":CC::STR:(ARMA_Cleaner_status)
; word controlling rescue of VRAM that is not used by screen (and sorting into bottom of free pool) - VRAM is slower than SDRAM for Phoebe.
; word organised as 3 fields - control field (byte) is not written by interrupt routine, so can be safely manipulated by foreground with IRQs enabled
VRAMRescue_control # 1 ; control bits manipulated by foreground, read by interrupt driven rescuer
VRAMRescue_status # 1 ; status bits manipulated by interrupt driven rescuer
VRAMRescue_nextVpage # 2 ; page number of next VRAM page to check for rescue (VRAM pages run from 0 on Phoebe or Risc PC)
; Bit fields of VRAMRescue_control (VRRc_...) defined as follows:
;
VRRc_disable * &01 ; control bit 0 slow page rescue from Free Pool disabled completely, if set (disabled for no VRAM)
VRRc_suspend * &02 ; control bit 1 slow page rescue suspended by outside agent, if set
VRRc_wimp_lock * &04 ; control bit 2 slow page rescue suspended because Wimp_ClaimFreeMemory has claimed free pool, if set
; control bits 3..7 reserved (should be 0)
; Bit fields of VRAMRescue_status (VRRs_...) defined as follows:
VRRs_CBpending * &01 ; status bit 0 rescuer has CallBack pending
; status bits 1..7 reserved (should be 0)
! 0, "VRAMRescue word at ":CC::STR:(VRAMRescue_control)
DynArea_ws # 4 ; workspace anchor word for data structures to accelerate OS SWIs for dynamic areas
; (OSs up to 3.71 are horrendously slow when no. of dynamic reas is large)
! 0, "DynArea_ws at ":CC::STR:(DynArea_ws)
[ mjsServiceTrace
mjsServiceTrace_ws # 4
! 0, ""
! 0, "**WARNING** compiling in code to trace service call statistics (mjsServiceTrace TRUE)"
! 0, ""
! 0, "mjsServiceTrace_ws at ":CC::STR:(mjsServiceTrace_ws)
]
[ StorkPowerSave
;;; AlignSpace 4
;;;VIDCExternalSoftCopy # 4 ; soft copy of VIDCExternal
......
......@@ -44,7 +44,7 @@ AMBMIRegWords * (AbsMaxAppPages+31) :SHR: 5 ;no. of words for AMBMapped
;(only 896 bytes for 28Mb AppSpace)
]
;maximum logical space size cleaned by range strategy
;StrongARM - maximum logical space size cleaned by range strategy
;
;Cleaning a sufficiently small space by range will be quicker, because of the fixed
;memory reading cost for a full DC clean. A sufficiently large space will be better handled
......@@ -62,7 +62,8 @@ AMB_ARMA_CleanSparseRange_thresh * 256*1024 ;must be whole no. pages
ValidateAMBHandles SETL {FALSE}
;performance enhancements introduced for Ursula OS
;performance enhancements introduced for Ursula OS (AMB_LazyMapIn is for StrongARM only - others
;should work on any ARM)
;
; ChocolateAMB - if {FALSE}, disables all AMBControl crazy chocolate flavour enhancements
; (defined in kernel GetAll, since other parts of kernel need hooks if true)
......@@ -72,30 +73,22 @@ ValidateAMBHandles SETL {FALSE}
; cost much lower and much less sensitive to large slot size. The worst case
; swapping cost is still good (abort mechanism cost is very small).
;
; AMB_StickyLastNode - if {TRUE}, the last deallocated node (the node itself, not the AppSpace
; pages) is retained, with page list. If the next allocate occurs
; without any intervening FreePool mangling, the page list is reused to save
; work. This is handy especially because the FreePool L2PT area is uncached.
;
; AMB_LimpidFreePool - if {TRUE}, the cache(s) can be assumed to be clear with respect to the FreePool
; when AMBControl fetches pages from it. This allows AMBControl to avoid any
; cache clean/flush for moving pages out of the FreePool. This assumption is
; valid if either: FreePool pages are uncacheable; or FreePool pages are
; never used in situ; or FreePool pages are flushed after use in situ (eg. by
; Wimp_ClaimFreeMemory).
; never used in situ; or FreePool pages are flushed after use in situ.
;
; AMB_ChocTrace - if {TRUE}, keep trace info for some enhanced code calls and data (probably development only)
GBLL AMB_LazyMapIn
GBLL AMB_StickyLastNode
GBLL AMB_LimpidFreePool
GBLL AMB_ChocTrace
AMB_LazyMapIn SETL {TRUE} :LAND: ChocolateAMB
AMB_StickyLastNode SETL {FALSE} :LAND: ChocolateAMB ;NOT implemented yet
AMB_ChocTrace SETL {FALSE} :LAND: ChocolateAMB ;development only
AMB_LimpidFreePool SETL {TRUE} :LAND: ChocolateAMB ;allowed because FreePool is currently marked uncacheable
;current implementation assumes uncacheability as criterion
AMB_ChocTrace SETL {FALSE} :LAND: ChocolateAMB ;development only
END
......@@ -65,8 +65,8 @@ AMBmaxwork * :INDEX:@ ;size of main workspace (assumed to be mu
;
;definition of bits in AMBFlags
;
AMBFlag_LazyMapIn_disable * &80000000 ;bit 31 permanent disable (eg. not running on StrongARM)
AMBFlag_LazyMapIn_suspend * &40000000 ;bit 30 suspend (controlled via AMB SWI)
AMBFlag_LazyMapIn_disable * &80000000 ;bit 31 LazyMapIn permanent disable (eg. not running on StrongARM)
AMBFlag_LazyMapIn_suspend * &40000000 ;bit 30 LazyMapIn suspend (controlled via AMB SWI)
;bits 29..0 reserved (0)
;
]
......
......@@ -439,8 +439,8 @@ AMB_SetMemMapEntries ROUT
[ AMB_LimpidFreePool
;can avoid cache clean/flush for moving pages out from FreePool, since FreePool pages are uncacheable
;
TST r3, #&20 ;test NotCacheable bit of PPL of 1st page
BEQ AMB_smme_mapnotlimpid ;if clear, must do full map somewhere with cache clean/flush
TST r3, #DynAreaFlags_NotCacheable ;test PPL of 1st page for not cacheable bit set
BEQ AMB_smme_mapnotlimpid ;if clear, must do full map somewhere with cache clean/flush
;
;this should be map FreePool -> App Space then
;
......@@ -448,7 +448,7 @@ AMB_SetMemMapEntries ROUT
BL AMB_movepagesout_L2PT
BL AMB_movepagesin_L2PT
BL AMB_movepagesin_CAM
ARM_flush_TLB r0 ;no cache clean/flush, just TLB flush
ARM_flush_TLB r0 ;no cache clean/flush, just TLB flush
Pull "r0-r4,r7-r11, pc"
AMB_smme_mapnotlimpid
]
......
This diff is collapsed.
......@@ -613,6 +613,25 @@ Issue_Service ROUT ; R1 is service number, R2 may be a parameter
; registers preserved.
Push "R9-R12, lr"
[ mjsServiceTrace
Push "r0-r3"
MOV r0,#0
LDR r2,[r0,#mjsServiceTrace_ws]
CMP r2,#0
BNE mjsst_1
MOV r3,#256*4
BL ClaimSysHeapNode
MOV r0,#0
STR r2,[r0,#mjsServiceTrace_ws]
mjsst_1
CMP r1,#255
MOVHI r1,#255
LDR r0,[r2,r1,LSL #2]
ADD r0,r0,#1
STR r0,[r2,r1,LSL #2]
Pull "r0-r3"
]
;do the direct calls to AMBControl for service calls of interest
CMP R1, #Service_MemoryMoved
BLEQ AMBsrv_memorymoved
......
This diff is collapsed.
......@@ -95,12 +95,8 @@ DoingVdu SETL {FALSE} ; so can get KeyWS!
Module SETL {FALSE}
GBLL IncludeTestSrc ; whether test code is included
! 0, "Modified code"
[ MorrisSupport
IncludeTestSrc SETL {FALSE}
|
IncludeTestSrc SETL :LNOT: (MEMM_Type = "MEMC2") ; not on internal test versions
]
[ RunningOnEmul
IncludeTestSrc SETL {FALSE} :LAND: :LNOT: STB
......@@ -156,6 +152,10 @@ ShrinkableDAs SETL {TRUE}
;(broken up to revision 3 SA110 at least)
GBLL StrongARM_POST ;whether to run POST for StrongARM (and possibly ARM8)
GBLL RescueVRAM ;whether to run process that rescues VRAM pages that are not in use for the screen
;and sorts them into the bottom of the free pool - implements use of VRAM as a last resort
;(maybe useful on Risc PC, important on Phoebe where VRAM is slower than SDRAM)
GBLL ChocolateScreen ;whether to implement crazy chocolate flavour screen (section mapped and cacheable) on SA
GBLL ChocolateAMB ;whether to implement crazy chocolate flavour AMBControl (lazy task swapping) on SA
;if LDMIBbroken is TRUE, ChocolateAMB is not forced FALSE, but the kernel does suspend
......@@ -174,6 +174,8 @@ SASTMhatbroken SETL {TRUE} :LAND: StrongARM
SALDMIBbroken SETL {TRUE} :LAND: StrongARM
StrongARM_POST SETL {TRUE} :LAND: StrongARM
RescueVRAM SETL {TRUE}
ChocolateScreen SETL {TRUE} :LAND: StrongARM
ChocolateAMB SETL {TRUE} :LAND: StrongARM
......@@ -187,6 +189,10 @@ ARM810_POST SETL {FALSE} :LAND: ARM810support
VCOstartfix SETL {TRUE}
GBLL mjsServiceTrace ;for statistics gathering on service calls only
mjsServiceTrace SETL {FALSE}
[ StrongARM
! 0," ______________________________________________________"
! 0,"| |"
......
......@@ -163,16 +163,17 @@ ROM * &3800000
OSMD * &11111111
[ MEMC_Type = "IOMD"
VideoPhysRam * &02000000 ; Amazing - it's in the same place!
DRAM0PhysRam * &10000000 ; 4 DRAM banks
DRAM1PhysRam * &14000000
DRAM2PhysRam * &18000000
DRAM3PhysRam * &1C000000
DRAMBaseAddressMask * &1C000000 ; used to mask off bits after stealing video RAM
PhysSpaceSize * &20000000 ; IOMD physical map is 512M big
PhysROM * &00000000 ; and real ROM starts at 0
VideoPhysRam * &02000000 ; Amazing - it's in the same place!
DRAM0PhysRam * &10000000 ; 4 DRAM banks
DRAM1PhysRam * &14000000
DRAM2PhysRam * &18000000
DRAM3PhysRam * &1C000000
DRAMBaseAddressMask * &1C000000 ; used to mask off bits after stealing video RAM
PhysSpaceSize_Full * &20000000 ; IOMD physical map is 512M (starting at 0)
PhysSpaceSize_NoDRAM * &10000000 ; physical map excluding DRAM (starting at 0)
PhysROM * &00000000 ; and real ROM starts at 0
[ STB
PhysExtROM * &01000000 ; 2nd ROM bank starts at 16M
PhysExtROM * &01000000 ; 2nd ROM bank starts at 16M
]
SAMLength * 512*4 ; SAM length in bytes for 1 bank of VRAM
EASISpacePhys * &08000000
......
......@@ -58,6 +58,7 @@ MemReturn
B MemoryReadPhys
B MemoryAmounts
B MemoryIOSpace
B MemoryFreePoolLock
40
......@@ -346,7 +347,7 @@ NotAvailable * &88888888
; Returns information about the memory arrangement table.
;
MemoryPhysSize
MOV r1, #PhysSpaceSize :SHR: ByteShift
MOV r1, #PhysSpaceSize_Full :SHR: ByteShift
MOV r2, #4*1024
MOV pc, lr
......@@ -603,4 +604,42 @@ easi_space_table
DCD PhysSpace + IOMD_EASI_Base7
]
;----------------------------------------------------------------------------------------
; MemoryFreePoolLock
;
; In: r0 bits 0..7 = 10 (reason code 10)
; r0 bit 8 = 1 if call is by Wimp (reserved for Acorn use), 0 otherwise
; r0 bits 9..31 reserved (must be 0)
; r1 = 0 to resume any background actions that may manipulate FreePool mapping
; (currently, this is just VRAMRescue)
; = 1 to suspend any background actions that may manipulate FreePool mapping
; all other values reserved (undefined behaviour)
;
; Out: r1 = previous state (1=suspended, 0=not suspended)
;
; A suspend call from the Wimp will be taken to mean that the whole FreePool is locked, and
; memory cannot be moved (supports Wimp_ClaimFreeMemory)
;
MemoryFreePoolLock ROUT
Push "r2,r3,lr"
MOV r3,#0
LDRB lr,[r3,#VRAMRescue_control]
TEQ r1,#0
BNE %FT10
;flush TLB(s) for resume - needed for Wimp resume, precaution for other - no cache flush
;since Free Pool is uncached
ARM_flush_TLB r2
10
TST r0,#&100 ;is it Wimp?
MOVEQ r2,#VRRc_suspend
MOVNE r2,#VRRc_wimp_lock
TEQ r1,#0
AND r1,lr,r2 ;previous state
BICEQ lr,lr,r2
ORRNE lr,lr,r2
STRB lr,[r3,#VRAMRescue_control] ;set/clear relevant bit
TEQ r1,#0
MOVNE r1,#1
Pull "r2,r3,pc"
END
......@@ -957,8 +957,10 @@ ReadSysInfo_Code ROUT
CMP r0, #5
BCC %FT40 ; R0 = 4
BEQ %FT50 ; R0 = 5
CMP r0, #6
BEQ %FT60 ; R0 = 6
; R0 > 5, so illegal value
; R0 > 6, so illegal value
ADR r0, ErrorBlock_BadReadSysInfo
Push "lr"
......@@ -1244,6 +1246,49 @@ GetMachineAddressCMOS
LDR r0, [r0, #RawMachineID+0]
ExitSWIHandler
; OS_ReadSysInfo 6 - read kernel values (Acorn use only; eg. SoftLoad, ROMPatch)
;
; On entry: r0 = 6 (reason code)
; r1 -> input block - 1 word per entry, giving number of value required, terminated by -1
; r2 -> output block - 1 word per entry, will be filled in on output
;
; On exit: r0,r1,r2 preserved
; output block filled in - filled in value set to 0 if unrecognised/no longer meaningful value
;
; valid value numbers defined - see table below
;
60
Push "r0-r3"
ADR r3,osri6_table
62
LDR r0,[r1],#4
CMP r0,#-1
BEQ %FT64
CMP r0,#8
MOVHI r0,#0
LDRLS r0,[r3,r0,LSL #2]
STR r0,[r2],#4
B %BT62
64
Pull "r0-r3"
ExitSWIHandler
osri6_maxvalue * 8
osri6_table
DCD CamEntriesPointer ;0
DCD MaxCamEntry ;1
DCD PageFlags_Unavailable ;2
DCD PhysRamTable ;3
DCD ARMA_Cleaner_flipflop ;4
DCD TickNodeChain ;5
DCD ROMModuleChain ;6
DCD DAList ;7
DCD AppSpaceDANode ;8
LTORG
END
......@@ -1240,14 +1240,6 @@ VsyncIRQ ROUT
SUB R0, R0, #1
STRB R0, CFStime
[ ChocolateScreen
;screen cleaner stuff if enabled (should only be for StrongARM)
MOV R12,#0
LDR R0,[R12,#ARMA_Cleaner_status]
TST R0,#ACS_SCdisable:OR:ACS_SCsuspend
BLEQ VsyncSAScreenClean ; do the VSC jazz if not disabled or suspended
]
VDWS WsPtr ; Do our stuff before issuing VSYNC event
BL VsyncCall
BYTEWS WsPtr
......@@ -1255,6 +1247,17 @@ VsyncIRQ ROUT
MOV R0, #Event_VSync ; VSYNC event number
BL OSEVEN
[ ChocolateScreen
;
;after all vsync stuff (except flashing colours), screen cleaner stuff if enabled
;(will only be enabled for StrongARM)
;
MOV R2,#0
LDR R0,[R2,#ARMA_Cleaner_status]
TST R0,#ACS_SCdisable:OR:ACS_SCsuspend
BLEQ VsyncSAScreenClean ; do the VSC jazz if not disabled or suspended
]
LDRB R1, FlashCount
SUBS R1, R1, #1
Pull PC, CC ; was zero, so frozen
......@@ -1282,42 +1285,42 @@ dothesecondflash
Pull "R4, PC"
[ ChocolateScreen
;entry: R0 = current ARMA_Cleaner_status, R12=0, R0,R1 trashable
;entry: R0 = current ARMA_Cleaner_status, R2=0, R0,R1 trashable, ARM is StrongARM
;
VsyncSAScreenClean ROUT
TST R0,#ACS_VSCcountdown_MASK
MOVEQ PC,LR ;no pending VSC if VSC countdown is 0
SUB R0,R0,#1:SHL:ACS_VSCcountdown_SHIFT ;decrement VSC countdown
TST R0,#ACS_VSCcountdown_MASK
STRNE R0,[R12,#ARMA_Cleaner_status]
STRNE R0,[R2,#ARMA_Cleaner_status]
MOVNE PC,LR ;nothing to do yet if VSC countdown has not reached zero
TST R0,#ACS_NSCsemaphore:OR:ACS_SCsemaphore
ORRNE R0,R0,#1:SHL:ACS_VSCcountdown_SHIFT
STRNE R0,[R12,#ARMA_Cleaner_status]
STRNE R0,[R2,#ARMA_Cleaner_status]
MOVNE PC,LR ;if NSC or SC semaphore set, do nothing now but keep VSC countdown at 1
Push "R2-R4,LR"
EOR R0,R0,#ACS_SCflipflop ;next screen cleaner area
ORR R0,R0,#ACS_SCsemaphore
STR R0,[R12,#ARMA_Cleaner_status]
AND R14,R0,#ACS_SCflipflop ;extract SC flipflop bit
STR R0,[R2,#ARMA_Cleaner_status]
AND R0,R0,#ACS_SCflipflop ;extract SC flipflop bit
LDR R1,=ARMA_ScreenCleaners_address
ADD R1,R1,R14,LSR #ACS_SCflipflop_SHIFT-14 ;start address for clean (LSR -14 since 16k area size)
ADD R1,R1,R0,LSR #ACS_SCflipflop_SHIFT-14 ;start address for clean (LSR -14 since 16k area size)
ADD R2,R1,#16*1024 ;end address (exclusive, 16k cache size)
02
LDR R14,[R1],#32 ;read next cleaner line into data cache (triggers 8-word line fill)
LDR R14,[R1],#32
LDR R14,[R1],#32
LDR R14,[R1],#32
LDR R0,[R1],#32 ;read next cleaner line into data cache (triggers 8-word line fill)
LDR R0,[R1],#32
LDR R0,[R1],#32
LDR R0,[R1],#32
CMP R1,R2
BLO %BT02 ;until done
BLO %BT02 ;until done
;write buffer can be allowed to drain on its own (this is not a code- or remap- critical clean)
ARMA_read_MMUdomain r2
BIC r2,r2,#&C
ARMA_write_MMUdomain r2 ;reset screen (domain 1) to fault
LDR R0,[R12,#ARMA_Cleaner_status]
ARMA_read_MMUdomain R0
BIC R0,R0,#&C
ARMA_write_MMUdomain R0 ;reset screen (domain 1) to fault
MOV R2,#0
LDR R0,[R2,#ARMA_Cleaner_status]
BIC R0,R0,#ACS_SCsemaphore
STR R0,[R12,#ARMA_Cleaner_status]
Pull "R2-R4,PC"
STR R0,[R2,#ARMA_Cleaner_status]
MOV PC,LR
] ;ChocolateScreen
......
......@@ -583,6 +583,19 @@ afterpokingaround_notSA
]
]
[ RescueVRAM
MOV R1,#0
LDR R0,[R1,#VRAMSize]
CMP R0,#0
MOVEQ R0,#VRRc_disable
MOVNE R0,#VRRc_suspend ;suspend for now
STR R0,[R1,#VRAMRescue_control] ;word store sets all 3 fields (control,status,nextVpage)
|
MOV R1,#0
MOV R0,#VRRc_disable
STR R0,[R1,#VRAMRescue_control] ;word store sets all 3 fields (control,status,nextVpage)
]
; Initialise CAO ptr to none.
MOV R0, #0
......@@ -1075,9 +1088,22 @@ WallopDuffOnes
ADD R0, R0, R1
;this now assumes 4k pages (kernel now does not support pre-Medusa anyway)
Push "R0,R7"
MOV R7, #5*8
MOV R2, #CursorChunkAddress
LDR r1, =AP_CursorChunk
LDR r1, =AP_CursorChunk5
BL AddCamEntries
MOV R7, #3*8
ADD R0, R0, #5*8
LDR r1, =AP_CursorChunk3
BL AddCamEntries
Pull "R0,R7"
;used to be:
; MOV R2, #CursorChunkAddress
; LDR r1, =AP_CursorChunk
; BL AddCamEntries
CMP R12, #512*1024
SUBEQ R0, R0, R7 ; previous entries
......@@ -1378,6 +1404,7 @@ furtherpoke_notSA
BL L1L2PTenhancements ; little tricks on cacheability etc for performance
BL InitVariables
BL AMBControl_Init ; initialise AMBControl section
BL ModuleInit ; initialise modules
; scan podules, copy modules.
......@@ -1492,6 +1519,32 @@ SkipHardResetPart2 ; code executed on all types of reset
MOV R1, #Service_Reset
SWI XOS_ServiceCall
[ RescueVRAM
Push "r0-r8"
MOV r1,#0
LDRB r0,[r1,#VRAMRescue_control]
TST r0,#VRRc_disable
BNE vrescue_init_done
BIC r0,r0,#VRRc_suspend
STRB r0,[r1,#VRAMRescue_control] ;remove suspension
MOV r0,#0
MOV r1,#ChangeDyn_VRescue
MOV r2,#0
MOV r3,#-1
LDR r4,=AP_VRescue
MOV r5,#4096
ADRL r6,VRescue_DAhandler
MOV r7,#VRAMRescue_control
ADRL r8,VRescue_DAname
SWI XOS_DynamicArea ;create the DA area for rescueing VRAM pages in use
MOV r0,#10-1 ;call rescuer every 10 centiseconds
ADR r1,VRAM_rescuer
MOV r2,#VRAMRescue_control
SWI XOS_CallEvery
vrescue_init_done
Pull "r0-r8"
]
; now set up the default FIQ owner
MOV R1, #Service_ClaimFIQ
......@@ -1801,6 +1854,171 @@ IsKeyPressedAtReset ENTRY "r0-r2"
TEQEQ r2, #&FF
EXIT
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[ RescueVRAM
; called via CallEvery
; entry: r12 = address of VRAMRescue_control
;
VRAM_rescuer ROUT
Push "r0-r2,lr"
MOV r2,PC
ORR r1,r2, #SVC_mode
TEQP r1,#0 ;make sure SVC mode
NOP
LDRB r0,[r12]
TST r0,#VRRc_disable :OR: VRRc_suspend :OR: VRRc_wimp_lock
BNE %FT99
LDRB r0,[r12,#1] ;status byte
TST r0,#VRRs_CBpending
BNE %FT99
ORR r0,r0,#VRRs_CBpending
STRB r0,[r12,#1] ;set CBpending
ADR r0,VRAM_rescuer_callback
MOV r1,r12
SWI XOS_AddCallBack
99
TEQP r2,#0
NOP
Pull "r0-r2,PC"
; called via AddCallBack
; entry: r12 = address of VRAMRescue_control, svc mode, interrrupts enabled
;
VRAM_rescuer_callback ROUT
Push "r0-r8,lr"
MOV r8,PC
ORR r0,r8, #SVC_mode + I_bit ;interrupts off
TEQP r0,#0
NOP
LDRB r0,[r12,#1] ;status byte
BIC r0,r0,#VRRs_CBpending
STRB r0,[r12,#1] ;clear CBpending
LDRB r0,[r12]
TST r0,#VRRc_disable :OR: VRRc_suspend :OR: VRRc_wimp_lock
BNE %FT99
MOV r0,#0
LDR r0,[r0,#CDASemaphore] ;paranoia - make sure CDA not threaded
TEQ r0,#0
BNE %FT99
LDR r0,=FreePoolDANode