Commit 9e6b9350 authored by Jeffrey Lee's avatar Jeffrey Lee
Browse files

Fix more issues caused by aborting MVA cache/TLB ops on ARMv7

Detail:
  s/ARMops - Fixed an instance of 'invalidate branch predictor entry' that should have been 'invalidate all branch predictors'
  s/ChangeDyn - Avoid cleaning the Nowhere page when reallocating memory, to avoid incurring the performance hit of the abort handler, and to avoid AMBControl screwing things up by mapping in pages that we're trying to modify
  s/VMSAv6 - Move MVA cache/TLB abort handler to before ChocolateAMB code, to ensure AMBControl doesn't try mapping in pages for harmless cache/TLB op aborts. Also tweaked code to be a little bit faster.
Admin:
  Tested on rev C2 beagleboard. No more lockups when moving screen memory around, for now at least.


Version 5.35, 4.79.2.98.2.30. Tagged as 'Kernel-5_35-4_79_2_98_2_30'
parent 847a1275
......@@ -13,11 +13,11 @@
GBLS Module_ComponentPath
Module_MajorVersion SETS "5.35"
Module_Version SETA 535
Module_MinorVersion SETS "4.79.2.98.2.29"
Module_Date SETS "24 Jun 2010"
Module_ApplicationDate SETS "24-Jun-10"
Module_MinorVersion SETS "4.79.2.98.2.30"
Module_Date SETS "03 Jul 2010"
Module_ApplicationDate SETS "03-Jul-10"
Module_ComponentName SETS "Kernel"
Module_ComponentPath SETS "castle/RiscOS/Sources/Kernel"
Module_FullVersion SETS "5.35 (4.79.2.98.2.29)"
Module_HelpVersion SETS "5.35 (24 Jun 2010) 4.79.2.98.2.29"
Module_FullVersion SETS "5.35 (4.79.2.98.2.30)"
Module_HelpVersion SETS "5.35 (03 Jul 2010) 4.79.2.98.2.30"
END
......@@ -5,19 +5,19 @@
*
*/
#define Module_MajorVersion_CMHG 5.35
#define Module_MinorVersion_CMHG 4.79.2.98.2.29
#define Module_Date_CMHG 24 Jun 2010
#define Module_MinorVersion_CMHG 4.79.2.98.2.30
#define Module_Date_CMHG 03 Jul 2010
#define Module_MajorVersion "5.35"
#define Module_Version 535
#define Module_MinorVersion "4.79.2.98.2.29"
#define Module_Date "24 Jun 2010"
#define Module_MinorVersion "4.79.2.98.2.30"
#define Module_Date "03 Jul 2010"
#define Module_ApplicationDate "24-Jun-10"
#define Module_ApplicationDate "03-Jul-10"
#define Module_ComponentName "Kernel"
#define Module_ComponentPath "castle/RiscOS/Sources/Kernel"
#define Module_FullVersion "5.35 (4.79.2.98.2.29)"
#define Module_HelpVersion "5.35 (24 Jun 2010) 4.79.2.98.2.29"
#define Module_FullVersion "5.35 (4.79.2.98.2.30)"
#define Module_HelpVersion "5.35 (03 Jul 2010) 4.79.2.98.2.30"
#define Module_LibraryVersionInfo "5:35"
......@@ -2003,7 +2003,7 @@ MMU_ChangingUncachedEntry_WB_CR7_Lx
myISB ; Also required
TLB_InvalidateEntry_WB_CR7_Lx ROUT
MCR p15, 0, a1, c8, c7, 1 ; invalidate ITLB & DTLB entry
MCR p15, 0, a1, c7, c5, 7 ; invalidate branch predictor entry
MCR p15, 0, a1, c7, c5, 6 ; invalidate branch predictors
myDSB ; Wait for cache/branch invalidation to complete
myISB ; Ensure that the effects of the completed cache/branch invalidation are visible
MOV pc, lr
......
......@@ -3892,9 +3892,11 @@ DoTheGrowPagesSpecified
LDMIA lr, {r2, r3} ; get page number, logical address
Push "r0, r4"
LDR r4, =Nowhere ; There's no point in cleaning the nowhere page, and on some architectures it'll even trigger an abort handler due to the lack of mapping
MOV r0, r3
TEQ r3, r4
MOV r4, #0
ARMop MMU_ChangingEntry,,,r4
ARMop MMU_ChangingEntry,NE,,r4
Pull "r0, r4"
BL Call_CAM_Mapping ; move replacement page in
......
......@@ -510,6 +510,29 @@ DAbPreVeneer ROUT
STMIA r13_abort, {r0-r7} ; save unbanked registers anyway
STR lr_abort, [r13_abort, #15*4] ; save old PC, ie instruction address
; Fixup code for MVA-based cache/TLB ops, which can abort on ARMv7 if the specified MVA doesn't have a mapping.
; Must come before AMBControl, else things can go very wrong during OS_ChangeDynamicArea
; MVA cache ops have the form coproc=p15, CRn=c7, opc1=0, opc2=1
; MVA TLB ops have the form coproc=p15, CRn=c8, opc1=0, opc2=1
; Note that some non-MVA ops also follow the above rules - at the moment we make no attempt to filter those false-positives out
; This code is also written from the perspective of running on an ARMv7 CPU - behaviour under ARMv6 hasn't been checked!
MRS r0, SPSR
TST r0, #T32_bit
BNE %FT10 ; We don't cope with Thumb ATM. Should really check for Jazelle too!
LDR r0, [lr, #-8] ; Get aborting instruction
CMP r0, #&F0000000
BHS %FT10 ; Ignore cc=NV, which is MCR2 encoding
BIC r0, r0, #&F000000F ; Mask out the uninteresting bits
BIC r0, r0, #&0000F000
EOR r0, r0, #&0E000000 ; Desired value, minus CRn
EOR r0, r0, #&00000F30
CMP r0, #&00070000 ; CRn=c7?
CMPNE r0, #&00080000 ; CRn=c8?
BNE %FT10 ; It's not an MVA-based op
LDR r0, [r13_abort], #17*4
SUBS pc, lr_abort, #4 ; Resume execution at the next instruction
10
[ ChocolateAMB
ARM_read_FAR r0 ; aborting address
MOV r2, #0
......@@ -559,22 +582,7 @@ DAbPreVeneer ROUT
BNE %FT90
[ {TRUE}
; For now, the only fixup we do is for MVA-based cache/TLB ops, which can abort on ARMv7 if the specified MVA doesn't have a mapping.
; MVA cache ops have the form coproc=p15, CRn=c7, opc1=0, opc2=1
; MVA TLB ops have the form coproc=p15, CRn=c8, opc=0, opc2=1
; Note that some non-MVA ops also follow the above rules - at the moment we make no attempt to filter those false-positives out
; This code is also written from the perspective of running on an ARMv7 CPU - behaviour under ARMv6 hasn't been checked!
LDR r10, [r4, #-8] ; Get aborting instruction
CMP r10, #&F0000000
BHS %FT90 ; Ignore cc=NV, which is MCR2 encoding
LDR r9, =&0FFF0FF0 ; Mask of interesting bits
AND r10,r10,r9
LDR r9, =&0E000F30 ; Desired value, minus CRn
EOR r10,r10,r9
CMP r10, #&70000 ; CRn=c7?
CMPNE r10, #&80000 ; CRn=c8?
BEQ %FT70 ; It's an MVA-based op. Ignore the abort and resume execution
B %FT90 ; Else skip the old & broken LDR/STR fixup code and go straight to the exception handler,
B %FT90 ; Skip the old & broken LDR/STR fixup code and go straight to the exception handler
]
;ARM 810 or StrongARM allow signed byte load or half-word load/stores - not supported at present
......
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