diff --git a/VersionASM b/VersionASM index 7bdd6ad29ddd98feefa6195ae3c816dcf2708678..e76083c8463d96eefab676d16849a619d6b0b305 100644 --- a/VersionASM +++ b/VersionASM @@ -9,12 +9,12 @@ GBLS Module_ApplicationDate GBLS Module_HelpVersion GBLS Module_ComponentName -Module_MajorVersion SETS "6.60" -Module_Version SETA 660 +Module_MajorVersion SETS "6.61" +Module_Version SETA 661 Module_MinorVersion SETS "" -Module_Date SETS "01 Jun 2022" -Module_ApplicationDate SETS "01-Jun-22" +Module_Date SETS "05 Jan 2023" +Module_ApplicationDate SETS "05-Jan-23" Module_ComponentName SETS "Kernel" -Module_FullVersion SETS "6.60" -Module_HelpVersion SETS "6.60 (01 Jun 2022)" +Module_FullVersion SETS "6.61" +Module_HelpVersion SETS "6.61 (05 Jan 2023)" END diff --git a/VersionNum b/VersionNum index 69ef35dce63e73d3cf6b996d4ed2134ed96f78fc..52c32fb68aecda58515a9e2b5eca95f5ec876815 100644 --- a/VersionNum +++ b/VersionNum @@ -1,21 +1,21 @@ -/* (6.60) +/* (6.61) * * This file is automatically maintained by srccommit, do not edit manually. * */ -#define Module_MajorVersion_CMHG 6.60 +#define Module_MajorVersion_CMHG 6.61 #define Module_MinorVersion_CMHG -#define Module_Date_CMHG 01 Jun 2022 +#define Module_Date_CMHG 05 Jan 2023 -#define Module_MajorVersion "6.60" -#define Module_Version 660 +#define Module_MajorVersion "6.61" +#define Module_Version 661 #define Module_MinorVersion "" -#define Module_Date "01 Jun 2022" +#define Module_Date "05 Jan 2023" -#define Module_ApplicationDate "01-Jun-22" +#define Module_ApplicationDate "05-Jan-23" #define Module_ComponentName "Kernel" -#define Module_FullVersion "6.60" -#define Module_HelpVersion "6.60 (01 Jun 2022)" -#define Module_LibraryVersionInfo "6:60" +#define Module_FullVersion "6.61" +#define Module_HelpVersion "6.61 (05 Jan 2023)" +#define Module_LibraryVersionInfo "6:61" diff --git a/hdr/RISCOS b/hdr/RISCOS index effd77b3adb1cebaeb535d238a1a60c171e0386b..7fd9f61f246a7d776e17d12a9d70ec6470b6469d 100644 --- a/hdr/RISCOS +++ b/hdr/RISCOS @@ -153,7 +153,9 @@ SWIClass SETS RISCOS_Kernel_1SWI_Name AddSWI EnterUSR26 ; &74 first used in Ursula AddSWI VIDCDivider ; &75 AddSWI NVMemory ; &76 - ^ OS_NVMemory + 4 + ^ OS_NVMemory + 2 + AddSWI TaskControl ; &78 + ^ OS_TaskControl + 2 AddSWI Hardware ; &7A AddSWI IICOp ; &7B AddSWI LeaveOS ; &7C @@ -163,6 +165,9 @@ SWIClass SETS RISCOS_Kernel_1SWI_Name NCORESWIS * OS_HeapSort32 + 1 ; There are this many kernel SWIs, 0..NCORESWIS-1 + ; Steer clear of SWI &AB: + ; It is used for semi-hosting debug in Thumb mode in profile A/R before ARMv7VE + ASSERT @ <= &C0 SWIClass SETS RISCOS_StringConversionSWI_Name