Commit 89f30451 authored by Robert Sprowson's avatar Robert Sprowson
Browse files

Missing hash

One less warning in each of ARM600/VMSAv6.
parent dd9c5400
...@@ -900,7 +900,7 @@ DAbPreVeneer ROUT ...@@ -900,7 +900,7 @@ DAbPreVeneer ROUT
BEQ %FT90 ; Abort if LDRD (encoded where STRSB would be) BEQ %FT90 ; Abort if LDRD (encoded where STRSB would be)
TST r10, #1 :SHL: 22 ; if immediate TST r10, #1 :SHL: 22 ; if immediate
BICNE r9, r10, 2_1111 :SHL: 4 BICNE r9, r10, #2_1111 :SHL: 4
ORRNE r9, r9, r9, LSR #4 ORRNE r9, r9, r9, LSR #4
ANDNE r9, r9, #&FF ; then extract imm8 bits ANDNE r9, r9, #&FF ; then extract imm8 bits
ANDEQ r8, r10, #&0F ; register offset ANDEQ r8, r10, #&0F ; register offset
......
...@@ -749,7 +749,7 @@ DAbPreVeneer ROUT ...@@ -749,7 +749,7 @@ DAbPreVeneer ROUT
BEQ %FT90 ; Abort if LDRD (encoded where STRSB would be) BEQ %FT90 ; Abort if LDRD (encoded where STRSB would be)
TST r10, #1 :SHL: 22 ; if immediate TST r10, #1 :SHL: 22 ; if immediate
BICNE r9, r10, 2_1111 :SHL: 4 BICNE r9, r10, #2_1111 :SHL: 4
ORRNE r9, r9, r9, LSR #4 ORRNE r9, r9, r9, LSR #4
ANDNE r9, r9, #&FF ; then extract imm8 bits ANDNE r9, r9, #&FF ; then extract imm8 bits
ANDEQ r8, r10, #&0F ; register offset ANDEQ r8, r10, #&0F ; register offset
......
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