diff --git a/Docs/HAL/Entries b/Docs/HAL/Entries
index 59e134130ed9d97c8454d97812a632decd4a18e2..6b01b5b88f4e6c20e3721e5300654448cba57653 100644
--- a/Docs/HAL/Entries
+++ b/Docs/HAL/Entries
@@ -276,66 +276,6 @@ Usage:
-void *RISCOS_AccessPhysicalAddress(unsigned int flags, uint64_t phys, void **oldp)
-
- flags: bit 2 => make memory bufferable
- other bits must be zero
- phys: physical address to access
- oldp: pointer to location to store old state (or NULL)
-
-On entry:
- Privileged mode
- MMU on
- FIQs on
- Re-entrant
-
-On exit:
- Returns logical address corresponding to phys
-
-Usage:
- Arranges for the physical address phys to be mapped in to logical memory.
- In fact, at least the whole megabyte containing "phys" is mapped in (ie if phys =
- &12345678, then &12300000 to &123FFFFF become available). The memory is
- supervisor access only, non-cacheable, non-bufferable by default, and will
- remain available until the next call to RISCOS_Release/AccessPhysicalAddress
- (although interrupt routines or subroutines may temporarily map in something
- else).
-
- When finished, the user should call RISCOS_ReleasePhysicalAddress.
-
-
-
-
-void RISCOS_ReleasePhysicalAddress(void *old)
-
- old: state returned from a previous call to RISCOS_AccessPhysicalAddress
-
-On entry:
- MMU on
- FIQs on
- Re-entrant
-
-Usage:
- Call with the a value output from a previous RISCOS_ReleasePhysicalAddress.
-
-Example:
-
- void *old;
- uint64_t addr_physical = (uint64_t) 0x80005000;
- uint64_t addr2_physical = (uint64_t) 0x90005000;
- uint32_t *addr_logical;
- uint32_t *addr2_logical;
-
- addr_logical = (unsigned int *) RISCOS_AccessPhysicalAddress(0, addr_physical, &old);
- addr_logical[0] = 3; addr_logical[1] = 5;
-
- addr2_logical = (unsigned int *) RISCOS_AccessPhysicalAddress(0, addr2_physical, NULL);
- *addr2_logical = 7;
-
- RISCOS_ReleasePhysicalAddress(old);
-
-
-
HAL entries
diff --git a/Docs/HAL/HAL_API b/Docs/HAL/HAL_API
index 1ad41a24df2bb071a6c4edd422f10eb2ea44cbc0..f45c9b0822b3e8930ab98bdcb9de4c7083cd0dd2 100644
--- a/Docs/HAL/HAL_API
+++ b/Docs/HAL/HAL_API
@@ -1042,58 +1042,3 @@ if the virtual address space is exhausted.
-- void *RISCOS_MapInIO64(unsigned int flags, uint64_t phys, unsigned int size)
As for RISCOS_MapInIO, but accepting a 64-bit physical address argument.
-
-
--- void *RISCOS_AccessPhysicalAddress(unsigned int flags, uint64_t phys, void **oldp)
-
- flags: bit 2 => make memory bufferable
- other bits must be zero
- phys: physical address to access
- oldp: pointer to location to store old state (or NULL)
-
-On entry:
- Privileged mode
- MMU on
- FIQs on
- Re-entrant
-
-On exit:
- Returns logical address corresponding to phys
-
-Arranges for the physical address phys to be mapped in to logical memory. In
-fact, at least the whole megabyte containing "phys" is mapped in (ie if phys =
-&12345678, then &12300000 to &123FFFFF become available). The memory is
-supervisor access only, non-cacheable, non-bufferable by default, and will
-remain available until the next call to RISCOS_Release/AccessPhysicalAddress
-(although interrupt routines or subroutines may temporarily map in something
-else).
-
-When finished, the user should call RISCOS_ReleasePhysicalAddress.
-
--- void RISCOS_ReleasePhysicalAddress(void *old)
-
- old: state returned from a previous call to RISCOS_AccessPhysicalAddress
-
-On entry:
- MMU on
- FIQs on
- Re-entrant
-
-Usage:
- Call with the a value output from a previous RISCOS_ReleasePhysicalAddress.
-
-Example:
-
- void *old;
- uint64_t addr_physical = (uint64_t) 0x80005000;
- uint64_t addr2_physical = (uint64_t) 0x90005000;
- uint32_t *addr_logical;
- uint32_t *addr2_logical;
-
- addr_logical = (uint32_t *) RISCOS_AccessPhysicalAddress(0, addr_physical, &old);
- addr_logical[0] = 3; addr_logical[1] = 5;
-
- addr2_logical = (uint32_t *) RISCOS_AccessPhysicalAddress(0, addr2_physical, NULL);
- *addr2_logical = 7;
-
- RISCOS_ReleasePhysicalAddress(old);
diff --git a/VersionASM b/VersionASM
index 5f3ed41e26e1a3d0e3373493484b922ea8ac9398..b5c551e90b02435f65f838c0610823c9b26454b9 100644
--- a/VersionASM
+++ b/VersionASM
@@ -9,12 +9,12 @@
GBLS Module_ApplicationDate
GBLS Module_HelpVersion
GBLS Module_ComponentName
-Module_MajorVersion SETS "6.51"
-Module_Version SETA 651
+Module_MajorVersion SETS "6.52"
+Module_Version SETA 652
Module_MinorVersion SETS ""
-Module_Date SETS "10 Feb 2021"
-Module_ApplicationDate SETS "10-Feb-21"
+Module_Date SETS "13 Feb 2021"
+Module_ApplicationDate SETS "13-Feb-21"
Module_ComponentName SETS "Kernel"
-Module_FullVersion SETS "6.51"
-Module_HelpVersion SETS "6.51 (10 Feb 2021)"
+Module_FullVersion SETS "6.52"
+Module_HelpVersion SETS "6.52 (13 Feb 2021)"
END
diff --git a/VersionNum b/VersionNum
index 1e72e5a98a2b30d03770e102dae737e31031531c..93443cf1f32aa86d12640c459c71e23c406256b7 100644
--- a/VersionNum
+++ b/VersionNum
@@ -1,21 +1,21 @@
-/* (6.51)
+/* (6.52)
*
* This file is automatically maintained by srccommit, do not edit manually.
*
*/
-#define Module_MajorVersion_CMHG 6.51
+#define Module_MajorVersion_CMHG 6.52
#define Module_MinorVersion_CMHG
-#define Module_Date_CMHG 10 Feb 2021
+#define Module_Date_CMHG 13 Feb 2021
-#define Module_MajorVersion "6.51"
-#define Module_Version 651
+#define Module_MajorVersion "6.52"
+#define Module_Version 652
#define Module_MinorVersion ""
-#define Module_Date "10 Feb 2021"
+#define Module_Date "13 Feb 2021"
-#define Module_ApplicationDate "10-Feb-21"
+#define Module_ApplicationDate "13-Feb-21"
#define Module_ComponentName "Kernel"
-#define Module_FullVersion "6.51"
-#define Module_HelpVersion "6.51 (10 Feb 2021)"
-#define Module_LibraryVersionInfo "6:51"
+#define Module_FullVersion "6.52"
+#define Module_HelpVersion "6.52 (13 Feb 2021)"
+#define Module_LibraryVersionInfo "6:52"
diff --git a/s/ChangeDyn b/s/ChangeDyn
index 91944e821f7430f931dcfe1f87e4f1e23edbe666..67baf0997f4236189b917d4d6ddaaaf890005e15 100644
--- a/s/ChangeDyn
+++ b/s/ChangeDyn
@@ -5934,11 +5934,11 @@ DoTheGrowPagesSpecified ROUT
ReplacePage_DestUnmapped
Push "r1"
FastCDA_ProfStart AccessPhysical, r2, r1, lr
- MOV r0, #L1_B
+ LDR r0, =OSAP_None+DynAreaFlags_NotCacheable
LDR r1, [r8, #PageBlockSize+8] ; r1 = physical address of dest for copy
MOV r2, #0
ADD r3, sp, #4
- BL RISCOS_AccessPhysicalAddress
+ BL AccessPhysicalAddress
; r0 = logical address of dest for copy
FastCDA_ProfEnd AccessPhysical, r2, r1, lr
Pull "r1"
@@ -5954,11 +5954,11 @@ ReplacePage_BothUnmapped
; than the SVC stack
Push "r0,r1"
FastCDA_ProfStart AccessPhysical, r0, r1, lr
- MOV r0, #L1_B
+ LDR r0, =OSAP_None+DynAreaFlags_NotCacheable
LDR r1, [r8, #8] ; r1 = physical address of src for copy
MOV r2, #0
ADD r3, sp, #8
- BL RISCOS_AccessPhysicalAddress
+ BL AccessPhysicalAddress
MOV r6, r0 ; r6 = logical address of src for copy
FastCDA_ProfEnd AccessPhysical, r0, r1, lr
@@ -5977,11 +5977,11 @@ ReplacePage_BothUnmapped
FastCDA_ProfEnd CopyPage, r2, r3, r4
; Now map in dest
- MOV r0, #L1_B
+ LDR r0, =OSAP_None+DynAreaFlags_NotCacheable
LDR r1, [r8, #PageBlockSize+8] ; r1 = physical address of dest for copy
MOV r2, #0
MOV r3, #0 ; no oldp needed
- BL RISCOS_AccessPhysicalAddress
+ BL AccessPhysicalAddress
; r0 = logical address of dest for copy
MOV r6, sp
FastCDA_ProfStart CopyPage, r2, r3, r4
@@ -6003,11 +6003,11 @@ ReplacePage_BothUnmapped
ReplacePage_SrcUnmapped
Push "r0,r1"
FastCDA_ProfStart AccessPhysical, r0, r1, lr
- MOV r0, #L1_B
+ LDR r0, =OSAP_None+DynAreaFlags_NotCacheable
LDR r1, [r8, #8] ; r1 = physical address of src for copy
MOV r2, #0
ADD r3, sp, #8
- BL RISCOS_AccessPhysicalAddress
+ BL AccessPhysicalAddress
MOV r6, r0 ; r6 = logical address of src for copy
FastCDA_ProfEnd AccessPhysical, r0, r1, lr
Pull "r0,r1"
@@ -6032,7 +6032,7 @@ ReplacePage_Done
BEQ %FT80
FastCDA_ProfStart ReleasePhysical, r2, r3, r4
]
- BLNE RISCOS_ReleasePhysicalAddress
+ BLNE ReleasePhysicalAddress
[ FastCDA_Prof
FastCDA_ProfEnd ReleasePhysical, r2, r3, r4
80
diff --git a/s/HAL b/s/HAL
index 53564e2df9c5d878000a753b46206e00ff7ac99e..c1a608b3d83b618ff046891ba8ed2bba32abab7c 100644
--- a/s/HAL
+++ b/s/HAL
@@ -982,7 +982,7 @@ MMUon_nol1ptoverlap
ChangedProcVecs a1
MOV a1, #L1_Fault
- BL RISCOS_ReleasePhysicalAddress
+ BL ReleasePhysicalAddress
LDR a1, =HALWorkspace
LDR a2, =ZeroPage
@@ -1808,12 +1808,12 @@ AllocateL2PT ROUT
TEQ v3, #0 ; MMU on?
MOVNE a1, v4 ; if not, just access v4
- MOVEQ a1, #L1_B ; if so, map in v4
+ LDREQ a1, =OSAP_None+DynAreaFlags_NotCacheable ; if so, map in v4
MOVEQ a2, v4
SUBEQ sp, sp, #4
MOVEQ a3, #0
MOVEQ a4, sp
- BLEQ RISCOS_AccessPhysicalAddress
+ BLEQ AccessPhysicalAddress
MOV a2, #0
MOV a3, #4*1024
@@ -1821,7 +1821,7 @@ AllocateL2PT ROUT
TEQ v3, #0
LDREQ a1, [sp], #4
- BLEQ RISCOS_ReleasePhysicalAddress
+ BLEQ ReleasePhysicalAddress
; Get the correct page table entry flags for Init_MapInPage
TEQ v3, #0
@@ -1893,15 +1893,25 @@ $lab ANDS $tmp, $flags, #L1_SS
MEND
-; void *RISCOS_AccessPhysicalAddress(unsigned int flags, uint64_t addr, void **oldp)
-RISCOS_AccessPhysicalAddress ROUT
- ; Only flag user can ask for is bufferable
- ; Convert to appropriate DA flags
- ; (n.b. since this is an internal routine we should really change it to pass in DA flags directly)
- TST a1, #L1_B
- LDR a1, =OSAP_None + DynAreaFlags_NotCacheable ; SVC RW, USR none
- ORREQ a1, a1, #DynAreaFlags_NotBufferable
-RISCOS_AccessPhysicalAddressUnchecked ; well OK then, I trust you know what you're doing
+; void *AccessPhysicalAddress(unsigned int flags, uint64_t phys, void **oldp)
+;
+; APCS calling convention.
+;
+; flags: RISC OS page flags
+; phys: Physical address to access
+; oldp: Pointer to word to store old state (or NULL)
+;
+; On exit: Returns logical address corresponding to 'phys'.
+;
+; Arranges for the physical address 'phys' to be (temporarily) mapped into
+; logical memory. In fact, at least the whole megabyte containing 'phys' is
+; mapped in. All mappings use the same shared logical window; the current state
+; of the window will be returned in 'oldp', to allow it to be restored (via
+; ReleasePhysicalAddress) once you've finised with it.
+;
+; Note: No cache maintenance performed. Assumption is that mappings will be
+; non-cacheable.
+AccessPhysicalAddress ROUT
; Check physical address is valid on current CPU
LDR ip, =ZeroPage
Push "a1,v3,lr"
@@ -1948,8 +1958,13 @@ RISCOS_AccessPhysicalAddressUnchecked ; well OK then, I trust
MOV a1, #0
Pull "v3,pc"
-; void RISCOS_ReleasePhysicalAddress(void *old)
-RISCOS_ReleasePhysicalAddress
+; void ReleasePhysicalAddress(void *old)
+;
+; APCS calling convention.
+;
+; Call with the 'oldp' value from a previous AccessPhysicalAddress call to
+; restore previous physical access window state.
+ReleasePhysicalAddress
LDR ip, =L1PT + (PhysicalAccess:SHR:18) ; ip -> L1PT entry
MOV a4, #15
STR a1, [ip], #4 ; restore first of 16 L1PT entries
@@ -2151,7 +2166,7 @@ ClearFreePoolSection ROUT
MOV a2, r8
MOV a3, r9
MOV a4, #0
- BL RISCOS_AccessPhysicalAddressUnchecked
+ BL AccessPhysicalAddress
MOV r5, r8, LSR #20
ORR r5, r5, r9, LSL #12 ; r5 = physical MB
@@ -2227,11 +2242,11 @@ ClearFreePoolSection ROUT
; Make page uncacheable so the following is safe
MOV r4, r0
- MOV r0, #L1_B
+ LDR r0, =OSAP_None+DynAreaFlags_NotCacheable
MOV r1, r10, LSL #20
MOV r2, r10, LSR #12
MOV r3, #0
- BL RISCOS_AccessPhysicalAddress
+ BL AccessPhysicalAddress
MOV r0, r4
@@ -2256,7 +2271,7 @@ ClearFreePoolSection ROUT
]
91
MOV a1, #L1_Fault
- BL RISCOS_ReleasePhysicalAddress ; reset to default
+ BL ReleasePhysicalAddress ; reset to default
Pull "r0-r12"
diff --git a/s/MemInfo b/s/MemInfo
index ae9d343de8e075fa69854007132689f9608bf3de..cfad075d1c3049ef2b2ff9945dc8b54808e8c3f9 100644
--- a/s/MemInfo
+++ b/s/MemInfo
@@ -963,11 +963,11 @@ AccessPhysAddr ROUT
AccessPhysAddr64
Push "r0-r3,r12,lr"
10 TST r0, #&100 ;test bufferable bit
- MOVNE r0, #L1_B
- MOVEQ r0, #0
+ LDR r0, =OSAP_None+DynAreaFlags_NotCacheable
+ ORREQ r0, r0, #DynAreaFlags_NotBufferable
SUB sp, sp, #4 ; word for old state
MOV r3, sp ; pointer to word
- BL RISCOS_AccessPhysicalAddress
+ BL AccessPhysicalAddress
MOVS r2, r0 ; null pointer means invalid physical address
LDMIB sp, {r0,r1}
BEQ %FT90
@@ -989,7 +989,7 @@ AccessPhysAddr64
ReleasePhysAddr
Push "r0-r3,r12,lr"
MOV r0, r1
- BL RISCOS_ReleasePhysicalAddress
+ BL ReleasePhysicalAddress
Pull "r0-r3,r12,pc"
LTORG