diff --git a/VersionASM b/VersionASM
index e76083c8463d96eefab676d16849a619d6b0b305..dab40621bc141d4d53efb49ffe6d5e9994a3adb2 100644
--- a/VersionASM
+++ b/VersionASM
@@ -9,12 +9,12 @@
                         GBLS    Module_ApplicationDate
                         GBLS    Module_HelpVersion
                         GBLS    Module_ComponentName
-Module_MajorVersion     SETS    "6.61"
-Module_Version          SETA    661
+Module_MajorVersion     SETS    "6.62"
+Module_Version          SETA    662
 Module_MinorVersion     SETS    ""
-Module_Date             SETS    "05 Jan 2023"
-Module_ApplicationDate  SETS    "05-Jan-23"
+Module_Date             SETS    "14 Jan 2023"
+Module_ApplicationDate  SETS    "14-Jan-23"
 Module_ComponentName    SETS    "Kernel"
-Module_FullVersion      SETS    "6.61"
-Module_HelpVersion      SETS    "6.61 (05 Jan 2023)"
+Module_FullVersion      SETS    "6.62"
+Module_HelpVersion      SETS    "6.62 (14 Jan 2023)"
                         END
diff --git a/VersionNum b/VersionNum
index 52c32fb68aecda58515a9e2b5eca95f5ec876815..56e286fedbf1ab1d46714ce60e72ed55d7da3026 100644
--- a/VersionNum
+++ b/VersionNum
@@ -1,21 +1,21 @@
-/* (6.61)
+/* (6.62)
  *
  * This file is automatically maintained by srccommit, do not edit manually.
  *
  */
-#define Module_MajorVersion_CMHG        6.61
+#define Module_MajorVersion_CMHG        6.62
 #define Module_MinorVersion_CMHG
-#define Module_Date_CMHG                05 Jan 2023
+#define Module_Date_CMHG                14 Jan 2023
 
-#define Module_MajorVersion             "6.61"
-#define Module_Version                  661
+#define Module_MajorVersion             "6.62"
+#define Module_Version                  662
 #define Module_MinorVersion             ""
-#define Module_Date                     "05 Jan 2023"
+#define Module_Date                     "14 Jan 2023"
 
-#define Module_ApplicationDate          "05-Jan-23"
+#define Module_ApplicationDate          "14-Jan-23"
 
 #define Module_ComponentName            "Kernel"
 
-#define Module_FullVersion              "6.61"
-#define Module_HelpVersion              "6.61 (05 Jan 2023)"
-#define Module_LibraryVersionInfo       "6:61"
+#define Module_FullVersion              "6.62"
+#define Module_HelpVersion              "6.62 (14 Jan 2023)"
+#define Module_LibraryVersionInfo       "6:62"
diff --git a/s/Middle b/s/Middle
index 82b6c63e22309dac63531d70346d01e976b7c7e1..f3410d6a2f08b31399bc48902aafa914610f692f 100644
--- a/s/Middle
+++ b/s/Middle
@@ -675,13 +675,27 @@ UNDEF1
         MOV     R10, #SeriousErrorV
         BL      CallVector
 
+        ; Unwind & flatten all the stacks.
+        ; This does leave the register dump floating somewhere in the abort
+        ; stack, but with all interrupts turned off it should be safe enough,
+        ; especially as we copy it away immediately afterwards.
+        ADD     R10, R0, #8*4
+        BL      TaskControl_ResetStacks ; R0-R3 corrupt, R13 reset
+
         MSR     CPSR_c, #I32_bit+F32_bit+SVC32_mode ; into SVC mode
-        LDR     sp, =SVCSTK             ; Flatten superstack
+
+        ; Copy the register dump from its unsafe location on the abort stack,
+        ; to a temp location on the SVC stack
+        LDMIA   R10, {R0-R6, R8-R9}     ; R8-R15, PSR
+        Push    "R0-R6, R8-R9"
+        LDMDB   R10, {R0-R6, R8}        ; R0-R7
+        Push    "R0-R6, R8"
+
+        MSR     CPSR_c, #SVC32_mode+I32_bit ; Restore FIQs, we don't need them to be blocked now that the register dump is safe
 
         ; Check that ExceptionDump is safe to use
         Push    "R7"                    ; Preserve error ptr
         LDR     R5, =ZeroPage
-        MOV     R3, R0
         LDR     R1, [R5, #ExceptionDump]
         MOV     R0, #24
         ADD     R2, R1, #17*4
@@ -701,11 +715,11 @@ UNDEF1
 05
         Pull    "R14"                   ; Restore error ptr
 
-        ; Copy the dump from the stack to ExceptionDump
+        ; Now move the dump from the SVC stack to ExceptionDump
         LDR     R0, [R5, #ExceptionDump]
-        LDMIA   R3!, {R1-R2,R5-R10}     ; R0-R7
+        Pull    "R1-R2,R5-R10"          ; R0-R7
         STMIA   R0!, {R1-R2,R5-R10}
-        LDMIA   R3, {R1-R2,R5-R11}      ; R8-R15, PSR
+        Pull    "R1-R2,R5-R11"          ; R8-R15, PSR
         STMIA   R0, {R1-R2,R5-R11}
 
         SUB     R0, R0, #8*4
@@ -790,31 +804,6 @@ UNDEF1
         LDR     R0, =GeneralMOSBuffer+128
       ]
 
-        ; Flatten UND and ABT stacks, jic
-        ; Also a convenient way of getting rid of the temp exception dump
-        MRS     R2, CPSR
-        BIC     R2, R2, #F32_bit + &1F
-        ORR     R3, R2, #ABT32_mode
-        MSR     CPSR_c, R3                      ; FIQs back on
-        LDR     r13_abort, =ABTSTK
-        ORR     R3, R2, #UND32_mode
-        MSR     CPSR_c, R3
-        LDR     r13_undef, =UNDSTK
-        ORR     R3, R2, #IRQ32_mode
-        MSR     CPSR_c, R3
-        LDR     R1, =ZeroPage
-      [ ZeroPage = 0
-        STR     R1, [R1, #IRQsema]
-      |
-        MOV     R3, #0
-        STR     R3, [R1, #IRQsema]
-      ]
-        LDR     r13_irq, =IRQSTK
-
-        ; Trigger exception dump processing
-        ORR     R3, R2, #SVC32_mode
-        MSR     CPSR_c, R3
-
         ; Let everyone know that the stacks have been reset
         MOV     R2, #SeriousErrorV_Recover
         MOV     R10, #SeriousErrorV