Commit 63a6ffec authored by Mike Stephens's avatar Mike Stephens
Browse files

1) Bring IOMD HAL more up to date. Add support for new call HAL_CleanerSpace...

1) Bring IOMD HAL more up to date. Add support for new call HAL_CleanerSpace (preparation for StrongARM kernel support).

2) In kernel, add HAL_CleanerSpace call (preparation for
StrongARM and XScale core support). Fix bug found with
ARMv3 support during test on Risc PC.

3) Implement new API for kernel SWIs that have used top
bits of addresses as flags. The new API has an extra
flag that must be set, so kernel can distinguish and
support both APIs. The reason for all this is that
addresses are 32-bits now, people, keep up there. Briefly:

  OS_HeapSort
    bit 31 of r0 set for new API, r1 is full 32-bit address
    flags move from r1 bits 31-29 to r0 bits 30-28

  OS_ReadLine
    bit 31 of r1 set for new API, r0 is full 32-bit address
    flags move from bits 31,30 of r0 to bits 30,29 of r1

  OS_SubstituteArgs
    bit 31 of r2 set for new API, r0 is full 32-bit address
    flag moves from bit 31 of r0 to bit 30 of r2

Tested on Risc PC and briefly on Customer A 2

Ta

Version 5.35, 4.79.2.41. Tagged as 'Kernel-5_35-4_79_2_41'
parent 6be01a33
......@@ -13,12 +13,12 @@
GBLS Module_ComponentPath
Module_MajorVersion SETS "5.35"
Module_Version SETA 535
Module_MinorVersion SETS "4.79.2.40"
Module_Date SETS "22 Jun 2001"
Module_ApplicationDate2 SETS "22-Jun-01"
Module_ApplicationDate4 SETS "22-Jun-2001"
Module_MinorVersion SETS "4.79.2.41"
Module_Date SETS "26 Jun 2001"
Module_ApplicationDate2 SETS "26-Jun-01"
Module_ApplicationDate4 SETS "26-Jun-2001"
Module_ComponentName SETS "Kernel"
Module_ComponentPath SETS "RiscOS/Sources/Kernel"
Module_FullVersion SETS "5.35 (4.79.2.40)"
Module_HelpVersion SETS "5.35 (22 Jun 2001) 4.79.2.40"
Module_FullVersion SETS "5.35 (4.79.2.41)"
Module_HelpVersion SETS "5.35 (26 Jun 2001) 4.79.2.41"
END
......@@ -4,19 +4,19 @@
*
*/
#define Module_MajorVersion_CMHG 5.35
#define Module_MinorVersion_CMHG 4.79.2.40
#define Module_Date_CMHG 22 Jun 2001
#define Module_MinorVersion_CMHG 4.79.2.41
#define Module_Date_CMHG 26 Jun 2001
#define Module_MajorVersion "5.35"
#define Module_Version 535
#define Module_MinorVersion "4.79.2.40"
#define Module_Date "22 Jun 2001"
#define Module_MinorVersion "4.79.2.41"
#define Module_Date "26 Jun 2001"
#define Module_ApplicationDate2 "22-Jun-01"
#define Module_ApplicationDate4 "22-Jun-2001"
#define Module_ApplicationDate2 "26-Jun-01"
#define Module_ApplicationDate4 "26-Jun-2001"
#define Module_ComponentName "Kernel"
#define Module_ComponentPath "RiscOS/Sources/Kernel"
#define Module_FullVersion "5.35 (4.79.2.40)"
#define Module_HelpVersion "5.35 (22 Jun 2001) (4.79.2.40)"
#define Module_FullVersion "5.35 (4.79.2.41)"
#define Module_HelpVersion "5.35 (26 Jun 2001) (4.79.2.41)"
......@@ -88,6 +88,7 @@ EntryNo_HAL_MachineID # 1
EntryNo_HAL_ControllerAddress # 1
EntryNo_HAL_HardwareInfo # 1
EntryNo_HAL_SuperIOInfo # 1
EntryNo_HAL_CleanerSpace # 1
EntryNo_HAL_UARTPorts # 1
EntryNo_HAL_UARTStartUp # 1
......@@ -115,15 +116,15 @@ EntryNo_HAL_Reset # 1
; NVMemory
NVMemoryFlag_None * 0
NVMemoryFlag_MaybeIIC * 1
NVMemoryFlag_IIC * 2
NVMemoryFlag_HAL * 3
NVMemoryFlag_Provision * 7 ; mask for provision
NVMemoryFlag_ProtectAtEnd * 1:SHL:8 ; Protected region at end
NVMemoryFlag_Deprotectable * 1:SHL:9
NVMemoryFlag_LowRead * 1:SHL:10 ; locations 0-15 are readable
NVMemoryFlag_LowWrite * 1:SHL:11 ; locations 0-15 are writeable
NVMemoryFlag_None * 0
NVMemoryFlag_MaybeIIC * 1
NVMemoryFlag_IIC * 2
NVMemoryFlag_HAL * 3
NVMemoryFlag_Provision * 7 ; mask for provision
NVMemoryFlag_ProtectAtEnd * 1:SHL:8 ; Protected region at end
NVMemoryFlag_Deprotectable * 1:SHL:9
NVMemoryFlag_LowRead * 1:SHL:10 ; locations 0-15 are readable
NVMemoryFlag_LowWrite * 1:SHL:11 ; locations 0-15 are writeable
; IIC
......
......@@ -235,11 +235,12 @@ ZeroPage * &00000000
[ HAL
; Sort out 26/32 bit versions
SVCStackSize * 32*1024
IRQStackSize * 8*1024
ABTStackSize * 8*1024
UNDStackSize * 8*1024
SVCStackSize * 32*1024
IRQStackSize * 8*1024
ABTStackSize * 8*1024
UNDStackSize * 8*1024
KbuffsMaxSize * 64*1024
DCacheCleanSize * 256*1024 ;should be multiple of 64k
AplWorkMaxSize * &01C00000 ; 28M - temporary (need to decide this at boot time)
ScreenEndAdr * &24000000 ; temporary - run time allocate
......
......@@ -508,6 +508,7 @@ DoTheL2PThack
BL Init_ARMarch ; corrupts a1 and ip
MOV a1, a4
MSREQ CPSR_c, #F32_bit+I32_bit+UND32_mode ; Recover the soft copy of the CR
MOVEQ v5, sp
ARM_read_control v5, NE
[ CacheOff
ORR v5, v5, #MMUC_M ; MMU on
......@@ -518,6 +519,7 @@ DoTheL2PThack
]
MMUon_instr
ARM_write_control v5
MOVEQ sp, v5
MSREQ CPSR_c, #F32_bit+I32_bit+SVC32_mode
MOV ip, #0 ; junk MMU-off contents of I-cache
......@@ -670,7 +672,26 @@ MMUon_nol1ptoverlap
STR v5, [v8, #RAMLIMIT]
STR v7, [v8, #MaxCamEntry]
; Set up the data cache cleaner space if necessary (eg. for StrongARM core)
CallHAL HAL_CleanerSpace
CMP a1, #-1 ;-1 means none needed (HAL only knows this if for specific ARM core eg. system-on-chip)
BEQ %FT20
LDR a2, =DCacheCleanAddress
LDR a3, =(AP_None * L2_APMult) + L2_C + L2_B ; ideally, svc read only, user none but hey ho
ASSERT DCacheCleanSize = 4*&10000 ; 64k of physical space used 4 times (allows large page mapping)
MOV a4, #&10000
MOV ip, #4
SUB sp, sp, #5*4 ;room for a1-a4,ip
10
STMIA sp, {a1-a4, ip}
BL Init_MapIn
LDMIA sp, {a1-a4, ip}
SUBS ip, ip, #1
ADD a2, a2, #&10000
BNE %BT10
ADD sp, sp, #5*4
20
; Allocate the CAM
LDR a3, [v8, #SoftCamMapSize]
LDR a2, =(AP_None * L2_APMult) + L2_C + L2_B
......@@ -1384,9 +1405,9 @@ CPR_skipped
MOV r1, #&80
STRB r1, [r0] ; flag the fact that RAM cleared
MSR CPSR_c, #F32_bit + FIQ32_mode ; retrieve the MMU control register
MSR CPSR_c, #F32_bit + UND32_mode ; retrieve the MMU control register
MOV r0, #ZeroPage ; soft copy
STR v5, [r0, #MMUControlSoftCopy]
STR sp, [r0, #MMUControlSoftCopy]
MSR CPSR_c, #F32_bit + SVC32_mode
MOV pc, lr
......
......@@ -18,11 +18,14 @@
; HeapSort routine. Borrowed from Knuth by Tutu. Labels h(i) correspond to
; steps in the algorithm.
; In r0 = n
;mjs June 2001, API adjusted to allow for full 32-bit addresses
; In r0 = n (maximum of 268,435,455), and flags in top 4 bits
; bit 31 *must* be set, flagging new API to allow full 32-bit addresses
; bit 30 set -> use r4,r5 on postpass
; bit 29 set -> build (r1) from r4,r5 in prepass
; bit 28 set -> use r6 as temp slot
; r1 = array(n) of word size objects (r2 determines type)
; bit 31 set -> use r4,r5 on postpass
; bit 30 set -> build (r1) from r4,r5 in prepass
; bit 29 set -> use r6 as temp slot
; r2 = address of comparison procedure
; Special cases:
; 0 -> treat r(n) as array of cardinal
......@@ -32,9 +35,17 @@
; 4 -> treat r(n) as array of char* (case insensitive)
; 5 -> treat r(n) as array of char* (case sensitive)
; r3 = wsptr for comparison procedure (only needed if r2 > 5)
; r4 = array(n) of things (only needed if r1 & 0xC0000000)
; r4 = array(n) of things (only needed if r0 & &60000000)
; r5 = sizeof(element) ( --------- ditto ---------- )
; r6 = address of temp slot (only needed if r5 > 16K or r1 & 0x20000000)
; r6 = address of temp slot (only needed if r5 > 16K or r0 & &10000000)
;For backward compatibility, supports old API assuming addresses are safe
;(specifically, that address in r1 does not have any of top 3 bits set)
;
;The old API uses bits 31-29 of r1 to mean the equivalent of bits 30-28 of r0
;as defined above. Just to make this more confusing, the old API always behaves
;as if bit 31 of r1 mirrors bit 30 (ie. bit 30 set forces bit 31 set, see PRM 5a-662),
;so we preserve this for old API, but do originally intended thing for new API.
; r10-r12 trashable
......@@ -61,7 +72,9 @@ hs_r RN r11
HeapSortRoutine ROUT
CMP r0, #2 ; 0 or 1 elements? No data moved either
BIC r10, r0, #&F0000000 ; n (zapping flag bits)
CMP r10, #2 ; 0 or 1 elements? No data moved either
ExitSWIHandler LO ; VClear in lr and psr
Push "r0-r3, hs_array, hs_procadr, hs_i, hs_j, hs_K, hs_R, lr"
......@@ -71,8 +84,14 @@ HeapSortRoutine ROUT
[ False
STR r0, ndump ; For debugging porpoises
]
TST r1, #1 :SHL: 30 ; Are we to build the pointer array?
BIC r1, r1, #2_111 :SHL: 29 ; Take out flag bits for now
TST r0, #&80000000 ; test old/new API
MOVNE r10, r0 ; new, flags are in r0
BICNE r0, r0, #&F0000000 ; zap new flags
MOVEQ r10, r1, LSR #1 ; old, flags are in r1, 1 bit to left
BICEQ r1, r1, #&E0000000 ; zap old flags
TST r10, #&20000000 ; Are we to build the pointer array?
BEQ %FT01
; Build array of pointers to data blocks for the punter if he desires this
......@@ -87,7 +106,6 @@ HeapSortRoutine ROUT
SUBS r10, r10, #1
BNE %BT00
01 SUB hs_array, r1, #4 ; HeapSort assumes r(1..n) not (0..n-1)
MOV hs_procadr, r2 ; Put proc address where we need it
......@@ -172,15 +190,22 @@ h8 STR hs_R, [hs_array, hs_i, LSL #2] ; R(i) = R
; Array now sorted into order
90 LDR r14, [sp, #4*1] ; r1in
TST r14, #1 :SHL: 30
90 LDR r14, [sp, #4*0] ; r0in
LDR r2, [sp, #4*1] ; r1in
TST r14, #&80000000 ; check for old/new API
ANDEQ r8, r2, #&E0000000
ORREQ r14, r14, r8, LSR #1 ; old, munge old flag bits into r14
BICEQ r2, r2, #&E0000000 ; clear from r2
ORREQ r14, r14, #&40000000 ; ho hum fudge to make old bit 31 mirror
TSTEQ r14, #&20000000 ; old bit 30 if using old API (behave as errata
BICEQ r14, r14, #&40000000 ; in PRM 5a-662)
TST r14, #&40000000 ; check for postpass
BEQ %FA99 ; [no shuffle required, exit]
; Reorder the blocks according to the sorted array of pointers
BIC r2, r14, #2_111 :SHL: 29 ; r2 -> list of pointers
; keep r14 ok for below
ADD r1, sp, #4*4
LDMIA r1, {r1, r8, r9} ; r4,r5,r6in
; r1 -> list of blocks
......@@ -190,9 +215,9 @@ h8 STR hs_R, [hs_array, hs_i, LSL #2] ; R(i) = R
DREG r8, "sizeof(element) "
]
MOV r3, r2 ; r3 -> first item of current cycle
LDR r0, [sp, #0*4] ; r0 = n
BIC r0, r14, #&F0000000 ; r0 = n
ADD r6, r2, r0, LSL #2 ; r6 -> end of array of pointers
TST r14, #1 :SHL: 29 ; punter forcing use of his temp slot?
TST r14, #&10000000 ; punter forcing use of his temp slot?
BNE %FT94 ; fine by me!
CMP r8, #ScratchSpaceSize
LDRLS r9, =ScratchSpace ; r9 -> temp slot (normally ScratchSpc)
......
......@@ -17,38 +17,45 @@
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; VecRdLine - Read line from input stream (OSWORD 0 equivalent)
;mjs June 2001, API redefined to support full 32-bit addresses
; In r0 -> buffer for characters
; r1 = max length of line (excluding carriage return)
; r1 = max length of line (excluding carriage return), and flags in top 3 bits
; bit 31 *must* be set to indicate new API supporting 32-bit addresses
; bit 30 set means don't reflect characters that don't go in the buffer
; bit 29 set means reflect with the character in R4
; r2 = lowest character put into buffer
; r3 = highest character put into buffer
; r4 = character to echo if r1 bit 29 is set
; wp -> OsbyteVars
; Out r1 = length of line (excluding carriage return)
; Out r0, r2, r3 corrupted
; r1 = length of line (excluding carriage return)
; C=0 => line terminated by return (CR or LF)
; C=1 => line terminated by ESCAPE
; ReadLine: suggested extensions (available RSN)
;
; are 1) stopping it reflecting control characters/characters not put in the
; buffer
; 2) making any reflection print a given character (for hiding passwords
; etc
;
; So, definition is :
;
; Top byte R0 contains flags :
; Bit 31 set means don't reflect characters that don't go in the buffer
; Bit 30 set means reflect with the character in R4
; For backward compatibility, supports old API, assuming address in r0 is
; safe (has top 2 bits clear). The old API uses bits 31,30 of r0 to
; specify flags as in bits 30,29 of r1 above.
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
VecRdLine ROUT
Push "R4-R7"
AND R7, R0, #&C0000000 ; extract flags
TST R1, #&80000000 ; check for old API
ANDEQ R7, R0, #&C0000000
ORREQ R1, R1, R7, LSR #1
ORREQ R1, R1, #&80000000
BICEQ R0, R0, #&C0000000 ; if so, munge into new API
AND R7, R1, #&E0000000 ; extract flags
AND R4, R4, #&FF
ORR R7, R7, R4 ; got flags, potential echo byte in R7
BIC R4, R0, #ARM_CC_Mask-3 ; R4 -> buffer
BIC R1, R1, #&E0000000 ; zap flags
MOV R4, R0 ; R4 -> buffer
MOV R6, #0 ; R6 = index into buffer
STRB R6, PageModeLineCount ; reset page lines
......@@ -112,10 +119,10 @@ VecRdLine ROUT
CMPCS R3, R0 ; and char <= max ?
ADDCS R6, R6, #1 ; if so, then inc pointer
BCS %FT80
CMP R7, #0 ; no reflection
BMI %BT10 ; of non-entered chars
TST R7, #&40000000 ; no reflection
BNE %BT10 ; of non-entered chars
80 TST R7, #1:SHL:30
80 TST R7, #&20000000
ANDNE R0, R7, #&FF ; echo char -> R0
B %BT05 ; echo character
......
......@@ -16,20 +16,32 @@
;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; SubstituteArgs
;
; mjs June 2001, API redefined to allow for full 32-bit addresses
;
; in: R0 -> arglist (space delimited args, terminated by 10,13,0)
; top bit set => don't append unused part of line
; R1 -> buffer
; R2 = bufflen
; R2 = bufflen, plus flags in top 2 bits
; bit 31 *must* be set to indicate new API, supporting full 32-bit addresses
; bit 30 set => don't append unused part of line
; R3 -> string to mangle
; R4 = no of chars in $R3
; out: R2 = no of chars in buffer
; For backward compatibility, supports old API assuming addresses
; safe (top bit of address in r0 clear). The old API uses r0
; bit 31 to specify flag as in bit 30 of r2 above.
;
XOS_SubstituteArgs_code ROUT
WritePSRc SVC_mode, R12 ; enable IRQs
Push "R0-R8, lr"
BIC r0, r0, #&80000000
TST R2, #&80000000 ; check for old API
BICEQ R0, R0, #&80000000 ; zap old API flag bit from address if so
ADD R8, R4, R3
; try and get parameter positions.
......@@ -73,7 +85,8 @@ XOS_SubstituteArgs_code ROUT
MOV R6, #0 ; count.
MOV R7, #0 ; highest param used.
LDR R2, [stack, #4*2]
LDR R2, [stack, #4*2] ;r2in
BIC R2, R2, #&C0000000 ;buffer length
37 BL suba_getchar
BEQ %FT41
CMP R5, #"%"
......@@ -140,10 +153,13 @@ PCStarTerminates
41 CMP r7, #11
LDREQ r12, [r4, #10*4] ; no more to copy
BEQ %FT42
LDR r0, [stack]
CMP r0, #0
LDRPL R12, [R12, R7, LSL #2] ; ptr to rest of command line : copy
LDRMI r12, [r4, #10*4] ; caller wants no appending.
LDR r0, [stack, #4*2] ; r2in
TST r0, #&80000000 ; check for old/new API
LDREQ r0, [stack, #4*0] ; if old, get r0in
MOVEQ r0, r0, LSR #1 ; and shift r0in bit 31 (old flag) to bit 30 (new flag)
TST r0, #&40000000
LDREQ R12, [R12, R7, LSL #2] ; ptr to rest of command line : copy
LDRNE r12, [r4, #10*4] ; caller wants no appending.
42 LDRB R5, [R12], #1
BL suba_addchar
BL suba_chktrm
......
......@@ -480,6 +480,7 @@ oqa_quicksilvertime_alias
BL GetOscliBuffer ; gives buffer ptr in R5, ID in R6
MOV R1, R5
MOV R2, #OscliBuffSize
ORR R2, R2, #&80000000 ; new API (allows for 32-bit addresses)
SWI XOS_SubstituteArgs
BVS AliasOscliTooLong
......
......@@ -108,6 +108,7 @@ OsWord00 ROUT
LDRB R2, [R1, #3] ; lo limit
LDRB R3, [R1, #4] ; hi limit
LDRB R1, [R1, #2] ; length of buffer
ORR R1, R1, #&80000000 ; use the new API, for modernity
SWI XOS_ReadLine
WordReturnV VS
......
......@@ -67,6 +67,7 @@ CLILOP ROUT
SWI OS_WriteN
LDR R0, =GeneralMOSBuffer
LDR R1, =?GeneralMOSBuffer-1
ORR R1, R1, #&80000000 ; new API (allows full 32-bit buffer address)
MOV R2, #" "
MOV R3, #255
SWI OS_ReadLine
......
......@@ -1265,8 +1265,9 @@ Build_Code ALTENTRY
10 BLVC LineNumberPrint ; Escape is tested for on OS_ReadLine.Err below
BVS UtilityExitCloseR1_256
MOV r0, sp ; Get a line from Joe Punter
MOV r1, #256-1 ; -1 for terminator
MOV r0, sp ; Get a line from Joe Punter
MOV r1, #256-1 ; -1 for terminator
ORR r1, r1, #&80000000 ; yep, new API
MOV r2, #" "
MOV r3, #&FF
SWI XOS_ReadLine
......
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